ELECTRONIC
DEVICES
& CIRCUITS
second edition
David A. Bell
Electronic Devices
and Circuits
Electronic Devices
and Circuits
2nd Edition
David A. Bell
iambton College of
Applied Arts and Technology
Sarnia , Ontario , Canada
Reston Publishing Company, Inc., Reston, Virginia
A Prentice-Hall Company
Library of Congress Cataloging in Publication Data
Bell, David A.
Electronic devices and circuits.
Includes index.
1. Semiconductors. 2. Electronic circuits.
3. Electronic apparatus and appliances. I. Title.
TK7871.85.B3785 1980 621.3815 79-22957
ISBN 0-8359-1634-0
© 1980 by
Reston Publishing Company, Inc.
A Prentice-Hall Company
Reston, Virginia 22090
All rights reserved. No part of this book may be
reproduced in any way, or by any means, without
permission in writing from the publisher.
10 98765432
Printed in the United States of America
to my wife Evelyn
Contents
Preface
XV
Chapter 1
BASIC SEMICONDUCTOR THEORY 1
1-1
Introduction 1
1-2
The Atom 1
1-3
Electron Orbits and Energy Levels 3
1-4
Energy Bands 4
1-5
Conduction in Solids 5
1-6
Conventional Current and Electron Flow 6
1-7
Bonding Forces Between Atoms 7
1-8
Conductors, Insulators, and Semiconductors 8
1-9
Semiconductor Doping 9
1-10
Effects of Heat and Light 1 1
1-11
Drift Current and Diffusion Current 12
Glossary of Important Terms 13
Review Questions 15
vii
viii
Contents
Chapter 2
pn-JUNCTION THEORY 16
2-1
Introduction 16
2-2
The /m-Junction 16
2-3
Reverse Biased Junction 19
2-4
Forward Biased Junction 21
2-5
Temperature Effects 23
2-6
Junction Capacitance 25
2-7
Junction Equivalent Circuit 25
Glossary of Important Terms 26
Review Questions 27
Chapter 3
The Semiconductor Diode 29
3-1
Introduction 29
3-2
Diode Symbol and Appearance 29
3-3
Diode Fabrication 31
3-4
Diode Characteristics and Parameters 32
3-5
Graphical Analysis of Diode Circuit 33
3-6
Diode Piecewise Linear Characteristics 38
3-7
Diode Equivalent Circuit 39
3-8
Diode Data Sheet 40
3-9
Half-Wave Rectification 43
3-10
Full-Wave Rectification 49
3-11
Diode Switching Time and Frequency Response
3-12
Diode Logic Circuits 55
3-13
Diode Clipper Circuits 56
3-14
Voltage Multiplier Circuit 58
Glossary of Important Terms 60
Review Questions 61
Problems 62
Chapter 4
The Junction Transistor 65
4-1
Introduction 65
4-2
Transistor Operation 65
4-3
Transistor Currents 70
4-4
Transistor Symbols and Voltages 73
4-5
Common Base Characteristics 74
4-6
Common Emitter Characteristics 78
4-7
Common Collector Characteristics 81
4-8
Transistor T-Equivalent Circuit and r-Parameters 83
4-9
A-Parameters 84
Glossary of Important Terms 89
Review Questions 90
Problems 91
Chapter 5
Transistor Biasing 93
5-1
Introduction 93
5-2
The dc Load Line and Bias Point
94
5-3
Fixed Current Bias 98
5-4
Collector-to-Base Bias 100
5-5
Emitter Current Bias (or Self Bias)
102
5-6
Comparison of Basic Bias Circuits
107
5-7
Thermal Stability 107
5-8
ac Bypassing and the ac Load Line
Glossary of Important Terms 113
Review Questions 114
Problems 114
110
Chapter 6 Basic Transistor Circuits 116
6-1 Introduction 116
6-2 Common Emitter Circuit 116
6-3 Common Emitter A-parameter Analysis 1 1 8
6-4 Common Collector Circuit 125
6-5 Common Collector ^-Parameter Analysis 126
6-6 Common Base Circuit 131
6-7 Common Base A-Parameter Analysis 132
6-8 Cascaded Common Emitter Circuits 139
Glossary of Important Terms 141
Review Questions 141
Problems 142
Chapter 7 Transistor and Integrated Circuit Fabrication 143
7-1 Introduction 143
7-2 Effects of Transistor Construction on Electrical
Performance 143
7-3 Processing of Semiconductor Materials 144
7-4 Transistor Fabrication 146
7-5 Integrated Circuit Fabrication 150
7-6 Integrated Circuit Components 152
7-7 Transistor and Integrated Circuit Packaging 154
Glossary of Important Terms 156
Review Questions 157
Chapter 8 Transistor Specifications and Performance 158
8-1 Introduction 158
8-2 The Transistor Data Sheet 158
ix
Contents
X
Contents
8-3 Power Dissipation 163
8-4 Decibels and Frequency Response 165
8-5 Miller Effect 170
8-6 Transistor Circuit Noise 171
8-7 Transistor Switching 175
Glossary of Important Terms 178
Review Questions 180
Problems 180
Chapter 9 Basic Multistage and Integrated Circuit Amplifiers 182
9-1
Introduction 182
9-2
Capacitor-Coupled Two-Stage Circuit
183
9-3
Direct Coupled Two-Stage Circuit 188
9-4
The Differential Amplifier 192
9-5
IC Differential Amplifiers 200
9-6
Basic IC Operational Amplifier Circuits
204
9-7
Transformer Coupled Class A Amplifier
211
9-8
Transformer Coupled Class B and Class AB Circuits 216
9-9
Multistage Emitter Followers 222
Glossary of Important Terms 226
Review Questions 226
Problems 228
Chapter 10 Basic Sinusoidal Oscillators 230
10-1 Introduction 230
10-2 Phase-Shift Oscillator 230
10-3 Colpitts Oscillator 234
10-4 Hartley Oscillator 237
10-5 Wein Bridge Oscillator 240
Glossary of Important Terms 243
Review Questions 243
Problems 244
Chapter 11 Zener Diodes 245
11-1
Introduction 245
11-2
Zener and Avalanche Breakdown
245
11-3
Zener Diode Characteristic and Parameters 247
11-4
Compensated Reference Diodes
251
11-5
Zener Diode Voltage Regulator
252
11-6
Regulator With Reference Diode
257
11-7
Other Zener Diode Applications
Glossary of Important Terms 259 ■
Review Questions 260
Problems 261
257
Chapter 12 Field Effect Transistors 262
12-1 Introduction 262
12-2 Principle of the n-Channel JFET 262
12-3 Characteristics of n-Channel JFET 264
12-4 The /^-Channel JFET 268
12-5 JFET Data Sheet and Parameters 269
12-6 JFET Construction 276
12-7 FET Equivalent Circuit 278
12-8 The MOSFET 278
12-9 The V-MOSFET 282
Glossary of Important Terms 285
Review Questions 287
Problems 287
xi
Contents
Chapter 13 FET Biasing 289
13-1 Introduction 289
13-2 dc Load Line and Bias Point 289
13-3 Spread of Characteristics and Fixed Bias Circuit 291
13-4 Self-bias 293
13-5 Self-bias with External Voltage 296
13-6 Design of FET Bias Circuits 298
13-7 Biasing MOSFETS 300
Glossary of Important Terms 303
Problems 303
Chapter 14 Basic FET Circuits 308
14-1 Introduction 308
14-2 The Common Source Circuit 308
14-3 ac Analysis of Common Source Circuit 310
14-4 The Common Drain Circuit 313
14-5 ac Analysis of Common Drain Circuit 315
14-6 The Common Gate Circuit 318
14-7 ac Analysis of the Common Gate Circuit 319
14-8 BI-FET and BI-MOS Circuits 322
Glossary of Important Terms 325
Review Questions 325
Problems 325
Chapter 15 The Tunnel Diode 327
15-1 Introduction 327
15-2 Theory of Operation 327
15-3 Tunnel Diode Symbol, Characteristics, and Parameters 332
xii
15-4
Piecewise Linear Characteristics 333
Contents
15-5
Tunnel Diode Equivalent Circuit 334
15-6
Tunnel Diode Parallel Amplifier 335
15-7
Gain Formula For a Parallel Amplifier 337
15-8
Practical Parallel Amplifier Circuit 338
Glossary of Important Terms 341
Review Questions 342
Problems 342
Chapter 16 The Silicon Controlled Rectifier 344
16-1 Introduction 344
16-2 SCR Operation 344
16-3 SCR Characteristics and Parameters 346
16-4 SCR Specifications 348
16-5 SCR Control Circuits 349
16-6 The TRIAC and DIAC 354
16-7 Other Four-Layer Devices 355
Glossary of Important Terms 360
Review Questions 362
Problems 362
Chapter 17 The Unijunction Transistor 364
17-1 Introduction 364
17-2 Theory of Operation 364
17-3 UJT Characteristics 366
17-4 UJT Parameters and Specifications 367
17-5 UJT Relaxation Oscillator 371
17-6 UJT Control of SCR 374
17-7 Programmable Unijunction Transistor 375
Glossary of Important Terms 377
Review Questions 378
Problems 378
Chapter 18 Optoelectronic Devices
380
18-1
Introduction 380
18-2
Light Units 381
18-3
Photomultiplier Tube 382
18-4
The Photoconductive Cell 384
18-5
The Photodiode 388
18-6
The Solar Cell 392
18-7
The Phototransistor and Photodarlington 394
18-8
The Photofet 397
18-9
Light-Emitting Diodes 398
18-10
Liquid Crystal Displays (LCD)
401
18-11
Gas Discharge Displays
404
18-12
Optoelectronic Couplers
405
18-13
Laser Diode 407
Glossary of Important Terms
409
Review Questions 410
Problems 411
xiii
Contents
Chapter 19 Miscellaneous Devices 414
19-1 Piezoelectricity 414
19-2 Piezoelectric Crystals 414
19-3 Synthetic Piezoelectric Devices 421
19-4 Voltage- Variable Capacitor Diodes 422
19-5 Thermistors 427
19-6 Lambda Diode 432
Glossary of Important Terms 433
Review Questions 434
Problems 435
Chapter 20 Electron Tubes 437
20-1 Introduction 437
20-2 The Vacuum Diode 438
20-3 The Vacuum Triode 441
20-4 Triode Characteristics 442
20-5 Triode Parameters 445
20-6 Common Cathode Circuit 447
20-7 ac Analysis of Common Cathode Circuit 449
20-8 Common Plate Circuit 453
20-9 Common Grid Circuit 454
20-10 Triode Biasing Methods 454
20- 1 1 The Tetrode Tube 457
20-12 The Pentode 460
20-13 The Variable-Mu or Remote Cutoff Pentode 462
20-14 The Cathode Ray Tube 463
Glossary of Important Terms 471
Review Questions 473
Problems 475
Appendix 1 Typical Standard Resistor Values 477
Appendix 2 Typical Standard Capacitor Values 478
Answers to Problems 479
Index 485
Preface
This is the second edition of Fundamentals of Electronic Devices , now
renamed Electronic Devices and Circuits to more correctly describe the contents
of the book. As in the first edition, my objectives are to clearly explain the
operation of all important electronic devices in general use today and to give
the reader a thorough understanding of the characteristics, parameters, and
circuit applications of each device. In addition, I attempt to show a basic
approach to designing each device into practical circuits.
The book is intended for use in electronics technology courses, whether
two-, three-, or four-year courses. It should also prove useful as a reference
handbook for practicing technicians, technologists, and engineers.
The text commences with the study of basic semiconductor theory and
/^-junction theory which is essential for an understanding of all solid-state
devices. Each different device is then treated in appropriate depth, begin-
ning, of course, with the semiconductor diode, then the bipolar transistor.
Transistor bias circuits, single-stage amplifiers, multistage amplifiers, and
oscillator circuits are all covered. Discrete component circuit coverage and
xv
xv i
Preface
integrated circuit applications are combined. The integrated circuit opera-
tional amplifier and its basic applications are explained in the chapters on
multistage amplifiers and oscillators.
Although useful background information for each device is included in
the book, every effort has been made to eliminate unnecessary material. For
example, transistor and integrated circuit fabrication techniques are covered
only from the point of view of how device performance is affected.
As well as bipolar transistors and integrated circuits, other devices
covered include: Zener diode, JFET, MOSFET, VMOS FET, tunnel diode,
SCR, UJT, PUT, photoconductive cell, solar cell, phototransistor, LED,
LCD, piezoelectric crystal, WC diode, and thermistor. Since electron tubes
are still in wide use in existing equipment, the final chapter covers its varied
forms: vacuum diode, triode, tetrode, pentode, and, of course, the very
important cathode-ray tube.
Throughout the book many examples are employed to explain practi-
cal applications of each device. Instead of rigorous analysis methods, practi-
cal approximations are used wherever possible, and the origin of each
approximation is explained. Manufacturers’ data sheets are referred to
where appropriate. Problems are provided at each chapter end, and answers
to all problems are found in the back of the book. Glossaries of important
terms are also included at the end of each chapter.
The mathematics level throughout the text does not go beyond alge-
braic equations and logarithms, simply because no higher math is necessary
to fulfill the purpose of the book. It is expected that students will have
already studied basic electricity.
David A. Bell
Basic
Semiconductor
Theory
The function of an electronic device is to control the movement of electrons.
The first step in a study of such devices is to understand the. electron (or
what it is believed to be), and how it is associated with the other components
of the atom. After such an understanding is reached the bonding forces
holding atoms together within a solid and the movement of electrons from
one atom to another must be investigated. This leads to an understanding of
the differences between conductors, insulators, and semiconductors.
The atom is believed to consist of a central nucleus surrounded by
orbiting electrons (see Fig. 1-1). Thus, it may be compared to a planet with
satellites in orbit around it. Just as satellites are held in orbit by an attractive
force of gravity due to the mass of the planet, so each electron is held in orbit
by an electrostatic force of attraction between it and the nucleus.
The electrons each have a negative electrical charge of 1.602X 10 -19
coulombs (C), and some particles within the nucleus have a positive charge of
the same magnitude. Since opposite charges attract, a force of attraction
CHAPTER
1
1-1
Introduction
1-2
The Atom
1
2
Basic
Semiconductor
Theory
Orbiting
electrons
Gravitational force = Centrifugal force
Atomic
nucleus
Electron
0-r}f
(b) Forces on satellite
orbiting a planet
Electrostatic force = Centrifugal force
(c) Forces on electrons
orbiting a nucleus
Figure 1-1. Planetary atom.
exists between the oppositely charged electron and nucleus. As in the case of
the satellites, the force of attraction is balanced by the centrifugal force due
to the motion of the electrons around the nucleus [Fig. l-l(b) and (c)].
Compared to the mass of the nucleus, electrons are relatively tiny
particles of almost negligible mass. In fact, we may think of them simply as
little particles of negative electricity having no mass at all.
The nucleus of an atom is largely a cluster of two types of particles,
protons and neutrons. Protons have a positive electrical charge, equal in
magnitude (but opposite in polarity) to the negative charge on an electron.
A neutron has no charge at all. Protons and neutrons each have masses
about 1800 times the mass of an electron. For a given atom, the number of
protons in the nucleus normally equals the number of orbiting electrons.
Since the protons and orbital electrons are equal in number and equal
and opposite in charge, they neutralize each other electrically. For this
reason, all atoms are normally electrically neutral. If an atom loses an
electron, it has lost some negative charge. Therefore, it becomes positively
charged and is referred to as a positive ion. Similarly, if an atom gains an
additional electron, it becomes negatively charged and is termed a negative ion.
The differences between atoms consist largely of dissimilar numbers
and arrangements of the three basic types of particles. However, all electrons
are identical, as are all protons and all neutrons. An electron from one atom
could replace an electron in any other atom. Different materials are made
up of different types of atoms, or differing combinations of several types of
atoms.
The number of protons (or electrons) in an atom is referred to as the
atomic number of the atom. The atomic weight is approximately equal to the
total number of protons and neutrons in the nucleus of the atom. The atom
of the semiconductor element silicon has 14 protons and 14 neutrons in its
nucleus, as well as 14 orbital electrons. Therefore, the atomic number for
silicon is 14, and its atomic weight is approximately 28.
3
Electron
Orbits and
Energy Levels
Atoms may be conveniently represented by the two-dimensional dia-
grams shown in Fig. 1-2. It has been found that electrons can occupy only
certain orbital rings or shells at fixed distances from the nucleus, and that
each shell can contain only a particular number of electrons. The electrons
in the outer shell determine the electrical (and chemical) characteristics of
each particular type of atom. These electrons are usually referred to as
valence electrons. An atom may have its outer or valence shell completely filled
or only partially filled.
The atoms of two important semiconductors, silicon (Si) and germanium
(Ge), are illustrated in Fig. 1-2. It is seen that each of these atoms have four
electrons in a valence shell that can contain a maximum of eight. Thus, we
say that their valence shells have four electrons and four holes. A hole is
defined simply as an absence of an electron in a shell where one could exist.
Even though their valence shells have four holes, both silicon and
germanium atoms are still electrically neutral, because the total number of
orbital electrons equals the total number of protons in the nucleus.
1-3
Electron
Orbits and
Energy Levels
(a) Germanium atom (b) Silicon atom
Figure 1-2. Two-dimensional representation of silicon and germanium atoms.
4
Basic
Semiconductor
Theory
1-4
Energy Bands
The closer an electron is to the nucleus, the stronger are the forces that
bind it. Each shell has an energy level associated with it which represents the
amount of energy that would have to be supplied to extract an electron from
the shell. Since the electrons in the valence shell are farthest from the
nucleus, they require the least amount of energy to extract them from the
atom. Conversely, those electrons closest to the nucleus require the greatest
energy application to extract them from the atom.
The energy levels considered above are measured in electron volts (eV).
An electron volt is defined as the amount of energy required to move one
electron through a potential difference of one volt.
So far the discussion has concerned a system of electrons around one
isolated atom. The electrons of an isolated atom are acted upon only by the
forces within that atom. However, when atoms are brought closer together as
in a solid, the electrons come under the influence of forces from other atoms.
The energy levels that may be occupied by electrons merge into bands of
energy levels. Within any given material there are two distinct energy bands in
which electrons may exist, the valence band and the conduction band. Separating
these two bands is an energy gap in which no electrons can normally exist.
This gap is termed the forbidden gap. The valence band, conduction band,
and forbidden gap are shown diagrammatically in Fig. 1-3.
Electrons within the conduction band have become disconnected from
atoms and are drifting around within the material. Conduction band
electrons may be easily moved around by the application of relatively small
amounts of energy. Much larger amounts of energy must be applied to
extract an electron from the valence band or to move it around within the
valence band. Electrons in the valence band are usually in normal orbit
around a nucleus. For any given type of material, the forbidden gap may be
large, small, or nonexistent. The distinction between conductors, insulators,
and semiconductors is largely concerned with the relative widths of the
forbidden gap.
It is important to note that the energy band diagram is simply a
graphic representation of the energy levels associated with electrons. To
J- *-^Conduction band
^-Forbidden gap
Valence band
Energy
level
Figure 1-3. Energy band diagram.
repeat, those electrons in the valence band are actually in orbit around the
nucleus of an atom; those in the conduction band are drifting about in the
spaces between atoms.
Conduction occurs in any given material when an applied voltage
causes electrons within the material to move in a desired direction. This may
be due to one or both of two processes, electron motion and hole transfer. In
electron motion, free electrons in the conduction band are moved under the
influence of the applied electric field. Since electrons have a negative charge,
they are repelled from the negative terminal of the applied voltage, and
attracted toward the positive terminal. Hole transfer involves electrons
which are still attached to atoms, i.e., those in the valence band.
If some of the energy levels in the valence band are not occupied by
electrons, there are holes where electrons could exist. An electron may jump
from one atom to fill the hole in another atom. When it jumps, the electron
leaves a hole behind it, and we say that the hole has moved in the opposite
direction to the electron. In this way a current flows which may be said to be
due to hole movement.
In Fig. l-4(a), the applied potential causes an electron to jump from
atom^ to atom x. In doing so, it fills the hole in the valence shell of atom x,
and leaves a hole behind it in atom^ as shown in Fig. l-4(b). If an electron
now jumps from atom z , under the influence of the applied potential, and
fills the hole in the valence shell of atom y> it leaves a hole in atom z
[Fig. l-4(c)]. Thus, the hole has been caused to move from atom x to atomy
to atom z.
Holes may be thought of as positive particles, and as such they move
through an electric field in a direction opposite to that of the electrons; i.e.,
Figure 1-4. Conduction by hole transfer, (a) Electron jumps from atom y to atom x. (b) It
fills the hole in atom x and leaves a hole in atom y. (c) If an electron jumps from atom z
to atom y, it will leave a hole in atom z.
5
Conduction
in Solids
1-5
Conduction
in Solids
6
Basic
Semiconductor
Theory
1-6
Conventional
Current and
Electron Flow
positive particles are attracted toward the negative terminal of an applied
voltage. It is usually more convenient to think in terms of hole movement,
rather than in terms of electrons jumping from atom to atom.
Since the flow of electric current is constituted by the movement of
electrons in the conduction band and holes in the valence band, electrons
and holes are referred to as charge carriers . Each time a hole moves, an
electron must be supplied with sufficient energy to enable it to escape from
its atom. Free electrons require less application of energy than holes to move
them, because they are already disconnected from their atoms. For this
reason, electrons have greater mobility than holes.
The unit of electric current is the ampere (A). An ampere may be
defined as that current which flows when one coulomb of charge passes a
given point in one second. From this definition we can calculate the number
of electrons involved in a current of one ampere. Since the charge on one
electron is 1.602X 10“ 19 C, the number of electrons with a total charge of
1 G is 1/(1.602 X 10 _19 )«6.25 X 10 18 . When one microampere (/tA) flows
(i.e., 1 X 10 -6 A), electrons are passing at the rate of 6.25 X 10 12 per second,
or 1 pA = 6,250,000,000,000 electrons per second.
In the early days of electrical experimentation it was believed that a
positive charge represented an increased amount of electricity and that a
negative charge was a reduced quantity. Thus, it was assumed that current
flowed from positive to negative. This is a convention that remains in use
today even though current is now known to be a movement of electrons from
negative to positive (see Fig. 1-5).
Conventional current
direction
Electron motion
Atom
Electron
Figure 1-5. Conventional current direction is from positive to negative. Electron flow is
from negative to positive.
Current flow from positive to negative is referred to as the conventional
direction of current. Electron flow from negative to positive is known as the
direction of electron flow.
It is important to understand both conventional current direction and
electron flow. Every graphic symbol used to represent an electronic device
has an arrowhead which indicates conventional current direction. A con-
sequence of this is that electronic circuits are most easily explained by using
current flow from positive to negative. However, to understand how each
device operates, it is necessary to think in terms of electron movement.
7
Bonding Forces
Between Atoms
Whether a material is a conductor, a semiconductor, or an insulator
depends largely upon what happens to the outer-shell electrons when the
atoms bond themselves together to form a solid. In the case of copper, the
easily detached valence electrons are given up by the atoms. This creates a
great mass of free electrons (or electron gas ) drifting about through the spaces
between the copper atoms. Since each atom has lost a (negative) electron, it
becomes a positive ion. The electron gas is, of course, negatively charged;
consequently, an electrostatic force of attraction exists between the positive
ions and the electron gas. This is the bonding force that holds the material
together in a solid. In the case of copper and other metals, the bonding force
is termed metallic bonding or sometimes electron gas bonding . This type of
bonding is illustrated in Fig. l-6(a).
In the case of silicon, which has four outer-shell electrons and four
holes, the bonding arrangement is a little more complicated than for copper.
Atoms in a solid piece of silicon are so close to each other that the outer-shell
electrons behave as if they were orbiting in the valence shells of two atoms.
In this way each valence-shell electron fills one of the holes in the valence
shell of a neighboring atom. This arrangement, illustrated in Fig. l-6(b),
forms a bonding force known as covalent bonding. In covalent bonding every
valence shell of every atom appears to be filled, and consequently there are
no holes and no free electrons drifiting about within the material. The same
is true for germanium atoms. When semiconductor material is prepared for
device manufacture, the atoms within the material are aligned into a
definite three-dimensional pattern or crystal lattice. Each atom is covalently
bonded to the four surrounding atoms.
In some insulating materials, notably rubber and plastics, the bonding
process is also covalent. The valence electrons in these bonds are very
strongly attached to their atoms, so the possibility of current flow is virtually
zero. In other types of insulating materials, some atoms have parted with
outer-shell electrons, but these have been accepted into the orbit of other
atoms. Thus, the atoms are ionized ; those which gave up electrons have
become positive ions y and those which accepted the electrons become negative
ions. This creates an electrostatic bonding force between the atoms, termed
ionic bonding. The situation is illustrated in Fig. l-6(c), which shows how the
negative and positive ions may be arranged together in groups.
1-7
Bonding
Forces
Between
Atoms
Positive ions
O u o jf o
.°J .9 v
Qyoyo
(b) Covalent bonding
Shared valence
electrons
(a) Metallic bonding
Figure 1-6. Atomic bonding in conductors, semiconductors, and insulators.
1-8
Conductors,
Insulators,
and
Semi-
conductors
As seen in the energy band diagrams of Fig. 1-7, insulators have a wide
forbidden gap, semiconductors have a narrow forbidden gap, and conductors
have no forbidden gap at all. In the case of insulators, there are practically
no electrons in the conduction band of energy levels, and the valence band is
filled. Also, the forbidden gap is so wide [Fig. 1 -7(a)] that it would require
the application of very large amounts of energy (approximately 6 eV) to
cause an electron to cross from the valence band to the conduction band.
Therefore, when a voltage is applied to an insulator, conduction cannot
occur either by electron motion or hole transfer.
For semiconductors at a temperature of absolute zero ( — 273.15°C) the
valence band is usually full, and there may be no electrons in the conduction
band. However, as shown in Fig. l-7(b), the semiconductor forbidden gap is
very much narrower than that of an insulator, and the application of small
amounts of energy (1.2 eV for silicon and 0.785 eV for germanium) can raise
electrons from the valence band to the conduction band. Sufficient thermal
8
(a) Insulator (b) Semiconductor (c) Conductor
Figure 1-7. Energy band diagrams for insulator, semiconductor, and conductor.
9
Semiconductor
Doping
energy for this purpose is made available when the semiconductor is at room
temperature. If a potential is applied to the semiconductor, conduction
occurs both by electron movement in the conduction band and by hole
transfer in the valence band.
In the case of conductors [Fig. 1 -7(c)] there is no forbidden gap, and
the valence and conduction energy bands overlap. For this reason, very large
numbers of electrons are available for conduction, even at extremely low
temperatures.
Typical resistance values for a 1 -cubic-centimeter sample are
Conductor lCT 6 fi/cm 3
Semiconductor 1 0 £2/ cm 3
Insulator 10 ,4 S2/cm 3
Pure semiconductor material is referred to as intrinsic material. Before
semiconductor material can be used for device manufacture, impurity atoms
must be added to it. This process is called doping , and it improves the
conductivity of the material very significantly. Doped semiconductor
material is termed extrinsic material. Two different types of doping are
possible, donor doping and acceptor doping. Donor doping generates free
electrons in the conduction band (i.e., electrons that are not tied to an
atom). Acceptor doping produces valence band holes, or a shortage of valence
electrons in the material.
Donor doping is effected by adding impurity atoms which have five
electrons and three holes in their valence shells. The impurity atoms form
covalent bonds with the silicon or germanium atoms; but since semiconduc-
tor atoms have only four electrons and four holes in their valence shells, one
1-9
Semi-
conductor
Doping
10
Basic
Semiconductor
Theory
Fifth valence electron
from impurity atom
becomes free electron
Impurity atom
Figure 1-8. Donor doping.
spare valence-shell electron is produced for each impurity atom added. Each
spare electron produced in this way enters the conduction band as a free
electron. In Fig. 1 -8 there is no hole for the fifth electron from the outer shell
of the impurity atom; therefore, it becomes a free electron. Since the free
electrons have negative charges, donor-doped material is known as n-type
semiconductor material.
Free electrons in the conduction band are easily moved around under
the influence of an electric field. Therefore, conduction occurs largely by
electron motion in donor-doped semiconductor material. The doped
material remains electrically neutral (i.e., it is neither positively nor nega-
tively charged), because the total number of electrons (including the free
electrons) is still equal to the total number of protons in the atomic nuclei.
(The number of protons in each impurity atom is equal to the number of
orbital electrons.) The term donor doping comes from the fact that an electron
is donated to the conduction band by each impurity atom. Typical donor
impurities are antimony , phosphorus , and arsenic. Since these atoms have five
valence electrons, they are referred to as pentavalent atoms.
In acceptor doping , impurity atoms are added with outer shells contain-
ing three electrons and five holes. Suitable atoms with three valence elec-
trons (which are called trivalent) are boron , aluminum , and gallium. These atoms
form bonds with the semiconductor atoms, but the bonds lack one electron
for a complete outer shell of eight. In Fig. 1-9 the impurity atom illustrated
has only three valence electrons; therefore, a hole exists in its bond with the
surrounding atoms. Thus, in acceptor doping holes are introduced into the
valence band, so that conduction may occur by the process of hole transfer.
Since holes can be said to have a positive charge, acceptor-doped
semiconductor material is referred to as p-type material. As with n-type
material, the material remains electrically neutral, because the total number
of orbital electrons in each impurity atom is equal to the total number of
protons in its atomic nucleus. Holes can accept a free electron, hence the term
acceptor doping.
Even in intrinsic (undoped) semiconductor material at room tempera-
ture there are a number of free electrons and holes. These are due to
(ojojo)
>c^C XX
^ - * o ;
o{o\o
Figure 1-9. Acceptor doping.
11
Effects of Heat
and Light
thermal energy causing some electrons to break the bonds with their atoms
and enter the conduction band, so creating pairs of holes and electrons. The
process is termed hole-electron pair generation , and its converse is a process
called recombination. As the name implies, recombination occurs when an
electron falls into a hole in the valence band. Since there are many more
electrons than holes in n-type material, electrons are said to be the majority
carriers , and holes are said to be minority carriers. In />-type material holes are
the majority carriers and electrons are minority carriers.
When a conductor is heated, the atoms (which are in fixed locations)
tend to vibrate, and the vibration impedes the movement of the surrounding
electron gas. This means that there is a reduction in the flow of the electrons
that constitute the electric current, and we say that the conductor resistance
has increased. A conductor has a positive temperature coefficient of resis-
tance, i.e., a resistance which increases with increase in temperature.
When semiconductor material is at absolute zero, there are practically
no free electrons in the conduction band and no holes in the valence band.
This is because all electrons are in normal orbit around the atoms. Thus, at
absolute zero, a semiconductor behaves as an insulator. When the material is
heated, electrons break away from their atoms and move from the valence
band to the conduction band. This produces holes in the valence band and
free electrons in the conduction band. Conduction can then occur by
electron movement and by hole transfer. Increasing application of thermal
energy generates an increasing number of hole-electron pairs. As in the case
of a conductor, thermal vibration of atoms occurs in a semiconductor.
However, there are very few electrons to be impeded compared to the dense
electron gas in a conductor. The thermal generation of electrons is the
dominating factor, and the current increases with temperature increase. This
represents a decrease in semiconductor resistance with temperature increase,
i.e., a negative temperature coefficient. An exception to this rule is heavily doped
semiconductor material, which may behave more like a conductor than a
semiconductor.
1-10
Effects of
Heat and
Light
12
Basic
Semiconductor
Theory
Just as thermal energy causes electrons to break their atomic bonds, so
hole-electron pairs may be generated by energy imparted to the semicon-
ductor in the form of light. If the material is intrinsic, it may have few free
electrons when not illuminated, and thus a very high dark resistance . When
illuminated, its resistance decreases and may become comparable to that of
a conductor.
1-11
Drift Current
and
Diffusion
Current
In free space, an electric field will accelerate an electron in a straight
line from the negative terminal to the positive terminal of the applied
voltage. In a conductor or a semiconductor at room temperature, a free
electron under the influence of an electric field will move toward the positive
terminal of the applied voltage, but it will continually collide with atoms
along the way. The situation is illustrated in Fig. 1-10. Each time the
electron strikes an atom, it rebounds in a random direction. The presence of
the electric field does not stop the collisions and random motion, but it does
cause the electron to drift in the direction of the applied electric force.
Current produced in this way is known as drift current, and it is the usual kind
of current flow that occurs in a conductor.
Figure 1-11 illustrates another kind of current. Suppose a concentra-
tion of one type of charge carriers occurs at one end of a piece of semicon-
ductor material. Since the charge carriers are either all electrons or all holes,
they have the same polarity of charge, and thus there is a force of repulsion
between them. The result is that there is a tendency for the charge carriers
to move gradually (or diffuse) from the region of high carrier density to one
of low density. This movement continues until all the carriers are evenly
distributed throughout the material. Any movement of charge carriers
constitutes an electric current, and this type of movement is known as
diffusion current. Both drift current and diffusion current occur in semiconductor
devices.
Electron path when
no electric field is present
or
semiconductor
Figure 1-10. Drift current.
Charge
carrier
concentration ►-
I
I
I
Figure 1-11. Diffusion current.
Diffusion
current
13
Glossary of
Important
Terms
Nucleus. Central portion or core of the atom. Glossary of
Electron. Very small negatively charged particle. Important
Electronic charge. 1 .602 X 10“ 19 C. Terms
Proton. Positively charged particle contained in the nucleus of an atom.
Neutron. Particle with no electrical charge, contained in the nucleus of an
atom.
Shell. Path of electron orbiting around nucleus.
Atomic weight. Approximately the total number of protons and neutrons
in the nucleus of an atom.
Atomic number. The number of protons or orbiting electrons in an atom.
Positive ion. Atom that has lost an electron.
Negative ion. Atom that has gained an electron.
Germanium atom. Atom of semiconductor material, has four electrons and
four holes in its outer shell.
Silicon atom. Atom of semiconductor material, has four electrons and four
holes in its outer shell.
Hole. Absence of an electron where one could exist.
Energy level of shell. Amount of energy required to extract a particular
electron from its atomic shell.
Electron volt (eV). Energy required to move one electron through a
potential difference of one volt.
Energy band. Group of energy levels that may be occupied by electrons.
Conduction band. Energy band of electrons that have escaped from
atomic orbits.
Valence band. Energy band of electrons that arc in normal atomic orbits.
Forbidden gap. Energy band at which electrons normally do not exist.
Charge carrier. Electron or hole.
Mobility. Ease (or difficulty) with which a charge carrier may be moved
around.
Conventional current direction. Current flow from positive to negative.
Electron flow direction. Electron motion from negative to positive.
14
Basic
Semiconductor
Theory
Ionic bond. Electrostatic attraction when one atom gives an electron to
another. Bonding force in some insulators.
Metallic bond. Electrostatic attraction between large numbers of electrons
and the atoms that have released them. Bonding force in conductors.
Covalent bond. Bonding force that binds atoms which share electrons and
holes in their outer shells. Bonding force in semiconductors and some
insulators.
Electron gas. Large number of electrons available for current carrying in a
conductor.
Doping. Addition of impurity atoms to change electrical characteristics of
semiconductor material.
Donor atoms. Impurity atoms which release additional electrons within
semiconductor material.
Acceptor atoms. Impurity atoms which release additional holes within
semiconductor material.
p-type semiconductor. Semiconductor that has been doped with acceptor
atoms.
n-type semiconductor. Semiconductor that has been doped with donor
atoms.
Intrinsic. Name given to undoped semiconductor, or to material doped
equally with both types of impurities.
Extrinsic. Name given to doped semiconductor material.
Majority carriers. Type of charge carriers which are in the majority in a
given material (electrons in n-type, holes in p-type).
Drift current. Electrons moving randomly from one atom to another being
made to drift in a desired direction under the influence of an electric
field.
Diffusion current. Charge carrier movement resulting from an initial
concentration of charge carriers.
Minority carriers. Type of charge carriers which are in the minority in a
given material (holes in n-type, electrons in p-type).
Temperature coefficient. Ratio of resistance change to temperature
change.
Dark resistance. Resistance of unilluminated semiconductor.
Crystal lattice. Three-dimensional pattern in which atoms align themselves
in a solid.
Hole-electron pair. A valence-band hole and a conduction-band electron
produced by energy causing the breaking of atomic bonds.
Recombination. Holes and electrons recombining, i.e., the conduction-
band electron fills the valence-band hole.
Review
Questions
1-1. Describe the atom and draw a two-dimensional diagram to illustrate
your description. Compare the atom to a planet with orbiting satel-
lites.
1-2. What is meant by atomic number and atomic weight ? State the atomic
number and atomic weight for silicon.
1-3. Name the three kinds of bonds that hold atoms together in a solid.
What kind of bonding might be found in (a) conductors, (b) insula-
tors, (c) semiconductors?
1-4. Explain the bonding process in silicon and germanium. Use illustra-
tions in your answer.
1-5. Draw sketches to show the bonding process in conductors and insula-
tors.
1-6. What is meant by energy levels and energy bands?
1-7. Define conduction band , valence band , and forbidden gap and explain their
origin.
1-8. Draw the band structure for, and explain the difference between,
conductors, insulators, and semiconductors.
1-9. Define intrinsic semiconductors and extrinsic semiconductors. How can
extrinsic material be made intrinsic?
1-10. What is meant by majority carriers and minority carriers ? Which are
majority carriers and why in (a) donor-doped material, (b) acceptor-
doped material?
1-11. Define acceptor doping and explain how it is effected. Use illustra-
tions in your answer.
1-12. Repeat Question 1-11 for donor doping.
1-13. What are the names given to acceptor-doped material and donor-
doped material? Explain why.
1-14. Draw a sketch to show the process of current flow by hole movement.
Which have greater mobility, electrons or holes? Explain why.
1-15. Explain what happens to resistance with increase in temperature in
the case of (a) a conductor, (b) a semiconductor, (c) a heavily doped
semiconductor. What do you think would happen to the resistance of
an insulator with increase in temperature? Why?
1-16. Explain diffusion current and drift current. Use illustrations in your
answer.
1-17. Explain conventional current direction and direction of electron motion . State
why each is important.
15
Review
Questions
CHAPTER
2
2-1
Introduction
2-2
The
pn-junction
pN-
Junction
Theory
The /^-junction is basic to all but a few semiconductor devices. Thus,
it is important that the electronics student gain a thorough understanding of
^-junction theory. This requires an appreciation of the forces that act upon
charge carriers crossing the junction, and an understanding of the effects of
externally applied bias voltages. A knowledge of the junction equivalent
circuits is also important.
Figure 2-1 represents a /w-junction formed by two blocks of semicon-
ductor material, one of p - type material and the other of «-type material. On
the /7-side the small broken circles represent holes, which are the majority
carriers in the /j-type material. The dots on the n-side represent free electrons
within the n-type material. The holes on the /?-side are fixed in position
because the atoms in which they exist are part of the crystal structure.
Normally they are uniformly distributed throughout the p - type material.
Similarly, the electrons on the H-side are uniformly distributed throughout
the H-type material.
16
p
n
17
The pn-junction
Holes
Electrons
Figure 2-1. Initial condition of charge carriers at pn-junction.
Because holes and electrons are close together at the junction, some
free electrons from the n - side are attracted across the junction and fill holes
on the />-side. They are said to diffuse across the junction, i.e., flow from a
region of high carrier concentration to one of lower concentration (see
Section 1-11). The free electrons crossing the junction create negative ions
on the p - side by giving some atoms one more electron than their total
number of protons. They also leave positive ions behind them on the n-side
(atoms with one less electron than the number of protons). The process is
illustrated in Fig. 2-2(a).
Before the charge carriers diffused across the junction, both the n-type
and the p - type material were electrically neutral. However, as negative ions
are created on the /?-side of the junction, the region of the /?-side close to the
junction acquires a negative charge. Similarly, the positive ions created on
the n-side give the n-side a positive charge. The accumulated negative
charge on the />-side tends to repel electrons that are crossing from the n-side,
P
n
(a) Diffusion of charge
carriers across (create negative ion)
pn-junction.
(leave positive ion)
Positive potential
due to positive ions
(b) Junction barrier
potential and
electric field.
due to
negative ions
+
Repels holes
Repels electrons
Electric field at junction
Figure 2-2. Charge carrier diffusion across junction, and junction barrier potential.
18
pn-
Junction
Theory
and the accumulated positive charge on the n-side tends to repel holes
crossing from the />-side. Thus, it becomes difficult for more charge carriers
to diffuse across the junction. The final result is that a barrier potential is
created at the junction, negative on the /?-side and positive on the a - side
[Fig. 2-2(b)]. The electric field produced by the barrier potential is large
enough to prevent any further movement of electrons and holes across the
junction.
By considering doping densities, electronic charge, and temperature, it
is possible to calculate the magnitude of the barrier potential. Typical
barrier potentials at room temperature are 0.3 V for germanium junctions
and 0.7 V for silicon.
The movement of charge carriers across the junction leaves a layer on
either side which is depleted of charge carriers. This is the depletion region
shown in Fig. 2-3(a). On the n-side, the depletion region consists of donor
impurity atoms which have lost the free electron associated with them, and
have thus become positively charged. On the />-side, the region is made up of
acceptor impurity atoms which have become negatively charged by losing
the hole associated with them (i.e., the hole is filled by an electron).
On each side of the junction, an equal number of impurity atoms are
involved in the depletion region. If the two blocks of material have equal
doping densities, the depletion layers on each side of the junction are equal
in thickness [Fig. 2-3(a)]. If the />-side is more heavily doped than the n-side,
as shown in Fig. 2-3(b), the depletion region penetrates more deeply into the
n-side in order to include an equal number of impurity atoms on each side of
the junction. Conversely, if the n-side is the most heavily doped, the
depletion region penetrates deeper into the p- type material.
It has been shown that the electric field produced by the barrier
potential at the junction opposes the flow of electrons from the n-side and
the flow of holes from the /?-side. Since electrons are the majority charge
carriers in the n-type material, and holes are the majority charge carriers in
the p- type material, it can be seen that the barrier potential opposes the flow of
majority carriers. Also, any free electrons generated on the />-side by thermal
energy are attracted across the positive potential barrier to the n-side since
electrons are negatively charged. Similarly, the thermally generated holes on
the n-side are attracted to the />-side through the negative barrier presented
to them at the junction. Electrons on the p-side and holes on the n-side are
minority charge carriers. Therefore, the barrier potential assists the flow of
minority carriers across the junction.
To Summarize: A region depleted of charge carriers spreads across both
sides of a pn-junction, and penetrates deeper into the more lightly doped
side. The depletion region encompasses an equal number of ionized atoms of
opposite polarity, on opposite sides of the junction. A barrier potential exists
due to the depletion effect, positive on the n-side and negative on the />-side
of the junction. The electric field from the barrier potential prevents the flow
of majority carriers and assists the flow of minority carriers from each side.
Depletion region
19
Reverse-Biased
Junction
(a) Equal doping
densities
Layer of negative ions Layer of positive ions
(depleted of holes) (depleted of electrons)
Depletion region
(wide on n side)
Figure 2-3. Junction depletion region.
If an external bias voltage is applied positive to the rt-side and negative
to the /^-side of a /^-junction, electrons from the n-side are attracted to the
positive bias terminal, and holes from the /7-side are attracted to the negative
terminal. Thus, as shown in Fig. 2 - 4 , holes from the impurity atoms on the
/7-side of the junction are attracted away from the junction, and electrons are
attracted away from the atoms on the n-side of the junction. In this way the
depletion region is widened, and the barrier potential is increased by the
magnitude of the applied voltage. With the barrier potential and the
resultant electric field increase, there is no possibility of majority carrier
current flow across the junction. In this case, the junction is said to be r (verse
biased.
Although there is no possibility of a majority carrier current flowing
across a reverse-biased junction, minority carriers generated on each side can
2-3
Reverse-
Biased
Junction
p
20
pn-
Junction
Theory
still cross the junction. Electrons in the /7-side are attracted across the
junction to the positive potential on the n-side. Holes on the n-side may be
said to flow across to the negative potential on the /7-side. This is shown by
the junction reverse characteristic , or graph of reverse current (I R ) plotted to a
base of reverse voltage (V R ) (Fig. 2-5). Only a very small reverse bias voltage is
necessary to direct all available minority carriers across the junction, and
when all minority carriers are flowing across, further increase in bias voltage
will not increase the current. This current is referred to as a reverse saturation
current , and is designated I s .
I s is normally a very small current. For silicon, it is typically less than
1 jiA, while for germanium it may exceed 10 ji A. This is because there are
more minority charge carriers available in germanium than in silicon, since
charge carriers are more easily detached from germanium atoms.
A reverse-biased /w-junction can be represented by a very large resis-
tance. From Fig. 2-5, it is seen that with 5-V reverse bias and I s = 10 fiA, the
reverse resistance is
n - 5V
R 10 pA
= 500 kQ
Reverse breakdown
voltage
Reverse voltage
V 5 4 3 2
, I |
" Reverse
breakdown
V*
Reverse
current
- 20
- 30
mA
21
Forward-Biased
Junction
Figure 2-5. pn- junction reverse characteristics.
For a silicon junction with an I s of about 0.1 n A and a reverse voltage of
5 V, R r is 50 M12. In practice, the reverse resistance is normally not
specified; instead, the effect of reverse saturation current J s is taken into
account for each particular circuit.
If the reverse bias voltage is increased, the velocity of the minority
charge carriers crossing the junction is increased. These high-energy charge
carriers strike the atoms within the depletion region and may cause large
numbers of charge carriers to be knocked out of the atoms ( ionization by
collision). When this happens, the number of charge carriers avalanches, and a
large current flows across the junction. This phenomenon, known as reverse
breakdown , occurs at a particular reverse voltage (the reverse breakdown voltage)
for a given /w-junction (see Fig. 2-5). Unless the current is limited by a
suitable series resistor, the junction may be destroyed. Reverse breakdown is
employed in a device known as a breakdown diode, discussed in Chapter 11.
Consider the effect of an external bias voltage applied with the polarity
shown in Fig. 2-6: positive on the />-side, negative on the n-side. The holes on
the />-side, being positively charged particles, are repelled from the positive
bias terminal and driven toward the junction. Similarly, the electrons on the
n-side are repelled from the negative bias terminal and driven toward the
junction. The result is that the depletion region is reduced in width, and the
barrier potential is also reduced. If the applied bias voltage is increased from
zero, the barrier potential gets progressively smaller until it effectively
disappears, and charge carriers can easily flow across the junction. Electrons
from the n-side are then attracted across to the positive bias terminal on the
p- side, and holes from the />-side flow across to the negative terminal on the
n-side. Thus, a majority carrier current flows, and the junction is said to be
forward biased.
2-4
Forward-
Biased
Junction
22
pn-
Junction
Theory
Narrowed depletion region
p — H ^ V * — n
Barrier potential for
unbiased junction
Barrier potential
reduced by forward
bias potential
Figure 2-6. Barrier potential at forward-biased junction.
Figure 2-7 shows the forward current ( I F ) plotted against forward
voltage ( V F ) for typical germanium and silcon /w -junctions. In each case, the
graph is known as the forward characteristic of the (silicon or germanium)
junction. It is seen that very little forward current flows until V F exceeds the
junction barrier potential (0.3 V for germanium, 0.7 V for silicon). The
characteristics follow an exponential law. As V F is increased to the knee of the
characteristic, the barrier potential is progressively reduced to zero, allowing
more and more majority charge carriers to flow across the junction. Beyond
Germanium Silicon
Figure 2-7. pn-junction forward characteristics.
the knee of the characteristic, the barrier potential has been completely
overcome, I F increases almost linearly with increase in V Fy and the combined
semiconductor blocks are simply behaving as a resistor.
It is obvious that a forward-biased junction can be represented by a
very low resistance. From point x on Fig. 2-7, the forward resistance for silicon
is calculated as
F 20 ttlA
For germanium, from pointy on Fig. 2-7,
* f =° n 3V -> 5 a
F 20 mA
In practice, R F is normally not used; instead the dynamic resistance ( r d ) of
the junction is determined. This quantity is also known as the incremental
resistance or ac resistance. The dynamic resistance is measured as the reciprocal
of the slope of the forward characteristic beyond the knee.
Suppose the current and voltage conditions are changed from point a
to point b on Fig. 2-7. The change in forward voltage is A F^~0.1 V, and the
change in forward current is A/^^40 mA, as illustrated. The resistance
change r d is calculated as
SV F 0.1V
d ~ M f 40 mA 2,5 “
23
Temperature
Effects
As discussed in Section 2-3, the reverse current I s is made up of
minority charge carriers crossing the junction. When the temperature of
semiconductor material is increased, the additional thermal energy causes
more electrons to break away from atoms. This creates more hole-electron
pairs and generates more minority charge carriers. Therefore, I s increases as
junction temperature rises.
I s can be shown to be dependent upon electronic charge, doping
density, and junction area, as well as temperature. With the exception of
temperature, all these factors are constant for a given junction; thus I s is
altered only by temperature change. It has been found that I s approxi-
mately doubles for each 10°C increase in temperature. Hence, for a given
junction, there is a definite I s level for each temperature level (Fig. 2-8).
It has been shown that I s increases with increase in temperature. It
can also be shown that the forward current I F is proportional to I s .
Therefore, as illustrated by the vertical line in Fig. 2-9(a), for a fixed level of
2-5
Temperature
Effects
Pn-
Junction
Theory
Figure 2-8. Temperature effect on reverse characteristics.
(a) V F fixed
(b) l F fixed
Figure 2-9. Temperature effect on forward characteristics.
V F , I F increases as the junction temperature increases. If I F (at the increased
temperature) is measured for several levels of V F and the results plotted, it is
seen that the characteristic is moved to the left. The horizontal line on Fig.
2-9(b) shows that, if I F is held constant while the junction temperature is
changing, the foward voltage, V F , decreases with junction temperature
increase (i.e., V F has a negative temperature coefficient). It is found that the
temperature coefficient for the forward voltage of a /^-junction is approxi-
mately — 1.8 mV/°C for silicon and —2.02 mV/°C for germanium.
The depletion layer of a /w-junction is a region depleted of charge
carriers. Therefore, as an insulator or a dielectric medium situated between
two low-resistance regions, it is a capacitor. The value of the depletion layer
capacitance , designated C^, may be calculated from the usual formula for a
parallel plate capacitor. A typical value of C ^ is 40 picofarads (pF). Since
the width of the depletion layer can be changed by altering the reverse-bias
voltage, the capacitance of a given junction may be controlled by the
applied bias. This property is utilized in a variable-capacitance device
known as a varicap or varactor (Chapter 19).
Consider a forward-biased junction carrying a current I F . If the
applied voltage is suddenly reversed, I F ceases immediately, leaving some
majority charge carriers in the depletion region. These charge carriers must
flow back out of the depletion region, which is widened when reverse biased.
The result is that, when a forward-biased junction is suddenly reversed, a
reverse current flows which is large initially and slowly decreases to the level
of I s . The effect may be likened to the discharging of a capacitor, and so it is
represented by a capacitance known as the diffusion capacitance C d . It can be
shown that C d is proportional to the forward current I F . This is to be
expected, since the number of charge carriers in the depletion region must
be directly proportional to I F . A typical value of diffusion capacitance C d is
0.02 pF, which is very much greater than the depiction layer capacitance,
<>•
The effect produced by C d is variously known as recovery time , carrier
storage, or, in junctions with a heavily doped />-region, as hole storage. The
diffusion capacitance becomes very important in devices which arc required
to switch rapidly from forward to reverse bias (see Section 3-1 1).
A reverse-biased junction can be simply represented as the reverse
resistance R r in parallel with the depiction layer capacitance C ^
[Fig. 2-10(a)].
The equivalent circuit for a forward-biased junction is represented by
the dynamic resistance r d in parallel with the diffusion capacitance C d . A
battery (to represent the barrier potential) must be included in scries with r d .
The complete equivalent circuit for a forward -biased junction is shown in
Fig. 2- 10(b).
25
Junction
Equivalent Circuit
2-6
Junction
Capacitance
2-7
Junction
Equivalent
Circuit
26
pn-
Junction
Theory
(a) Equivalent circuit
for reverse biased
junction
Cd
(b) Equivalent circuit
for forward biased
junction
Figure 2-10. Equivalent circuits for pn- junction.
Glossary
of
Important
Terms
Barrier potential. Potential at a pn -junction, resulting from charge carriers
crossing the junction. Typically, 0.3 V for germanium, 0.7 V for
silicon.
Depletion region. Narrow region depleted of charge carriers.
Reverse saturation current. Minority charge carrier current that flows
across a reverse-biased junction.
Avalanche effect. Charge carriers increasing in number by knocking other
charge carriers out of atoms.
Reverse breakdown. Junction breakdown under the influence of a large
reverse-bias voltage.
Forward current. Current that flows across a forward-biased -junction.
Depletion layer capacitance. Junction capacitance due to depletion region.
Diffusion capacitance. Junction capacitance due to forward current.
Varicap. Variable capacitance device utilizing the depletion layer capaci-
tance.
Varactor. Same as varicap .
Reverse resistance. Resistance of a reverse-biased junction.
Forward resistance. Resistance of a forward-biased junction.
Reverse characteristic. Plot of reverse current to base of junction reverse-
bias voltage.
Forward characteristic. Plot of forward current to base of junction for-
ward-bias voltage.
Dynamic resistance. Reciprocal of the slope of the forward characteristic
beyond the knee.
Incremental resistance. Same as dynamic resistance.
AC resistance. Same as dynamic resistance.
Recovery time. Effect of diffusion capacitance on time required to change
the current crossing a forward- biased junction.
Carrier storage. Same as recovery time.
Hole storage. Same as recovery time.
Reverse bias. Voltage applied to junction, positive to n-side, negative to
/>-side.
Forward bias. Voltage applied to junction, positive to />-side, negative to
n-side.
2-1. Using illustrations, explain how the depletion region at a /^-junction
is produced. List the characteristics of the depletion region.
2-2. Draw a sketch to show the barrier potential at a /w-junction, with (a)
equal doping, and (b) unequal doping of each side. Show the relative
widths of the depletion region on each side of the junction and the
polarity of the barrier potential.
2-3. A bias is applied to a pn -junction, positive to the p- side, negative to
the n-side. Show, by a series of sketches, the effect of this bias upon:
depletion region width, barrier potential, minority carriers, majority
carriers. Briefly explain the effect in each case.
2-4. Repeat Question 2-3 for a bias applied negative to the />-side, positive
to the n-side.
2-5. Sketch the voltage-current characteristics for a /wi-junction (a) with
forward bias, (b) with reverse bias. Show how temperature change
affects the characteristics.
2-6. State typical values for the depletion layer capacitance and diffusion
capacitance and briefly explain the origin of each. Which of the two
is more important at (a) a forward-biased junction, (b) a reverse-
biased junction?
2-7. Draw the equivalent circuits for forward -biased and reverse-biased
junctions. Identify the components of each.
2-8. From the forward and reverse characteristics shown in Fig. 2-11,
determine R Fi r Jy R r , and I s . Define each quantity.
27
Review
Questions
Review
Questions
28
pn-
Junction
Theory
2-9. State typical values of reverse saturation current for silicon and
germanium junctions. Explain the origin of reverse saturation cur-
rent.
2-10. State typical values of barrier potential for silicon and germanium
junctions. Explain the origin of the barrier potential.
2-11. What effect does the barrier potential have upon majority charge
carriers and minority charge carriers? Briefly explain.
The
Semiconductor
Diode
The term diode indicates a two-electrode device. The semiconductor
diode is simply a /m-junction. The two sides of the junction are provided
with connecting terminals or leads. A diode is a one-way device, offering a
low resistance when forward biased, and behaving almost as an insulator (or
opened switch) when reverse biased. One of the most important applications
of the diode is as a rectifier.
The symbol for the diode is an arrowhead and bar, as shown in Fig.
3-1. The arrowhead indicates the conventional direction of current flow when
forward biased, i.e., from the positive terminal through the device to the
negative terminal. The />-side of the diode is always the positive terminal for
forward bias and is designated the anode. The n-sidc is called the cathode and
is the negative terminal when the device is forward biased.
CHAPTER
3
3-1
Introduction
3-2
Diode Symbol
and
Appearance
29
30
The
Semiconductor
Diode
Positive terminal
for forward bias
Negative terminal
for forward bias
Anode (p-type)
Cathode (n-type)
Arrowhead indicates
convention current
direction when
forward biased
Figure 3-1. Diode symbol.
0.3 cm
H h-
=CUD=
0.5 cm
(a) Low current
diode
CD —
(b) Medium current
diode
(c) High current
diode
Figure 3-2. Typical low, medium, and high-current diodes.
Figure 3-2 shows the appearance of low-, medium-, and high-current
diodes. The body of the low-current device may be only 0.3 cm long. The
cathode is usually denoted by a color band, and several bands may be used
to color code the device’s type number. This type of diode is capable of
passing approximately 100 mA of forward current. It can also survive about
75-V reverse bias without breaking down, and its reverse saturation current
at 25° C is typically less than 1 juA.
The medium-current diode shown in Fig. 3-2(b) can typically pass a
forward current of about 400 mA and can survive over 200 V of reverse bias.
The anode and cathode terminals may be indicated by a diode symbol on
the side of the device or by colored bands close to the cathode end. Low- and
medium-current diodes are usually mounted by soldering their leads to
connecting terminals. Heat generated in the device is then carried away by
air convection and by conduction along the connecting leads. High-current
diodes, or power diodes [Fig. 3-2(c)], generate a lot of heat, and air
convection would be completely inadequate. Such devices are designed for
bolt mounting to a metal heat sink which will conduct the heat away. Power
diodes can pass forward currents of many amperes and can survive several
hundred volts of reverse bias.
31
Diode
Fabrication
One of the most common methods used for diode construction is the
alloy technique. In this method, a /^-junction is formed by melting a tiny
pellet of aluminum (or some other ^>-type impurity) upon the surface of an
n-type crystal. Similarly, an n-type impurity may be melted upon the surface
of a //-type crystal. The process is illustrated in Fig. 3-3(a).
3-3
Diode
Fabrication
Aluminum or
indium pellet
/7-type substrate Cathode
(a) Alloy diode
P - type
impurities Anode
Figure 3-3. Fabrication of alloy and diffused diodes.
32
The
Semiconductor
Diode
Another method employed in diode manufacture is diffusion construc-
tion, illustrated in Fig. 3-3(b). When an n-type semiconductor is heated in a
chamber containing an acceptor impurity in vapor form, some of the
acceptor atoms are diffused (or absorbed) into the n-type crystal. This
produces a /^-region in the n-type material, and thus creates a /ra-junction.
By uncovering only part of the n-type material during the diffusion process
(the remainder has a thin coating of silicon dioxide), the size of the />-region
can be limited. Metal contacts are finally electroplated on the surface of
each region for connecting leads.
The diffusion technique lends itself to the simultaneous fabrication of
many hundreds of diodes on one small disc of semiconductor material. This
process is also used in the production of transistors and integrated circuits.
3-4
Diode
Characteristics
and
Parameters
The diode is essentially a /ra-junction and its characteristics and
parameters are those discussed in Chapter 2. Figure 3-4 shows the character-
istics of a typical low-current silicon diode. It is seen that the forward
current (I F ) remains low (less than 1 mA) until the forward-bias voltage
( V F ) exceeds approximately 0.7 V. Beyond this bias voltage I F increases
almost linearly with increase in V F .
Since the reverse current ( I R ) is very much smaller than the forward
current, the reverse characteristic is plotted to an expanded scale. I R is
Figure 3-4. Forward and reverse characteristics for a typical low-current silicon diode.
shown to be on the order of nanoamperes and is almost completely un-
affected by increases in reverse-bias voltage. As already explained in
Chapter 2, I R is largely a minority carrier reverse saturation current ( l s ).
Nonlinearity of I R occurs because some minority charge carriers leak along
the junction surface, and this current component increases with increase in
reverse-bias voltage. For the characteristics in Fig. 3-4, I R is less than
1/10,000 of the lowest normal forward current. Therefore, I R is quite
negligible when compared to I F , and the reverse-biased diode may be
considered almost as an insulator or an open switch.
If the reverse voltage V R is increased to 75 V for a diode with the
characteristics of Fig. 3-4, the device will go into reverse breakdown. This is
shown by the broken line on the reverse characteristic. Reverse breakdown
can destroy a diode unless the current is limited by means of a suitable
resistor connected in series with the device. The resistor value must be
selected to keep the device power dissipation ( V R X I R ) below the maximum
specified by the manufacturer.
The diode parameters of greatest interest are forward volt drop ( V F ),
dynamic resistance (r d ), reverse saturation current (/$), and reverse breakdown voltage
(Vbr\ The maximum forward current (/f ) is also important. All these
quantities are normally listed on the device data sheet provided by the
manufacturer. For the characteristics in Fig. 3-4, V F is 0.7 to 0.9 V, I s is
approximately 0.1 /xA, and Vbr is 75 V. The dynamic resistance is de-
termined by calculating the reciprocal of the slope of the forward character-
istic beyond the knee. As shown in the figure,
sv,
\i F
o.i v
40 mA
= 2.5 Q
33
Graphical
Analysis
of Diode
Circuit
Figure 3-5 shows a diode connected in series with a 100-12 resistance
(R l ) and a supply voltage ( Fy). The polarity of V s is such that the diode is
forward biased; consequently, the current in the circuit is identified as I F .
To determine the voltage across the diode and the current flowing
through it, a dc load line must be superimposed on the diode forward
characteristics. The dc load line illustrates all dc conditions that could exist
within the circuit for given values of Fy and R L . Since the load line is always
straight, it can be constructed by plotting any two corresponding current
and voltage points and then drawing a straight line through them. The
process is demonstrated in Example 3-1.
To determine tw'o points on the load line, a formula relating voltage,
current, and resistance must first be derived from the circuit. From Fig. 3-5,
3-5
Graphical
Analysis
of
Diode Circuit
Supply voltage ( F 5 ) = (volts drop across R L ) + (volts drop across diode)
i v„
( 3 - 1 )
If
34
The
Semiconductor
Diode
Supply
voltage
Figure 3-5. Diode and resistor in series.
Example 3-1
Draw the dc load line for the circuit shown in Fig. 3-5. The diode
characteristics are given in Fig. 3-6.
solution
From Eq. (3-1),
V s = I f R l +V f
When I F = 0,
V s = 0+V F
Therefore, the diode voltage is
V f =V s = 5V
Plot point A on the diode characteristics at 1 F — 0 and V F = b V.
When V F =0.
V s = I f R l + 0
h=
2k
*L
5V
100S2
= 50 mA
Plot point B on the diode characteristic at I F = 50 mA and V F = 0. Now draw the dc
load line through points A and B.
Since the relationship between the diode forward voltage V F and the
forward current I F is defined by the diode characteristic, there is only one
point on the dc load line at which the diode voltage and current are
compatible with the circuit conditions. That is point (), termed the quiescent
Figure 3-6. Plotting the dc load line for a diode circuit.
point or dc bias point, where the load line intersects the diode characteristic.
This may be checked by substituting the values of I F and V F at point Q. into
Eq. (3-1).
From point () on Fig. 3-6, I F — 40 mA and V F = 1 V. Equation (3-1)
states that V s = I F R L + V F ; therefore, F 5 = (40 mAXlOO ft)+ 1 V = 5 V. No
other values of I F and V F on the diode characteristics can satisfy Eq. (3-1).
In the circuit of Fig. 3-5, the resistor R L determines the slope of the dc
load line, and the supply voltage V s determines the point d on the load line.
Therefore, the quiescent conditions for the circuit can be altered by chang-
ing either R L or V s .
When designing a diode circuit, it may be desired to use a given supply
voltage and set up a specified forward current. In this case, point A and the
Q point are first plotted, and the dc load line is drawn. R L is then calculated
by determining the slope of the load line. The problem could also occur in
another way. For example, R L and the required I F are known, and V s has to
be determined. This problem is solved by plotting points B and () and
drawing the load line through them. The supply voltage is then read as V F
at point A.
For the circuit shown in Fig. 3-5, determine a new value of load
resistance which will give a forward current of 30 mA.
solution
From Eq. (3-1), V F = V s - I F R L .
When I F —0, V F = 5 V.
Plot point A on the characteristics (Fig. 3-7) at I F = 0 and V F — 5 V.
Point () is plotted on the device characteristic at 7^ = 30 mA. The new dc
load line is now drawn through points A and (), and R L is determined as the
35
Graphical
Analysis
of Diode
Circuit
Example 3-2
36
The
Semiconductor
Diode
Example 3-3
For the circuit of Fig. 3-5, determine a new value of V s which will give
I F = 50 mA.
solution
Plot point Q on the forward characteristic at I F = 50 mA (Fig. 3-8). V F at the
Q point is 1.1 V. To find another point on the load line, the voltage change
across the diode for a given change in I F is calculated.
Figure 3-8. Determining the value of supply voltage required for a given R L and I F .
When I F changes from 50 mA to zero, A 7^ = 50 mA
and AV F = AI F R L = 50 mAXlOO £2 = 5 V.
The new value of V F is (1.1 V + 5 V) = 6.1 V.
Point A is now plotted at I F = 0 and F f = 6.1 V (Fig. 3*8). The dc load
line is drawn through points A and Q,, and the value of supply voltage is
read from point A as V s = 6. 1 V.
37
Graphical
Analysis
of Diode
Circuit
The previous discussion refers only to a forward-biased diode. For a
reverse-biased diode a similar approach can be taken. To determine the
exact levels of reverse current and voltage, the load line can be drawn as
before, but this time upon the reverse characteristic. Equation (3-1) is
applicable, but instead of forward voltage and current, the reverse quantities
are substituted [see Fig. 3-9(a)]. The equation becomes
V s = I r R l +V r (3-2)
A dc load line drawn upon the device reverse characteristics would be
almost vertical [see Fig. 3-9(b)]. Usually, such a load line is not drawn,
because the diode reverse current can easily be determined from the device
reverse characteristics. On Fig. 3-9(b), at V R = b§ V, I R is approximately 1.5
/iA. At V R = 10 V, I R is around 1 ju,A.
(a) Diode circuit
with reverse
bias voltage
— v* —
V 50 40 30 20 10 u
Figure 3-9. Drawing the dc load line on diode reverse characteristics
Diode
Piecewise
Linear
Characteristics
When designing a diode circuit, a straight-line approximation of the
diode forward characteristic is sometimes employed. This approximation is
called the piecewise linear characteristic. The piecewise linear characteristic may
be constructed by simply drawing a straight line on the near linear portion
of the characteristic and extending it to the horizontal axis, as shown in Fig.
3-10. Notice that the straight line cuts the horizontal axis approximately at
V F = 0.7 V, i.e., at the barrier potential ( V B ). For germanium diode char-
acteristics the straight line would meet the horizontal axis at approximately
V f =0.3 V.
The reciprocal of the slope of the near linear portion of the diode
characteristics is the dynamic resistance r d . From Fig. 3-10, an equation may
be determined relating V F , h , and V B .
If the diode forward characteristic is not available, the piecewise linear
characteristic may be constructed from a knowledge of the dynamic resis-
tance r d and the barrier voltage V B . The value of r d is usually available from
the manufacturer’s data sheet, and V B is approximately 0.7 V for a silicon
diode and 0.3 V for a germanium device.
The diode piecewise linear characteristic is reasonably accurate only
for values of I F above the knee of the diode forward characteristic. There-
fore, this approximate characteristic should be used only for diodes that are
normally biased into the near-linear region of the device forward character-
istics.
(3-3)
/
0.2 0.4 0.6 0.7 0.8 1.0 V
Figure 3-10. Diode piecewise linear characteristics.
38
Draw the piecewise linear characteristic for a silicon diode with a Example 3-4
dynamic resistance r d of 3.2 S2. The maximum forward current I F is 100 mA.
solution
Convenient I F and V F scales are set up as shown in Fig. 3-11, with I F going
to its maximum value of 100 mA. Since the device is silicon, a V B of 0.7 V is
marked at point K. Point L is determined from Eq. (3-3):
V F -V„ + I p r,
Figure 3-11. Diode piecewise linear characteristics drawn from V B and r d .
Take 7^—100 mA.
Then F f = 0.7 V + (100 mAX3.2 S2) = 0.7 V + 0.32 V=1.02 V.
Point L is now plotted at I F = 100 mA and V F * 1.02 V. The piecewise linear
characteristic is drawn by joining points K and L together.
The equivalent circuits for a forward-biased and reverse-biased diode
are exactly the same as those discussed in Section 2-7. The equivalent circuit
for the forward-biased diode may be modified to form a small-signal ac
equivalent circuit. This circuit is employed for diodes which are maintained in
a forward-bias condition, but which are subjected to small variations in I F
and V F . The small-signal ac equivalent circuit is drawn (see Fig. 3-12) by
dropping the battery representing the barrier potential from the circuit of
Fig. 2- 10(b).
3-7
Diode
Equivalent
Circuit
39
40
The
Semiconductor
Diode
Figure 3-12. Small-signal ac equivalent circuit for forward-biased diode.
Diodes are frequently connected with other components in circuits
which must be ac analyzed . An example of this is an amplifier, which must be
analyzed to determine its gain, input impedance, etc. In this circumstance,
the diode ac equivalent circuit is employed.
3-8
Diode Data
Sheet
To select the proper diode for a particular application, the data sheets
provided by device manufacturers must be consulted. Portions of typical
diode data sheets are shown in Fig. 3-13 and 3-14.
Most data sheets start off with the device type number at the top of the
page, and a short descriptive title, e.g., silicon rectifier or diffused silicon switching
diode. Immediately following, there are usually mechanical data, perhaps a
description of the package, and an illustration showing the package shape
and dimensions. The absolute maximum ratings at 25° C are then listed.
These are maximum voltages, currents, etc., that can be applied without
destroying the device. It is very important that these ratings not be exceeded,
otherwise failure of the diode is quite possible. For reliability, the absolute
maximum ratings should not even be approached. Also, the maximum
ratings must be adjusted downward for operation at temperatures greater
than 25° C.
There is normally a list of other electrical characteristics for the device
following the absolute maximum ratings. An understanding of all the
parameters specified on a data sheet will not be achieved until circuit design
is studied. However, some of the most important parameters are considered
below:
y«M Peak reverse voltage (or peak inverse voltage) This is the absolute
peak of voltage that may be applied in reverse across the diode.
Vbr Reverse breakdown voltage The minimum reverse voltage at which
the device may break down.
I F Steady-state forward current This is the maximum current that may
be passed continuously through the diode. It is usually specified
for 25° C, and must be derated for operation at higher tempera-
tures.
Ifm( surge) Peak surge current This current may be passed for the time period
specified through a diode operating below the specified tempera-
ture. The surge current is very much higher than the normal
TYPES 1N4001 THROUGH 1N4007
DIFFUSED-JUNCTION SILICON RECTIFIERS
SO-IOOO VOLTS • 1 AMP AVG
• MINIATURE MOLDED PACKAGE
• INSULATED CASE
• IDEAL FOR HIGH-DENSITY CIRCUITRY
'mechanical data
'absolute maximum rotings at specified ombientt temperature
! l N4001 1N4002 1N4003 1N4004 1N4005 1N4006
j 1 P44007
UNIT
Peak Reverse Voltoge from
— 65*C to 1 75*( (See Note 1)
SO 100 200 400 600 800
1000
J
v Steady Stole Reverse Voltoge
* from 2S*C to 7S*C
! 1
SO 1 100 200 400 600 800
1000
f
Average Rectified forword Current from
2S°( fo 7S°( (See Notes 1 ond 2)
1
O
• Repetitive Peok Forword Current. 10 cycles,
ot (or below) 7S°C (See Note 3)
10
0
. Peok Surge Current. One Cycle.
ot (or below) 7S°C (See Note 3)
30
Taiop.i Optroltng Ambient Temperoture Ronge
— 6S to - I7S
•c
T,., Sloroge Temperoture Ronge
-6S to - 200
•c 1
leod Temperoture *4 Inch from
Cose lor 10 Seconds
3 SO
•c
■OTCS
(•AliRMWtlf pAivt ph«tr 10 1»t.
0
} IK.« t*il.hn It* » It44-<*ii4v«>4« r**l»4 tnnl U (•> vWtt) •> '»♦ 1*44 ’« t*v* <•« •»*> *•
»4 V.fkft ik«it J*( rti.i il» •ml.tni ititipr' j'h. 9 *•• thru ■ 4<>*|t 4»e't
1 Hint «•'»" tilli tvi U Ift 4#M IIM *•»« rnh,» 1*4 4m I" it *•* •* |*i ktl»| t« «•< <m >»4 *•('»*• #»4 'w«».«4
* I44.14I41 SC Of C ••fltlotf 4414
t Iht •rntlHtf ltD.N'4'911 .« 4144111.94 4< 4 »4illl > l*ll»4l tilt* 't* 4t>t|t «4'»>4l III I44l.4f |K.'' V. *tl4
41
Diode Data
Sheet
Figure 3-13. Diode data sheet. (Courtesy of Texas Instruments, Inc.)
42
The
Semiconductor
Diode
TYPES 1N914, 1N914A, 1N914B, 1N915,
1N916, 1N916A, 1N916B and 1N917
DIFFUSED SILICON SWITCHING DIODES
| • Extremely Stable and Reliable High-Speed Diodes
mechanical data
ab»oiuta maximum rating* at 25°C ambient temperature (unless otherwise noted)
V.
Revert* Voltage at — 65 to + 150*(
1N914
1N914A
IN9T4B
1N915
1N916
1N916A
IN916B
1N9I7 Unit
75
75
75
so
7S
75
75
30 *
1.
Average Rectified Fwd. Current
7S
75
7S
75
75
75
7$
50 mo
1.
Average Rectified Fwd. Current ot + 1S0 # C
10
10
10
10
10
r io
10
10 mo
I.
Recurrent Feok Fwd. Current
225
225
225
225
225
225
225
150 mo
inw?*!. Surge Current, 1 s*<
soo
500
500
SOO
500
500
500
300 mo
r
Rower Dissipation
250
250
250
250
250
250
250
^ 250 T
T*
Operating Temperoture Range
— 65 to 4-
175
•c
T.„
Storage Temperature Ronge
200
•c
maximum electrical characteristics at 25*C ambient temperature (unless otherwise noted)
BV* Min Breakdown Voltage ot 100 /io
It Reverse Current ot V (
It Reverse Current at — 20 r
It B even* Current ot — 20 v ot 100°C
It Reverse Current ot — 20 v ot 4- 1S0°C
It Reverse Current of — 10 v
It Reverse Current ot — 10 » ot 125°C
It Min Fwd Current at V* = 1 •
V f of 250 fia
Vt at 1.5 mo
Vt ot 3.5 mo
Vt ot 5 mo
Vt Min ot 5 mo
C Capacitance ot V t = 0
operating characteristics at 25°C ambient temperature (unless otherwise noted)
1„ Max Revert* Recovery Time
V, Fwd Recovery Voltage (50 mo r*ak Sq. wove,
0.1 /xsec puke width, 10 ns*< nt* time,
5 kc i» 100 kc rep. rate)
• tf*«nilt <1 lim iMlnMRtl
■ Imw (I* •« [f IS m* I,. r«m> It I *«)
« ECU |lt M l F . *» *, wm> H I nt)
2.5 2.5 | 25
100
100
100
65
100
100
100
40 v
s
5
5
5
5
5
5 i
HO
0.025
0025
0.025
|
0 025
0.025
0025
HO
3
3
3
5 j
3
3
3
25 h°
50 |
50
50
r. 50
50 1
: s °
0025
0 05 h°
l ■ ■
r
i
l ^
10
20 H
100
50 '
! io ■
i 20 1
30
10 mo
1
^ 0 64 v
[ 0.74 : v
0 S3 v
r 0 72
0.73
073
V
0.60 ’
!
4
4
^ 4 H
4 | 2
2 2
2.5 1 pi
Figure 3-14. Low-current diode data sheet. (Courtesy of Texas Instruments, Inc.)
maximum forward current. It is a current that may flow briefly
when a circuit is first switched on.
I R Static reverse current The reverse saturation current for a specified
reverse-bias voltage and maximum device temperature.
V F Static forward voltage drop The maximum forward volt drop for a
given forward current and device temperature.
P Continuous power dissipation , at 25° C The maximum power that
the device can safely dissipate on a continuous basis in free air.
This rating must be downgraded at higher temperatures, and
may be upgraded when the device is mounted on a heat sink.
C r Total capacitance Maximum capacitance for a forward -biased
diode at a specified forward current.
t n Reverse recovery time Maximum time for the device to switch from
on to off.
The basic diode half-wave rectifier circuit is shown in Fig. 3-15. An
alternating voltage is applied to a single diode connected in series with a
load resistor ( R L ). The diode is forward biased during the positive half-cycle
of the input waveform, and reverse biased during the negative half-cycle.
Input
Output
(a) Basic rectifier circuit showing input and output waveforms
-H V f K"
+ O M t o + - o x ♦ o
1 ! I ^1 |
I II I
- o — — - i 6 - * o — - * — — o +
(b) Effect of positive input (c) Effect of negative input
Figure 3-15. Basic half-wave rectifier circuit.
43
Half-Wave
Rectification
3-9
Half-Wave
Rectification
3 - 9.1
Basic Half-
Wave
Rectifier
L
44
The
Semiconductor
Diode
Example 3-5
Substantial current flows through R L only during the positive half-cycles of
the input. During the negative half-cycles, the diode behaves almost as an
open circuit. The output voltage developed across R L is a series of positive
half-cycles of alternating voltage, with intervening small constant negative
voltage levels.
When the diode is forward biased [Fig. 3-1 5(b)], the voltage drop
across it is K F , and the output voltage is (input voltage) — V F . The peak
output voltage is
E,-V r -V F (3-4)
and the peak load current is
(3-5)
During the negative half-cycle of the input waveform [Fig. 3- 15(c)] the
reverse-biased diode offers a very high resistance, so that only a very small
reverse current (I R ) flows. In this case the output voltage is
(3-6)
A diode connected as shown in Fig. 3-15 has the characteristics shown
in Fig. 3-16. R L is 500 12, and the input voltage has a peak amplitude of 50
V. Calculate the positive and negative peaks of output voltage developed
across R L . Also determine the peak load current and diode power dissipa-
tion.
solution
50 V
500 12
= 100 mA
From the forward characteristics in Fig. 3-16, when I F = 100 mA, F f = 0.9 V.
From Eq. (3-4),
£,> = 50 V-0.9 V
Peak output voltage , E P — 49.l V.
From the reverse characteristics in Fig. 3-16, when V R = — 50 V, I R = — 1
jtiA.
From Eq. (3-6),
E 0 = - 1 /a A X 500 12
Negative output voltage , E 0 — — 0.5 m V.
From Eq. (3-5),
V P ~ V F 50 V-0.9 V
p R l 500 12
\
45
Half-Wave
Rectification
Figure 3-16. Diode characteristics for Example 3-5.
Peak load current , I P = 98.2 mA.
When forward biased, the diode peak power dissipation is
P D = V F X I p = 0.9 V X 98.2 mA
= 88.38 mW
When an alternating voltage is rectified, the output is a series of
positive (or negative) half-cycles of the input waveform. It is still not direct
voltage. To convert to direct voltage (dc) a smoothing circuit (or filter) is
employed. Figure 3-17 shows a half-wave rectifier circuit with a single
capacitive filter. The capacitor, termed a reservoir capacitor , becomes charged
up almost to the input peak voltage when the diode is forward biased. When
the diode is reverse biased, the capacitor partially discharges through the
load. Since the capacitor always has some positive charge, the diode becomes
forward biased only near the peaks of input voltage. At this time, it passes a
current pulse to the capacitor to replace the charge lost to the load. The
result is that the output is a direct voltage with a superimposed ripple
waveform. The amplitude of the ripple voltage depends upon the load
resistance and capacitor values. For half-wave rectification, the ripple volt-
age frequency is the same as the input frequency.
The required value of the reservoir capacitor depends upon the load
current and the acceptable ripple voltage amplitude. Consider the ripple
waveform illustrated in Fig. 3-18. V r is the peak-to-peak ripple voltage,
^ 0 (m*x) * s the maximum output level, and £ 0(min) is the minimum output
level. Time /, is the interval between input current pulses, i.c., the time
during which the reservoir capacitor is being discharged by the load current.
Time t 2 is the duration of the input current pulse that recharges the
3 - 9.2
Half-Wave
Rectifier with
Capacitor
Smoothing
Rs
Rectified Current
waveform pulse
Figure 3-17. Circuit and output waveform for a half-wave rectifier with capacitor
smoothing.
Ripple
waveform
capacitor. From the figure it is seen that time t x depends upon the sum of the
degrees through which the input waveform passes while the output is going
from £ 0 (fnax ) to £ 0(min) . Knowing the input frequency, the total time t x can
be determined. Then using t u I L and V r , the reservoir capacitor value can be
calculated.
£o(min) = £o(max) S,n ^1
sin 0 , = JpSEEl ( 3 . 7 )
£ 0(max)
<! = (time for 90°) + (time for 180°) + (time for 0°) (3-8)
Taking the load current as a constant quantity which is discharging
the capacitor between input pulses, the simple formula C= Q/ V may be
used to calculate the reservoir capacitor value. Since (? = It,
c=^ (3-9)
46
The time t 2 can be determined as
t 2 = (time for 90°) — (time for 9 ,°) (3-10)
Determine the reservoir capacitor value for a half-wave rectifier and
smoothing circuit to supply 20 V to a load of 500 S2. Maximum ripple
amplitude is to be 10% of the average output voltage, and the input
frequency is 60 hertz (Hz).
solution
Ripple voltage amplitude = F r =10% of 20 V = 2 V.
^0(«nin)
^O(mix)
= 20 V- 1 V = 19 V
= 20 V+ 1 V = 2 1 V
From Eq. (3-7),
sin#, = ~ =0.905 #,«s65°
Since the input frequency is 60 Hz, the time period of the input waveform is
T= = 16.6 ms
and since T is the time for 360°,
time for 180° = 16.6 msx(^) = 8.3 ms
time for 90° = 4.16 ms
time for 9 { = 16.6 msx(^) = 3 ms
From Eq. (3-8),
Load current is
From Eq. (3-9),
/, =4.16 + 8.3 + 3 ms = 15.5 ms
20 V
500 S2
= 40 m/\
C =
40 mAX 15.5 ms
2V
47
Half-Wave
Rectification
Example 3-6
310 /iF
4 8
The
Semiconductor
Diode
Example 3-7
The rectifier diode used in a circuit such as that shown in Fig. 3-17
must be specified in terms of the currents and voltages that it will be
subjected to. The calculated values are the minimums that the device must
survive. Obviously, the selected diode should be able to survive greater
voltage and current levels than the calculated minimum values.
The capacitor is discharged by I L flowing for time (/ t + t 2 ) y and
recharged by a current flowing for time t 2 . The recharging current is referred
to as the peak repetitive current and is designated / FA/(rcp) . I FAf (re P ) ls directly
proportional to I L and + / 2 ) and inversely proportional to t 2 . For example,
if a load current of 1 A flows for a period of 10 ms, then to recharge the
capacitor in 1 ms a current of 10 A must flow for the 1 ms time period.
\ +t 2)
(3-11)
In the circuit shown in Fig. 3-17, R s is a small-value resistance known
as the surge limiting resistor. As its name suggests, the purpose of R s is to limit
any surge of current that may pass through the diode. Such a surge occurs
when the supply is first switched on to the rectifier circuit. Before switch-on,
the capacitor normally contains no charge, and at switch-on it will initially
behave as a short circuit. If switch-on occurs at the instant of peak input
voltage, the initial surge current flowing will be
surge) ‘
Vp
R<
If the diode can survive a specified maximum surge current, I FM(surgcV then
the surge limiting resistance is selected as
Rs--r- Vp - ( 3 - 12 )
I FM(surgc)
When the half-wave rectifier circuit is operating, the capacitor charge
remains approximately at + V P (see Fig. 3-17). This means that the diode
cathode voltage is always approximately + V p . At the peak of the negative
half-cycle the input voltage at the diode anode is — V p . In this case the
maximum reverse voltage across the diode is
E r = 2V p (3-13)
Specify the diode required for the half-wave rectifier circuit referred to
in Example 3-6. Select a suitable device from the data sheets in Figs. 3-13
and 3-14, and calculate the required value of R s .
solution
From Eq. (3-10),
49
Full-Wave
Rectification
t 2 = 4. 1 6 ms — 3 ms = 1 . 1 6 ms
and from Eq. (3-11),
T _ 40 mA X (16.6 ms)
7 ™ (rep) M6^
The diode peak repetitive current IpM(np f&570 mA.
The diode average forward current is I 0 — I L = 40 mA .
From Eq. (3-4),
Vp= Ep+ \ F = + V F
Taking the typical V F for a silicon diode as 0.7 V,
1^, — 21 +0.7 V = 21. 7 V
and from Eq. (3-13),
£*-2X21.7 V
The diode maximum reverse voltage, E R = 43.4 V.
In Fig. 3-13, the 1N4001 is stated as having 1^=50 V, / 0 = 1 A,
rep) = 10 A. Therefore, its specification is better than required for this
application. Any one of the 1N4002 through 1N4007 rectifiers could also be
used, but they have progressively higher reverse voltage specifications, and
they are all more expensive than the 1N4001. The 1N914 through 1N916
diodes (Fig. 3-14) have large enough reverse voltage specifications for this
application, but since the maximum recurrent peak forward current is 225
mA, none of them is suitable.
For the 1N4001,
IfM(* urge) = 30 A
Use Eq. (3-12):
v >
I FM(mr gc)
27.1 V
30 A
0.7 n
Two types of full-wave rectifier circuits arc shown in Figs. 3-19 and
3-20. The circuit in Fig. 3-19 uses only two diodes, but its power must be
supplied from a transformer with a center-tapped secondary winding. When
3-10
Full-Wave
Rectification
50
The
Semiconductor
Diode
fW\
Output
Figure 3-19. Full-wave rectifier circuit using two diodes and a center-tapped trans-
former.
(b) During positive
half cycle
(c) During negative
half cycle
Figure 3-20. Full-wave bridge rectifier circuit.
the transformer output voltage is positive at the top, as shown in the figure,
Z)j is forward biased and D 2 is reverse biased. During the negative half-cycle
of transformer output, D 2 is forward biased and D x is reverse biased. The
result is a load waveform composed of continuous positive half-cycles of the
diode input waveform, i.e., full-wave rectification.
Because center-tapped transformers are usually more expensive and
require much more space than additional diodes, the bridge rectifier shown in
Fig. 3-20 is the circuit most frequently used for full-wave rectification.
During the positive half-cycle of input voltage to the bridge rectifier, diodes
D x and Z) 4 conduct as shown in Fig. 3-20(b). At same time diodes D 2 and D 3
are reverse biased. Figure 3-20(c) shows diodes D 2 and D 3 forward biased
during the negative half-cycle of input, while Z>, and Z> 4 are reverse biased.
The result is that both positive and negative half-cycles of the input are
passed to load resistance R L . Also, the negative half-cycles are inverted, so
that the output is a continuous series of positive half-cycles of alternating
voltage.
Since the bridge rectifier has two forward-biased diodes in series with
the supply voltage and R L , the output voltage amplitude is
E P = V P — 2V F (3-14)
Full-wave rectifier circuits also require smoothing circuits to convert
the pulsating output to direct voltage. Figure 3-21 shows that for full-wave
rectification the capacitor discharge time is considerably less than with the
half-wave rectifier circuit. This means that, for a given load current and
ripple voltage, the reservoir capacitor and diode peak repetitive current can
both be much smaller.
From Fig. 3-21, the time /, becomes
= (time for 90°) + (time for 9 X ) (3-15)
For the two-diode full-wave rectifier circuit in Fig. 3-19, the maximum
diode reverse voltage is E R — 2 V p , just as for the half-wave rectifier. This is
not true in the case of the bridge rectifier circuit. Referring again to Fig.
3-20(b), note that the peak cathode voltage of D 3 is V P — ( V F across /),). Also
note that the anode voltage of Z) 3 is zero. Therefore, the maximum reverse
51
Full-Wave
Rectification
Ripple
waveform
Figure 3-21. Output from full-wave rectifier with capacitor smoothing circuit.
52
The
Semiconductor
Diode
Example 3-8
voltage across D 3 and all other diodes is V P .
E r -V p (3-16)
Apart from Eqs. (3-14) to (3-16), all other equations derived for the
half-wave rectifier and smoothing circuit also apply to the bridge rectifier.
Determine the reservoir capacitor value and specify the diodes for a
bridge rectifier and smoothing circuit to supply the load specified in Exam-
ple 3-6.
solution
From Examples 3-6 and 3-7,
F r = 2 V
£<*min)=19V
^max) = 21V
0, = 65°
time for 90° = 4. 1 6 ms
time for 9 { = 3 ms
I L = 40 mA
t 2 = 1.16 ms
From Eq. (3-15),
From Eq. (3-9),
q =4.16 ms + 3 ms = 7. 16 ms
40 mAX 7.16 ms
2 V
Capacitor C= 143 fiF.
From Eq. (3-1 1),
40 mAX (7.16 ms+ 1.16 ms)
W*)- 1.16 ms
Diode peak repetitive current, I FM( ^^287 mA.
Since each pair of diodes is conducting on alternate half-cycles:
Diode average forward current.
53
Diode Switching
Time and
Frequency
Response
/q-4/2
— 40 mA/2 = 20 mA
From Eqs. (3-14) and (3-16),
E R = v p = 21 V + 2(0.7 V)
Diode maximum reverse voltage, E R = 22 A V.
Once again a 1N4001 is better than required.
There are a great many circuit applications for semiconductor diodes
other than rectification. Some of these require the diodes to switch very
rapidly from forward to reverse bias, and vice versa. Most diodes will switch
rapidly into the forward-biased condition, however, there is always a longer
switch-off time due to the diffusion capacitance. This switch-off time,
designated as the reverse recovery time (/„), limits the maximum frequency at
which the device may be operated.
Figure 3-22(a) illustrates the effect of an input pulse on the diode
current. When the pulse goes negative, instead of switching off sharply, the
diode conducts in reverse. The reverse current ( I R ) is initially equal to Ip*
but it gradually falls off to the reverse saturation current level ( I s ). The
reverse current occurs because at the instant of reverse bias there are charge
carriers crossing the junction depletion region, and these must be removed.
The reverse recovery time is the time required for the current to decrease to
Is-
The reverse recovery time is usually measured in nanoseconds (ns),
which are seconds X10“ 9 . Typical values of for switching diodes range
from 4 to 50 ns. The switching time obviously limits the maximum operating
frequency of the device. If reverse current is to be avoided or minimized, the
diode must be switched off relatively slowly. Figure 3-22(b) shows that, if the
input frequency is such that 7'=2X/ rr , then the diode is conducting almost
as much in reverse as it is in the forward direction. In this case it is no longer
behaving as a one-way device. To minimize the effect of the reverse current,
the time period of the operating frequency should be at least ten times t n
[Fig. 3-22(c)].
3-11
Diode
Switching
Time and
Frequency
Response
54
The
Semiconductor
Diode
Example 3-9
Input
voltage
1
(a) Reverse recovery time
(b) Effect of t„ with
high frequency input
(c) t„ effect with
low frequency input
Figure 3-22. Reverse recovery time and its effect on high- and low-frequency inputs.
Calculate the maximum operating frequency for a diode with reverse
recovery time of 4 ns.
solution
T^\0xt n
Therefore,
1 1
55
Diode Logic
Circuits
T lOX^
A logic circuit produces an output voltage which is either high or low ,
depending upon the levels of several input voltages. The two basic logic
circuits are the AND gate and the OR gate.
Figure 3-23 shows the circuit diagram of a diode AND gate. The
circuit has a single output terminal at the diode common anodes and three
inputs at the device cathode terminals. (An AND gate could have almost
any number of input terminals from 2 up to perhaps 50.) The diode anodes
are connected via resistor /?, to a supply of Kcc-SV.
If one or more of the input terminals is grounded, current flows from
the supply through R { and through the forward-biased diodes to ground. In
this case, the output voltage is just V F above ground (0.7 V for silicon). The
output is said to be low. When input levels of 5 V are applied to all three
input terminals, none of the diodes is forward biased, and no significant volt
drop occurs across R v Thus, the output voltage is equal to *cc> and it is
referred to as a high output level.
The AND gate gives a low output voltage when one or more of its
inputs are low and a high output when input A is high and input B is high
and input C is high. Hence the name AND gate.
3-12
Diode Logic
Circuits
Figure 3-23. Circuit of a three-input diode AND gate.
56
The
Semiconductor
Diode
3-13
Diode Clipper
Circuits
The circuit diagram of a three-input terminal OR gate is shown in Fig.
3-24. Again, the gate could have two or more inputs. It is fairly obvious that
the output voltage of the OR gate is low when all three inputs are low. Now
suppose that a +5-V input is applied to terminal A, while terminals B and
C remain grounded. Diode Z), becomes forward biased, and its cathode
voltage (i.e., the output voltage) is +(5 V- V F ). The output is high. Diodes
D 2 and D 3 are reverse biased with 4- V 0 on the anodes and ground at the
cathodes.
As its name implies, the OR gate produces a high output when a high
input level is applied to terminal A or terminal B or terminal C.
Both AND and OR gates can be designed and constructed using
discrete components. Alternatively, small integrated-circuit (IC) packages
are available, each of which contain many diodes already fabricated in the
form of the desired gate.
The function of a clipper circuit is to clip off an unwanted portion of a
waveform. A half-wave rectifier can be described as a clipper, since it passes
only the positive (or negative) portion of an alternating waveform and clips
off the other portion. In fact, a diode series clipper is simply a half-wave
rectifier circuit.
Figure 3-25 shows negative and positive series clipper circuits. It is seen that
in each case the diode is connected in series with the load resistor R L . The
negative clipper passes the positive half-cycle of the input and removes the
negative half-cycle. The positive clipper passes the negative half-cycle and
clips off the positive portion.
Two shunt clipper circuits are illustrated in Fig. 3-26. Here the diodes are
connected in shunt (or parallel) with R L . For the negative shunt clipper , Fig.
3-26(a), diode D x is reverse biased while the input is positive. Only a small
volt drop occurs across /?,, due to the output current 7 0 . This means that the
57
Diode Clipper
Circuits
(b) Positive series clipper
Figure 3-25. Negative and positive series clipping circuits.
(a) Negative shunt clipper
Figure 3-26. Negative and positive shunt clipping circuits.
58
The
Semiconductor
Diode
output voltage V 0 is approximately equal to the positive input peak + E.
When the input is — E y D x if forward biased and the circuit output becomes
— V F . The negative half of the input waveform is effectively clipped off. The
output of the positive shunt clipper , Fig. 3-26(b), is + V F and — E y as
illustrated.
Example 3-10
A positive shunt clipper circuit has an input voltage of E = ± 5 V. The
negative output voltage is to be —4.5 V when I 0 is 2 mA. Determine the
value of R x , and specify the diode forward current and reverse voltage.
solution
When the diode is reverse biased,
Vq = E — I 0 R X
Therefore,
„ E-y 0 5 V— 4.5 V
1 ' 2 mA
= 250 £2
Diode reverse voltage is V R ^ E = 5 V.
When the diode is forward biased,
E-V F 5 V — 0.7 V
F R x 250 £2
= 17.2 mA
3-14
Voltage
Multiplier
Circuit
The dc output voltage obtainable from an ordinary (half-wave or
full-wave) rectifier circuit with a smoothing capacitor cannot be larger than
the peak input voltage. With a voltage multiplier circuit an output voltage can
be produced which is two or more times the peak value of the input voltage.
Figure 3-27 shows a diode-capacitor voltage multiplier circuit and
illustrates its operation.
When the input voltage is 4- V py Fig. 3-27(b), diode D x is forward
biased, and a charging current /, flows to capacitor C x . At this time
Cj becomes charged with the polarity shown to a level of approximately V p .
This assumes that the diode forward voltage V F is very much less than V p .
When the input goes to — V py Fig. 3-27(c), D x is reverse biased, and D 2
becomes forward biased. The voltage V 2 applied to the circuit of C 2 and
D 2 is the sum of the input voltage — V p and V cx . Note that the polarities are
X'
Input
o )h
2 l/„ |2 V p
1
C, ' C.
°7 f 0 3 i |0 4 ^
X -
X"
~ vp m,
(a) Voltage multiplier circuit
r i
1
\.Vf
r i
i- i
1
v c\ * V r
(b) Effect of positive input
t/ C2 = 2 V,
~ 11 ^
?
1 i
1
1
c '
)h + L
1-
(c) Effect of negative input
Figure 3-27. Diode-capacitor voltage multiplier circuit.
such that the voltages add to give V 2 —2 V P . Again assuming that V F is much
less than V* capacitor C 2 is charged to almost 2 V p with the polarity shown
on the circuit diagram.
Now consider the effect on D 3 and C 3 when the input goes positive
once again. Referring to Fig. 3-27(a), the voltage V 3 is the sum of + V p (at
the input), K C1 , and V C T
v 3 = V F + V CI + V C2
Taking careful note of the voltage polarities,
V 2 -V p + {-V p ) + 2 V p
-2K,
59
Voltage
Multiplier
Circuit
Capacitor C 3 is charged to 2K,, with the polarity illustrated. The total
voltage measured across capacitors C, and C 3 is now 3 V P .
60
The
Semiconductor
Diode
The addition of capacitor C 4 and diode Z) 4 gives a total voltage of 4 V p
across C 2 and C 4 . Further capacitor and diode additions produce progres-
sively increasing multiples of the input voltage.
One application of this circuit is found in some pocket calculators
which use gas-discharge display devices requiring perhaps 200 V to operate
them. By means of a voltage multiplier circuit the low-level battery voltage
is increased to the desired potential.
Glossary
of Important
Terms
Diode. Two-electrode device — a /^-junction with terminals.
Anode. Positive terminal for forward-biased diode — the />-side of a pn-
junction.
Cathode. Negative terminal for forward-biased diode — the n-side of a
/m-junction.
Diode forward characteristics. Plot of forward current versus forward-bias
voltage.
Diode reverse characteristic. Plot of reverse current versus reverse-bias
voltage.
Piecewise linear characteristic. Straight-line approximation of diode char-
acteristic.
DC load line. Line plotted on diode characteristics to represent all circuit
conditions.
Quiescent point. Point on characteristics at which device is biased, defined
by device current and voltage.
Dynamic resistance. Reciprocal of the slope of a forward -biased diode
characteristic beyond the knee.
Small-signal ac equivalent circuit. Equivalent circuit for forward-biased
diode experiencing small changes in forward current.
Reverse saturation current. Small, temperature-dependent, constant cur-
rent that flows across a reverse-biased junction.
Peak repetitive current. Maximum short-term forward current pulse that
may be repeated continuously through a diode.
Half-wave rectifier. Diode circuit which passes only the positive (or nega-
tive) half-cycles of an alternating input voltage.
Full- wave rectifier. Diode circuit which converts an alternating input
voltage to a continuous series of positive (or negative) half-cycles.
Bridge rectifier. Full-wave rectifier circuit using four diodes.
Capacitor smoothing circuit. Capacitor and resistor circuit employed to
convert the output waveform of a rectifier to direct voltage.
Reservoir capacitor. Large capacitor used in a capacitor smoothing
circuit.
Ripple. Small alternating voltage superimposed upon the direct voltage
output of a capacitor smoothing circuit.
Peak repetitive current. Peak level of recurring pulse of current through a
rectifier.
Surge current. Current which may flow through a rectifier for a short time
when the supply is switched on.
Surge limiting resistor. Resistor connected in series with a rectifier to limit
the surge current.
Average forward current. Average current flowing when a rectifier is
forward biased.
Reverse recovery time. Time required for a diode to switch from on to off.
AND gate. Logic circuit which provides an output when inputs are present
at terminals A and B and C, etc.
OR gate. Logic circuit which provides an output when an input is present
at terminals A or B or C, etc.
Positive clipper. Clipper circuit which removes the positive portion of an
input.
Negative clipper. Clipper circuit which removes the negative portion of an
input.
Voltage multiplier circuit. Diode capacitor circuit which produces a direct
output voltage which is a multiple of the supply voltage.
3-1. Sketch the symbol for a semiconductor diode, labeling the anode and
cathode, and showing the polarity and current direction for forward
bias. Also show the direction of movement of charge carriers when
the device is (a) forward biased, and (b) reverse biased.
3-2. Sketch typical forward and reverse characteristics for a germanium
diode and for a silicon diode. Discuss the characteristics, and show'
the effects of temperature change.
3-3. Draw the small-signal ac equivalent circuit for a forward-biased
diode, and briefly explain its origin.
3-4. Sketch a half-wave rectifier circuit and a two-diode full-wave recti-
fier. Explain the operation of each and show the output waveforms
that would result in each case for a sinusoidal ac input.
3-5. Sketch the circuit of a bridge rectifier and explain its operation. Show
the output waveform that results from a sinusoidal ac input.
3-6. Sketch a capacitor smoothing circuit for use with a rectifier. Show the
output waveform when the smoothing circuit is connected to (a) a
half-wave rectifier, (b) a full-wave rectifier. In each case assume a
sinusoidal input and explain the shape of the output waveform.
3-7. Define the following quantities: peak reverse voltage, reverse break-
down voltage, steady-state forward current, peak surge current, static
reverse current, peak repetitive current, reverse recovery time.
3-8. Sketch the circuit of a diode AND gate. Briefly explain the circuit
operation.
3-9. Repeat Question 3-8 for a diode OR gate.
3-10. Sketch the circuit of a positive series clipper circuit and show the
input and output waveforms. Repeat for a negative scries clipper.
61
Review
Questions
Review
Questions
62
The
Semiconductor
Diode
Problems
3-11. Repeat Question 3-10 for a positive shunt clipper and for a negative
shunt clipper.
3-12. Sketch a voltage multiplier circuit which will double the supply
voltage. Briefly explain how the circuit operates and show how
additional stages should be added to increase the voltage multiplying
effect.
3-1. A diode having the characteristic shown in Fig. 3-28 is required to
pass 75 mA from a supply of 5 V. Draw the dc load line and
determine the resistance that must be connected in series with the
diode. If the supply is reduced to 3.5 V, what will be the new value of
v
Figure 3-28.
3-2. A diode with the forward characteristic shown in Fig. 3-29 is con-
nected in series with a 250-fi resistance and a 5-V supply. Determine
the diode current, and find the new current when the resistance is
changed to 100 fi.
Figure 3-29.
3-3. A 60-V reverse bias is applied to a diode with the characteristics
shown in Fig. 3-30. Determine the current that flows, and estimate
the current level when the device temperature is increased by 10° C.
3-4. Draw the piecewise linear characteristic for a silicon diode with a 3-ft
dynamic resistance and a maximum forward current of 75 mA.
3-5. For the diodes in Questions 3-3 and 3-4 draw the piecewise linear
characteristics, and determine the values of dynamic resistance in
each case.
3-6. A diode which has the characteristics shown in Fig. 2-11 is to pass a
forward current of 20 mA when the supply is 1 V. Determine the
value of resistance that must be connected in series with the diode.
Also determine the level of forward current that flows when the
resistance is doubled.
3-7. If the diode described in Question 3-6 is connected in series with a
1.5-V supply and a 20-12 resistor, determine the current that flow’s (a)
when the diode is forward biased, (b) when reverse biased.
3-8. A diode which has the characteristics given in Fig. 3-30 is employed
as a half-wave rectifier. The series resistor R L is 1 k!2, and the input
voltage amplitude is ±50 V. Calculate the positive and negative
amplitudes of the output waveform. Also calculate peak load current
and diode peak power dissipation.
3-9. Determine the value of reservoir capacitor for a half-w-ave rectifier
and smoothing circuit to supply 12 V to a 100-12 load. Maximum
ripple voltage amplitude is to be 20% of the average output voltage,
and input frequency is 60 Hz.
3-10. Specify the diode required for the circuit described in Question 3-9.
63
Problems
64
The
Semiconductor
Diode
Select a suitable device from the data sheets in Figs. 3-13 and 3-14.
Also calculate the required value of the surge limiting resistance.
3-11. Repeat Question 3-9 for a full-wave rectifier circuit.
3-12. Repeat Question 3-10 for a full-wave rectifier circuit.
3-13. Calculate the value of a smoothing capacitor which, when connected
to the circuit described in Question 3-8, will give a dc output with a
1-V peak-to-peak ripple.
3-14. Calculate the maximum frequency at which a 1N914 diode should be
operated. Repeat for a 1N917 diode.
3-15. The input voltage to a positive shunt clipper circuit is £*=±15 V.
The output current is to be 5 mA when the output voltage is — 14 V.
Determine the value of series resistance and specify the diode.
3-16. A shunt clipper is to remove the negative portion of a ±7-V square
wave. The output voltage is to be at least +5.7 V when the output
current is 3 mA. Sketch the circuit and specify the components.
The
Junction
Transistor
A bipolar junction transistor (BJT) has two pn -junctions; thus, an under-
standing of its operation can be obtained by applying /^-junction theory.
The currents that flow in a transistor are similar to those that flow across a
single junction, and the transistor equivalent circuit is simply an extension of
the ^-junction equivalent circuit. Since the transistor is a three-terminal
device, there are three possible sets of current-voltage characteristics by
which its performance may be specified.
A junction transistor is simply a sandwich of one type of semiconductor
material (p- type or n-type) between two layers of the other type. The
cross-sectional view of a layer of n-type material between two layers of p- type
is shown in Fig. 4- 1(a). This is described as a pnp transistor. Figure 4- 1(b)
shows an npn transistor , consisting of a layer of p-type material between two
layers of n-type. For reasons which will be understood later, the center layer
is called the base , one of the outer layers is called the emitter , and the other
outer layer is referred to as the collector. The emitter, base, and collector are
CHAPTER
4
4-1
Introduction
4-2
Transistor
Operation
65
66
The
Junction
Transistor
Emitter-base Collector-base
junction junction
(a) pnp transistor
£
(b) npn transistor
Figure 4-1. pnp and npn transistors.
Emitter-base Collector-base
junction junction
B
provided with terminals which are appropriately labeled E, B, and C. Two
/w -junctions exist within each transistor; the collector-base junction and the
emitter-base junction . Each of these junctions has all the characteristics dis-
cussed in Chapters 2 and 3.
Figure 4-2(a) and (b) illustrates the depletion regions, barrier poten-
tials, and electric fields at the junctions of pnp and npn transistors. These
were originally explained in Section 2-2. Although it is not shown in the
illustrations, the center layer in each case is made very much narrower than
the two outer layers. Also, the outer layers are much more heavily doped
than the center layer. This causes the depletion regions to penetrate deeply
into the base, and thus the distance between the emitter-base (EB) and
collector-base (CB) depletion regions is minimized. Note that the barrier
potentials and electric fields axe positive on the base and negative on the
emitter and collector for the pnp device, and negative on the base and
positive on the emitter and collector for the npn device.
Consider the npn transistor shown in Fig. 4-3. For normal (linear)
transistor operation, the EB junction is forward biased and the CB junction
is reverse biased. (Note the battery polarities). The forward bias at the EB
junction causes electrons to flow from the n-type emitter to the p~ type base.
The electrons are “emitted” into the base region, hence the name emitter.
Holes also flow from the p- type base to the n-type emitter, but since the base
is much more lighdy doped than the collector, almost all the current flow
across the EB junction consists of electrons entering the base from the
emitter. Therefore, electrons are the majority carriers in an npn device.
(a) pnp transistor
67
Transistor
Operation
Depletion regions penetrating
deeply into lightly doped base
Barrier potentials: positive on
the n side, negative on the p side
Electric field at junction'
(b) npn transistor
Depletion regions penetrating
deeply into lightly doped base
Barrier potentials: positive on
n side, negative on p side
Electric field at junctions.
Figure 4-2. Barrier potentials and depletion regions for unbiased pnp and npn transis-
tors.
The reverse bias at the CB junction causes the depletion region at that
junction to be widened and to penetrate deeply into the base, as shown in
Fig. 4-3. Thus, the electrons crossing from the emitter to the base arrive
quite close to the negative-positive electric field at the CB depletion region.
Since electrons have a negative charge, they are drawn across the CB
junction by this electric field. They are “collected.”
68
The
Junction
Transistor
Figure 4-3. Biased npn transistor.
Some of the charge carriers entering the base from the emitter do not
reach the collector, but flow out via the base connection and around the
base-emitter bias circuit. However, the path to the CB depletion region is
very much shorter than that to the base terminal, so that only a very small
percentage of charge carriers flows out of the base terminal. Also, because
the base region is very lightly doped, there are few holes available in the
base to recombine with the charge carriers from the emitter. The result is
that about 98% of the charge carriers from the emitter are collected at the
CB junction, and flow through the collector circuit via the bias batteries
back to the emitter.
Another way of looking at the effect of the reverse-biased CB junction
is from the point of view of minority and majority charge carriers. It has
already been shown that a reverse-biased junction opposes the flow of
majority carriers and assists the flow of minority carriers. Majority carriers
are, of course, holes coming from the />-side of a junction and electrons
coming from the n-side. Minority carriers are holes coming from the n-side
and electrons from the />-side (see Section 1-9). In the case of the npn
transistor, the charge carriers arriving at the CB junction are electrons (from
the emitter) traveling through the p - type base. Consequently, to the CB
junction they appear as minority charge carriers, and the reverse bias assists
them to cross the junction.
Since the EB junction is forward biased, it has the characteristics of a
forward-biased diode. Substantial current will not flow until the forward bias
is about 0.7 V for a silicon device or about 0.3 V for germanium. Reducing
the level of the EB bias voltage in effect reduces the /^-junction forward bias
and thus reduces the current that flows from the emitter through the base to
the collector. Increasing the EB bias voltage increases this current. Reducing
the bias voltage to zero, or reversing it, cuts the current off completely. Thus,
variation of the small forward-bias voltage on the EB junction controls the
emitter and collector currents, and the EB controlling voltage source has to
supply only the small base current.
The pnp transistor behaves exactly the same as an npn device, with the
exception that the majority charge carriers are holes. As illustrated in Fig.
4-4, holes are emitted from the p- type emitter across the forward-biased EB
junction into the base. In the lightly doped n-type base, the holes find few
electrons to recombine with. Some of the holes flow out via the base
terminal, but most are drawn across to the collector by the positive-negative
electric field at the reverse-biased CB junction. As in the case of the npn
device, the forward bias at the EB junction controls the collector and emitter
currents.
Although one type of charge carrier is in the majority, two types of
charge carrier (holes and electrons) are involved in current flow through an
npn or pnp transistor. Consequently, these devices are sometimes termed
bipolar junction transistors (BJT). This is to distinguish them from field-effect
transistors (Chapter 12), which use only one type of charge carriers and are
therefore termed unipolar devices.
To Summarize : A transistor is a sandwich of pnp or npn semiconductor
material. The outer layers are called the emitter and the collector, and the
center layer is termed the base. Two junctions are formed, with depletion
regions and barrier potentials set up at each. The barrier potentials are
negative on the />-side and positive on the n-side.
The EB junction is forward biased, so that charge carriers are emitted
into the base. The CB junction is reverse biased, and its depletion region
penetrates deeply into the base. The base section is made as narrow as
69
Transistor
Operation
Figure 4-4. Biased pnp transistor.
70
The
Junction
Transistor
possible so that charge carriers can easily move across from emitter to
collector. The base is also lightly doped, so that few charge carriers are
available to recombine with the majority charge carriers from the emitter.
Most charge carriers from the emitter flow out through the collector; few
flow out through the base. Variation of the EB junction bias voltage alters
the base, emitter, and collector currents.
4-3
Transistor
Currents
The various current components which flow within a transistor are
once again illustrated in Fig. 4-5. The current flowing into the emitter
terminal is referred to as the emitter current and identified as I E . For the pnp
device shown, I E can be thought of as a flow of holes from the emitter to the
base. Note that the indicated l E direction external to the transistor is the
conventional current direction. Base current I B and collector current I c are also
shown external to the transistor as conventional current direction. Both I c
and I B flow out of the transistor while I E flows into the transistor. Therefore,
^e~^c + ^b ( 4 - 1 )
As already discussed, almost all of I E crosses to the collector, and only
a small portion flows out of the base terminal. The portion of I E which flows
across the collector-base junction is designated a dc I E , where a dc (alpha dc) is
typically 0.96 to 0.99.Thus,a dc I E is typically 96% to 99% of I E .
Because the CB junction is reverse biased, a very small reverse satura-
tion current flows across the junction. This is shown as I CB0 in Fig. 4-5, and
it is termed the collector- to- base leakage current . J CB0 is made up of minority
charge carriers, which in the case of a pnp device are holes moving from the
n -type base to the />-type collector.
Figure 4-5. Currents in a pnp transistor.
The collector current is obviously the sum of a dc I E and I CB0 :
(4-2)
71
Transistor
Currents
= -h In
Rearranging Eq. (4-2),
«dc =
(4-3)
Since I CB0 is very much smaller than I c , an approximation for is
a
dc' '
k
(4-4)
Therefore, a dc is approximately the ratio of collector current to emitter
current. a dc is also referred to as the common base current gain factor. When
using h- parameters (Section 4-9), the designation h FB may be employed
instead of a dc .
Using Eq. (4-1) to substitute for I E into Eq. (4-2),
*C ~ a dc Uc 4" ?b) + IcBO
“«dc / C+“ d
W- a dc ) = a d ck 4" IcBO
or
k
a dc ?B + IcBO
l-a dc 1 _a dc
(4-5)
All the foregoing formulas are just as valid for an npn transistor as for a pnp
device.
Calculate the values of collector current and emitter current for a
transistor with a dc = 0.98 and I C bo~^ The base current is measured as
100 /iA.
solution
From Eq. (4-5),
Ic
a dJs + IcBO
\-a dc \~a dc
Example 4-1
Therefore,
72
The
Junction
Transistor
Example 4-2
0.98 X 100 ^A 5/iA
1-0.98 + 1-0.98
= 4.9 mA + 0.25 mA = 5.15 mA
From Eq. (4-1),
1e~ h
Therefore,
I E = 5.15 mA + 100 /uA = 5.25 mA
According to Eq. (4-4), the ratio of l c to 1 E should approximately
equal a dc . Checking: 5.15 mA/5.25 mAs»0.98.
Equation (4-5) may be written as
/ c = j8 dc / i + (/3 dc + l)/ cso (4-6)
where /? dc = a/( 1 — a). Because I CBO is very much less than I B , an approxi-
mation for Eq. (4-6) is I c z&fi dc I B . Therefore,
(4-7)
l B
Thus, j8 dc (beta dc ) is approximately the ratio of collector current to base
current. /? dc is also referred to as the dc common emitter current gain factor , and
the designation h FE (Section 4-9) is frequently used instead of fi dc .
The collector and base currents of a certain transistor are measured as
I c = 5.202 mA, I B = 50 fiA, I CBO = 2 fiA
(a) Calculate a dc , /2 dc , and I E .
(b) Determine the new level of I B required to make l c — 10 mA.
solution (a)
From Eq. (4-6), / c = ^ dc / fl + (/J dc + 1)/ CB0 .
Therefore, 5.202 mA = ( j8 dc X 50 fi A) + ( j8 dc +1)2 fiA
= /3 dc (50 fiA+2 /xA) + 2 jiA
and
100
73
Transistor Symbols
and Voltages
_ 5.202 m A — 2 /a A _
^ dc 52 100
From Eq. (4-1), 7 £ = / c + / B .
Therefore, 7^ = 5.202 mA + 50 /iA = 5.252 mA
From Eq. (4-2), I c = <*6 Je + j cbo-
Therefore, 5.202 mA = (a dc X 5.252 mA) + 2 pA
5.202 mA — 2 pA
5.252 mA
= 0.99
solution (b)
From Eq. (4-6), I c = P dc I B + (P dc + 1 )I C bo-
Therefore, 10 mA = (100X I B ) + (101 X2 pA)
1b
10 mA -202 pA
100
= 97.98 pA
The symbols employed for npn and pnp transistors are shown in Fig.
4-6(a) and (b). The arrowhead is always at the emitter terminal, and in each
case its direction indicates the conventional direction of current flow . For the npn
transistor, the arrowhead points from the p - type base to the n-type emitter
terminal. For the pnp transistor, it points from the p - type emitter toward the
rt-type base terminal. Thus, the arrowhead is always from p to n.
The bias and supply voltage polarities for npn and pnp transistors are
shown in Fig. 4-7. As was the case with the transistor type, the bias polarities
are indicated by the arrowhead direction. For an npn transistor [Fig. 4-7(a)]
4-4
Transistor
Symbols
and Voltages
(a) npn transistor symbol (b) pnp transistor symbol
n-type
collector
P type
base
n-type
emitter
Arrowhead is in
conventional current
direction, fromp ton
p-type
collector
ntype
base
p-type
emitter
Figure 4-6. Transistor symbols.
(b) pnp bias polarities
74
The
Junction
Transistor
4-5
Common
Base
Characteristics
4 - 5.1
Common
Base
Circuit
Connection
(a) npn bias polarities
0.7 V for silicon
0.3 V for germanium
0.7 V for silicon
0.3 V for germanium
Figure 4-7. Transistor bias voltage polarities.
the base is biased positive with respect to the emitter, and the arrowhead
points from the (positive) base to the (negative) emitter. The collector is then
biased to a higher positive level than the base. For a pnp device [Fig. 4-7(b)],
the base is negative with respect to the emitter. The arrowhead points from
the (positive) emitter to the (negative) base, and the collector is then more
negative than the base.
Typical base-emitter voltages for both npn and pnp transistors are 0.7
V for silicon and 0.3 V for germanium. Typical collector-to-base voltages
might be anything from 0 to 20 V for most types of transistors, although in
many cases the collector-to-base voltage may be greater than 20 V.
The transistor is normally operated with its CB junction reverse biased
and its BE junction forward biased. In the case of a switching transistor (i.e.,
a transistor that is not operated as an amplifier but is either switched on or
off), the CB junction may become forward biased, but only by about 0.5 V.
Also in transistor switching circuits (and some others) the BE junction can
become reverse biased. Most transistors will not survive more than about 5 V
of reverse bias on the BE junction.
To investigate the characteristics of a two-terminal device (such as a
diode), several levels of forward or reverse bias voltage are applied and the
corresponding currents that flow are measured. The characteristics of the
device are then derived by plotting the graphs of current against voltage.
Since a transistor is a three-terminal device, there are three possible config-
urations in which it may be connected to study its characteristics. From each
of these configurations three sets of characteristics may be derived.
Consider Fig. 4-8. A pnp transistor is shown connected with its base
terminal common to both the input (EB) voltage and the output (CB)
voltage. For this reason, the transistor is said to be connected in common base
configuration. Voltmeters and ammeters are connected to measure input
and output voltages and currents.
Figure 4-8. Circuit for determining common base characteristics.
4 - 5.2
Input
Characteristics
4 - 5.3
Output
Characteristics
istics are plotted for I E = 2 mA, 3 mA, etc.
To determine the input characteristics, the output (CB) voltage is
maintained constant, and the input (EB) voltage is set at several convenient
levels. For each level of input voltage, the input current I E is recorded. 1 E is
then plotted versus Veb to give the common base input characteristics shown in
Fig. 4-9.
Since the EB junction is forward biased, the common base input
characteristics are essentially those of a forward biased pn junction. Figure
4-9 also shows that for a given level of input voltage more input current
flows when higher levels of CB voltage are employed. This is because larger
CB (reverse bias) voltages cause the depletion region at the CB junction to
penetrate deeper into the base of the transistor, thus shortening the distance
and the resistance between the EB and CB depletion regions.
The emitter current ( I E ) is held constant at each of several fixed levels.
For each fixed level of 4 . the output voltage (Vcb) is adjusted in convenient
steps, and the corresponding levels of collector current (/ c ) are recorded. In
this way, a table of values is obtained from which a family of output
characteristics may be plotted. In Fig. 4-10 the corresponding I c and ^CB
values obtained when I E was held constant at 1 mA arc plotted, and the
resultant characteristic is identified as I E — 1 mA. Similarly, other character-
Figure 4-9. Common base input characteristics.
76
The
Junction
Transistor
The common base output characteristics in Fig. 4-10 show that for
each fixed level of I E , I c is almost equal to I E and appears to remain
constant when ^CB is increased. In fact, there is a very small increase in I c
with V C B increase. This is because the increase in collector-to-base bias
voltage ( V CB ) expands the CB depletion region, and thus shortens the
distance between the two depletion regions. With I E held constant, however,
the I c increase is so small that it is usually noticeable only for large ^CB
variations.
As shown in Fig. 4-10, when ^CB is reduced to zero I c still flows. Even
when the externally applied bias voltage is zero, there is still a barrier
potential existing at the CB junction, and this assists the flow of I c . The
charge carriers which make up I c constitute minority carriers as they cross
the CB junction. Thus, the reverse-bias voltage ( V CB ) and the (unbiased) CB
barrier potential assist the flow of the l c charge carriers. To stop the flow of
charge carriers the CB junction has to be forward biased. Consequently, as
illustrated, I c is reduced to zero only when V CB is increased positively. The
region of the graph for CB forward biased is known as the saturation region
(Fig. 4-10). The region in which the junction is reverse biased is named the
active region , and this is the region in which a transistor is normally operated.
If the reverse-bias voltage on the CB junction is allowed to exceed the
maximum safe limit specified by the manufacturer, device breakdown may
occur. Breakdown, illustrated by the broken lines on Fig. 4-10, can be
caused by either (or both) of two effects. One of these is the same effect
which causes diode breakdown. The other effect is the result of the CB
depletion region penetrating into the base until it makes contact with the EB
depletion region. This condition is known as punch through or reach through.
When it occurs large currents can flow, possibly destroying the device. The
extension of the depletion region is, of course, the direct result of increase in
Saturation Active region
v cb
Figure 4-10. Common base output characteristics (or collector characteristics).
Current gain Output Note that for / f = 2 mA, this
characteristics characteristics line (representing l c ) is always
Figure 4-11. Derivation of common base current gain characteristics.
Vcb- Therefore, it is very important to maintain V CB below the maximum
safe limit specified by the device manufacturer.
The current gain characteristics (also referred to as forward transfer character-
istics) (Fig. 4-11) are obtained experimentally by holding V CB fixed at a
convenient level, and recording the I c levels measured for various settings of
I E . I c is then plotted versus I E , and the resultant graph is identified
according to the V CB level.
The current gain characteristics can also be derived from the common
base output characteristics as illustrated in Fig. 4-11. A vertical line is drawn
through a selected value of and corresponding values of I E and I c are
read off along this line. The values of I c are then plotted versus I E> and the
characteristic is labeled with the V C B employed.
From the common base output characteristics shown in Fig. 4-11,
derive the current gain characteristics for V CB = 2 V and for I'c.-ev,
solution
On the output characteristics draw a vertical line at V C b- 2 V(Fig. 4-11).
Where the line intersects the output characteristics at point A , read / c = 0.95
mA for / £ = 1 mA. Now plot point C at / c = 0.95 mA on the vertical axis and
l E = 1 mA on the lefthand horizontal axis. Returning to the output char-
acteristics, read l c — 3.95 mA at 1 E = 4 mA and Vcb- 2 V. point B. Now plot
point D at 7 C = 3.95 mA on the vertical axis and I E = 4 mA on the horizontal
axis. Draw a line through points C and D to give the current gain
characteristic for V CB = 2 V. Repeat the above procedure for V CB = 6 V.
77
Common
Base
Characteristics
4-5.4
Current
Cain
Characteristics
Example 4-3
Example 4-4
A transistor connected in common base configuration has the char-
acteristics shown in Figs. 4-9 to 4-11. V EB =0.1 V and V CB = 6 V. Determine
I E and I c .
solution
From the input characteristics (Fig. 4-9), at ^be~ O-? V and y a - e v,
I e p & 2 mA. From the output characteristics (Fig. 4-10), at I'c-SV and
I e = 2 mA, 7 c «s;1.95 mA. From the current gain characteristics (Fig. 4-11), at
V CB = & V and I E = 2 mA, 7 C «1.95 mA.
4-6
Common
Emitter
Characteristics
4-6.1
Common
Emitter
Circuit
Connection
Figure 4-12 shows the circuit employed for determining transistor
common emitter characteristics. The input voltage is applied between B and
E terminals, and the output is taken at C and E terminals. Therefore, the E
terminal is common to both input and output. Input and output voltages
and currents are measured by voltmeters and ammeters as shown.
4-6.2
Input
Characteristics
To determine the input characteristics, V CE is held constant, and I B
levels are recorded for several levels of ^ BE' Ib is then plotted versus ^BE’ as
shown in Fig. 4-13. It can be seen that the common emitter input character-
istics (like the common base input characteristics) are those of a forward-bi-
ased /^-junction. However, I B is only a small portion of the total current (7 £ )
which flows across the forward-biased BE junction. Figure 4-13 also shows
that, for a given vlaue of V BE , less I B flows when higher levels of V CE are
employed. This is because the higher levels of ^CE provide greater CB
junction reverse bias, resulting in greater depletion region penetration into
the base, and causing the distance between the CB and EB depletion regions
to be shortened. Consequently, more of the charge carriers from the emitter
flow across the CB junction and fewer flow out via the base terminal.
78
Figure 4-12. Circuit for determining common emitter characteristics.
Figure 4-13. Common emitter input characteristics.
To determine a table of values for plotting the common emitter output
characteristics, I B is maintained constant at several convenient levels. At
each fixed level of I B , ^ CE is adjusted in steps, and the corresponding values
of I c are recorded. For each level of 7 fl , I c is plotted versus V CE' This gives a
family of characteristics which are typically as illustrated in Fig. 4-14.
Since I E is not held constant, as in the case of the common base output
characteristics, the shortening of the distance between the depletion regions
(when ^CE is increased) draws more charge carriers from the emitter to the
collector. Thus, I c increases to some extent with increase in VC* and the
slope of the common emitter characteristics is much more pronounced than
that of the common base characteristics. Also, note that I c now reduces to
zero when ^CE becomes zero. This is because the voltage plotted on the
79
Common
Emitter
Characteristics
4 - 6.3
Output
Characteristics
Figure 4-14. Common emitter output characteristics (or collector characteristics).
80
The
junction
Transistor
4-6.4
Current Gain
Characteristics
Example 4-5
horizontal axis is Vce> which equals the sum of ^CB and At the “knee”
of the characteristic, the collector-base junction bias ( V CB ) has been reduced
to zero. Further reduction in ^CE causes the collector-base junction to be
forward biased. The forward bias repels the minority charge carriers which
constitute ^C’ and so I c is reduced to zero.
As shown by the broken lines in Fig. 4-14, if the CE voltage exceeds a
maximum safe level, I c increases very rapidly and may destroy the device.
As in the case of common base configuration, this effect is due to punch
through.
These characteristics are simply I c plotted versus I B for various fixed
values of V CE . Like the common base current gain characteristics, they can
be obtained experimentally or determined from the output characteristics.
To experimentally obtain the required table of values, ^CE is held at a
selected level, and the base current (I B ) is adjusted in convenient steps. At
each step of 7 fi , the value of I c is observed and recorded. Figure 4-15 shows
the derivation of the current gain characteristics from the common emitter
output characteristics.The procedure is exactly the same as for the common
base current gain characteristics, with the exception that I c is plotted against
I B instead of I E .
Determine the value of I B and I c for a device with the characteristics
shown in Figs. 4-13 to 4-15 when V BE is 0.7 V and ^CE — 6 V. Also calculate
the transistor /? value.
Current gain Output
Figure 4-15. Derivation of common emitter current gain characteristics.
solution
From the input characteristics (Fig. 4-13), when V BE = 0J V and F C£ . = 6 V,
I B «s60 jmA. From the output characteristics (Fig. 4-14), when V ce -6V and
I g = 60 /iA, I c z&3.3 mA. From the current gain characteristics (Fig. 4-15),
when Vce~ ^ V and I B = 60 pA, 7 C » 3.3 mA. The current gain value at this
point is
3.3 mA
60 juA
= 55
81
Common
Collector
Characteristics
In the circuit arrangement of Fig. 4-16 the collector terminal is
common to both input CB voltage and output CE voltage. Using this circuit,
the common collector input, output, and current gain characteristics can be
determined. The output and current gain characteristics are show'n in Fig.
4-17. The common collector output characteristics are I E plotted versus V CE
for several fixed values of I B . The common collector current gain characteris-
tics are I E plotted versus I B for several fixed values of V CE'
Figure 4-16. Circuit for determining common collector characteristics.
4-7
Common
Collector
Characteristics
Figure 4-17. Common collector output and current gam characteristics.
82
The
Junction
Transistor
It will be recalled that the common emitter output characteristics are
I c plotted against V C E, and that the common emitter current gain character-
istics are I c plotted against I B . Since I c is approximately equal to the
common collector output and current gain characteristics are practically
identical to those of the common emitter circuit.
The common collector input characteristics illustrated in Fig. 4-18 are
quite different from either common base or common emitter input char-
acteristics. The difference is due to the fact that the input voltage V CB is
largely determined by the level of CE voltage (Fig. 4-16). This is because
when the transistor is biased on V BE will remain around 0.7 V for a silicon
transistor (0.3 V for germanium), and V CE may be much larger than 0.7 V.
From Fig. 4-16,
Vce=Vcb+Vbe
or
V B e= V ce - V cb
Consider the characteristic for Vce~ 2 V (Fig. 4-18). At I c = 100 fiA (point
1), V CB sv\.3 v and
V BE = ^CE ^CB
= 2 V— 1.3 V =0.7 V
Now suppose Vce is maintained constant at 2 V while the input voltage
(Vcb) is increased to 1.5 V (point 2). The base-emitter voltage becomes
V be = 2 V — 1.5 V=0.5 V
Because Vbe is reduced, I B is reduced from 100 jiA to zero.
Similarly, when V CE is maintained constant at 4 V and Vcb is
increased from 3.3 to 3.5 V, I B is reduced from 100 jiA to zero.
Figure 4-18. Common collector input characteristics.
A transistor consists of two /^-junctions with a common center block.
Therefore, to represent a transistor equivalent circuit, it should be possible to
use two /^-junction equivalent circuits. This has been done in Fig. 4-19, with
the exception that r ( now represents the CB junction resistance, r t represents
the BE junction resistance, and r b represents the resistance of the base region
which is common to both junctions. Junction capacitances Cbe and C BC are
also included.
If the transistor equivalent circuit were simply left as a combination of
resistances and capacitances, it could not account for the fact that most
charge carriers from the emitter flow out of the collector terminal. To
accommodate this phenomenon, a current generator is included in parallel
with r ( and Cbc- The current generator is given the value af> where
Since an input voltage would be applied between B and E , and the
output taken across C and B, the circuit of Fig. 4-19 is a common base
equivalent circuit. The equivalent circuit could easily be rearranged in
common emitter or common collector configuration. Note that the currents are
designated I b , I ( , and l e instead of I B , 7 C , and I E . This indicates that the quantities
involved are ac quantities rather than dc; i.e., we are considering current variations
rather than steady-state quantities. In the T-equivalent circuit the parameters r , r b , r ,
and a are also ac parameters.
Referring to Fig. 4-19, r e represents the ac resistance of the forward-bi-
ased BE junction. Therefore, r t is fairly small. On the other hand, r {
represents the resistance of the CB junction, which is normally reverse biased
for transistor operation. Therefore, r t has a high value. The resistance of the
base region represented by r b depends upon the doping density of the base
material. Usually, r h is larger than r,, but very much smaller than r ( .
4-8
Transistor
T-Equivalent
Circuit and
r -Parameters
E o-
I*
'e
Figure 4-19. T-equivalent circuit of transistor (common base).
83
84
The
Junction
Transistor
r b
o-
'- u e
e
-WW
-o
■o
O i o
Figure 4-20. Transistor low-frequency ac equivalent circuits.
Typical values for the resistive components are
r t = 25 12
r 6 = 1 00 to 30012
r. = 1 M12
The BE junction capacitance ( C BE ) is the capacitance of a forward-bi-
ased /^-junction, and the CB capacitance ( C CB ) is that of a reverse-biased
junction. At medium and low frequencies the junction capacitances may be
neglected. Also, instead of having the current generator ( al e ) in parallel with
r c , a voltage generator may be employed in series with r c . The voltage of this
generator is al e r c . Two circuits, either of which may be employed at medium
and low frequencies, are now available (Fig. 4-20). They are each referred to
as the T- equivalent circuit , or the r- parameter circuit.
4-9 In Section 4-8 it was shown that transistor circuits can be represented
h- Parameters by an r-parameter equivalent circuit (or T-equivalent circuit). In circuits
involving more than a single transistor, analysis by r-parameters can become
extremely difficult. A more convenient set of parameters for circuit analysis
is the hybrid parameters or h- parameters. These are used only for ac circuit
analysis, although dc current gain factors are also expressed as A-parameters.
In Fig. 4-21 a common emitter /i-parameter equivalent circuit is
compared with a common emitter r-parameter equivalent circuit. In each
case a load resistance R L is included, as well as a signal source V t and R r
The input to the /t-parameter circuit is represented as an input
resistance h it in series with a voltage h re X V u . Looking at the r-parameter
circuit, it is seen that a change in output current I c causes a voltage variation
across r f , i.e., a voltage /<«/ back to the input. In the /i-parameter circuit this
feedback voltage is represented as a portion ( h rt ) of the output voltage V (t .
The output of the A-parameter circuit is represented as an output
resistance 1 / h M in parallel with a current generator h ft X I b , where l b is the
base current variation, or ac base current. Therefore, hj t l b is produced by the
input current I b , and it divides between the device output resistance and the
load R l . I c is shown as the current passed to R L . Again, looking at the
r-parameter equivalent circuit, it is seen that all the generator current (a/,)
does not flow out through the load resistor; part of it flows through r t .
The /t-parameter equivalent circuit separates the input and output
parts of the circuit, and consequently simplifies circuit analysis.
Common emitter r-parameter
equivalent circuit
Common emitter h parameter
equivalent circuit
85
h -Parameters
Figure 4-21. Comparison of r-parameter and ^-parameter equivalent circuits.
Definition of the Common Emitter A -Parameters.
86
The
Junction
Transistor
A V Bl
h- = input resistance = . —
“ P A/»
= ratio of
(using ac quantities)
variation in (input) base emitter voltage
variation in (input) base current
h =
— reverse voltage transfer ratio = — — —
A V CE
variation in (input) base emitter voltage
variation in (output) collector to emitter voltage
A I c
h f . — forward current transfer ratio = — —
fe A/ fl
(when V C E is held
constant)
(when I B is held
constant)
L
h
V C E
variation in (output) collector current
variation in (input) base current
(when ^CE is held
constant).
The dc forward current transfer ratio ( jS^) is also written as h FE . Note
that to indicate that this is a dc parameter the subscript FE is used instead of
fe.
A I c
h oe — output conductance =
A V ri
(in siemens (S))
variation in (output) collector current
variation in (output) collector to emitter voltage
(when I B is held
constant)
The above parameters can be experimentally determined or can be
derived from the device characteristics.
For the common emitter output and current gain characteristics shown
in Fig. 4-22, determine the value of h M and hj e when I ( = 3.5 mA and
V CE = 4.5 V.
Example 4-6
Common emitter
current gain
Common emitter
output characteristic
Figure 4-22. Derivation of h M and h f , from characteristics.
solution
From the output characteristics ,
A Ic
A V ri
= h M — output conductance
From the current gam characteristics ,
Uc
= h f , = forward current transfer ratio
From point A on Fig. 4-22, at l c = 3.5 mA and V C e — 4.5 V,
A I c
AF'r;
0.35 mA
5 3.5 V
1X10“ 4 S
(/.-60 mA)
From point B on Fig. 4-22, at I c = 3.5 mA and F C£ — 4.5 V,
A I c
kf ~ A/p
(K Cf -4.5 V)
2.1 mA
' 35 /xA
= 60
From the common emitter input and reverse transfer characteristics,
determine the values of h lt and h rt for V CE — 4.5 V and / c = 3.5 mA.
87
h -Parameters
Example 4-7
88
The
Junction
Transistor
Figure 4-23. Derivation of h ie and h re from characteristics.
solution
When I c = 3.5 mA and F C£ = 4.5 V, 4 = 60 pA (Fig. 4-22).
From point C on Fig. 4-23,
K
kV B E 0.2 V
A4 ( v CE - 4.5 V) GO ^
3.3 kfl
From point D on Fig. 4-23,
Ke
A Vjn
(/ a = 60/iA)
0.03 V
~ 6 V
= 5 X 10 -3
(Note that the common emitter reverse transfer characteristic can be determined
from the family of input characteristics, Fig. 4-13, simply by drawing a horizontal line
for a given level of base current and reading V be for various levels of V C E-)
For common collector and common base configurations, the A -parame-
ters are defined in a similar way to the common emitter A -parameters, and
they may also be derived from the CE and CB characteristics. For common
collector, the suffix c replaces the e used in common emitter, and for
common base the suffix b is employed. The common collector and common
base A-parameter circuits are shown in Figs. 4-24 and 4-25, respectively.
Figure 4-24. Common collector b-parameter circuit.
Figure 4-25. Common base h - parameter circuit.
89
Glossary of
Important
Terms
Emitter. The portion of a transistor which emits charge carriers into the Glossary of
central base region. Important
Base. The central portion of a transistor, situated between the emitter and
the collector.
Collector. The portion of a transistor which collects the charge carriers
from the base region.
Collector- base junction, ^-junction between collector and base.
Emitter-base junction, ^-junction between emitter and base.
emitter current. Current entering or leaving the emitter terminal.
I B , base current. Current entering or leaving the base terminal.
/ c , collector current. Current entering or leaving the collector terminal.
I C bo> collector base leakage current. Minority charge carrier current that
flows across a reverse-biased collector-base junction.
Bipolar transistor, fmp or npn transistor.
a dc’ alpha dc. The fraction of the emitter current that is collected at the
collector-base junction, typically 0.98.
0^, beta dc. Current gain factor: / c //r.
a, alpha. Ratio of I c change to I E change. The ac equivalent of a d( .
/3, beta. Ratio of I c change to I B change. The ac equivalent of
npn transistor. Transistor made of a sandwich of a central p region and
two outer n regions.
90
The
Junction
Transistor
pnp transistor. Transistor made of a sandwich of a central n region and
two outer p regions.
^cb- Voltage applied across collector and base terminals.
Vbe* Voltage across base and emitter terminals.
r e . Portion of transistor T-equi valent circuit connected to the emitter
terminal, typically r e = 25 A.
r b . Portion of transistor equivalent circuit connected to the base terminal,
typically 100 to 300 ft.
r c . Portion of transistor equivalent circuit connected to collector terminal,
typically 1 MS2.
Common base. Transistor connection in which base terminal is common to
both input and output voltages.
Common emitter. Transistor connection in which emitter terminal is com-
mon to both input and output voltages.
Common collector. Transistor connection in which collector terminal is
common to both input and output voltages.
Punch through. Condition that occurs when collector-base depletion re-
gion spreads throughout the base and causes transistor breakdown.
Reach through. Same as punch through.
r-parameter equivalent circuit. Circuit redrawn with transistor replaced
with its equivalent parameters.
T-equivalent circuit. Same as r-parameter equivalent circuit.
A-parameters. Parameters employed in a transistor ac equivalent circuit
which isolate input and output terminals from each other.
Hybrid parameters. Same as h-parameters.
h ie . Common emitter input resistance for A-parameter equivalent circuit.
h re . Common emitter reverse transfer ratio for A-parameter equivalent
circuit.
h FE . Common emitter dc forward current transfer ratio. Same as
A Be . Common emitter output conductance for A-parameter equivalent
circuit.
/y € . Common emitter ac forward current transfer ratio for A-parameter
equivalent circuit.
Review
Questions
4-1. Draw sketches to show unbiased pnp and npn junction transistors in
block form. Show the depletion region widths and barrier potentials.
Briefly explain.
4-2. Repeat Question 4-1 for a correctly biased pnp transistor. Label each
block according to its function, and show the direction of movement
of charge carriers and the type of carriers involved. Briefly explain
the transistor operation.
4-3. Repeat Question 4-2 for a correctly biased npn transistor.
4-4. Draw a sketch to show the various current components in a transistor,
and briefly explain the origin of each. Derive an expression for the
collector current I c in terms of base currents I B and reverse saturation
current I cbo . Define a dc and ft dc and state typical values for each.
4-5. Sketch the circuit symbols for pnp and npn transistors. Label each
type, show the polarity of bias and supply voltages, and state typical
voltage values.
4-6. Sketch and explain the shape of common base input and output
characteristics. Also, explain how the characteristics are determined
experimentally.
4-7. Sketch and explain the shape of the common base current gain
characteristics. Explain how the characteristics may be determined
experimentally.
4-8. Sketch and explain the shape of the common emitter input and
output characteristics. Explain how the characteristics are de-
termined experimentally.
4-9. Sketch and explain the shape of the common emitter current gain
characteristics. Explain how the characteristics may be determined
experimentally.
4-10. Sketch the common collector input, output, and current gain char-
acteristics, and explain their shape.
4-11. Sketch the T-equivalent circuit for a transistor. Name each compo-
nent and discuss its origin. Also, show the simple form of equivalent
circuit for low-frequency calculations.
4-12. Sketch the /^-parameter equivalent circuit for the common emitter
configuration. Correctly label all resistors, currents, and voltages.
4-13. Repeat Question 4-12 for the common collector configuration.
4-14. Repeat Question 4-12 for the common base configuration.
4-15. Define h lt , and h Tt .
4-1. Calculate the values of I c and I E for a transistor with a^ = 0.97 and
I C bo~ 10 pA , I B is measured as 50 fiA.
4-2. For a certain transistor I c — 5.255 mA, I B = 100 piA, and Iqbo = ^ /*A:
(a) Calculate a^, /?*, and I E .
(b) Determine the new level of I B required to make / c = 15 mA.
4-3. Calculate the collector and emitter current levels for a transistor with
a^ = 0.99 and I C bo~ 1 /*A, when the base current is 20 fj.A.
4-4. The following current measurements were made on a particular
transistor in a circuit:
I c = 12.427 mA, I B = 200 /rA, I CBO = l pA
91
Problems
Problems
(a) Determine I E , and a d( .
4-5.
92
The
Junction
Transistor
4-6.
4-7.
4-8.
4-9.
4-10.
(b) Determine the new level of I c which will result from reducing I B
to 150 juA.
Determine the values of I B and l c for a device with the characteristics
shown in Figs. 4-13 to 4-15 when V BE is 0.6 V and V CE = 6 V.
From the common base output characteristics in Fig. 4-10, derive the
current gain characteristics for Vcb — ^ V.
A transistor has the characteristics shown in Figs. 4-9 to 4-11.
Determine I E and I c when V BE = 0.8 V and V CB = 6 V.
Using the common emitter output characteristics shown in Fig. 4-14,
derive the current gain characteristic for r«-s V. Also determine
the value of h fe when / c «s2 mA and V.
From the common emitter current gain and output characteristics in
Fig. 4-15, determine and hj e when V CE ^ — 2 V and / c « 3 mA.
From the common emitter input characteristics in Fig. 4-13, de-
termine h u when I B = 100 fiA and V ce~& V.
Transistor
Biasing
A dc load line, similar to those for diodes and other electronic devices,
may be drawn on the transistor characteristics in order to study the currents
and voltages in a particular circuit. The dc bias point , or quiescent point , is the
point on the load line which represents the currents in a transistor and the
voltages across it when no signal is applied; i.e., it represents the dc bias
conditions. The stability of the bias point may be affected by variations in
parameters from one transistor to another or by temperature variations.
The value of h FF (or /? dc ) for a given type of transistor has a wide
tolerance. A typical h FE specification is
minimum value
25
typical
50
maximum value
75
As will be seen, the typically wide tolerance of h FE can affect the bias
conditions, and thus determine the type of bias circuit that must be used.
Temperature variations can also affect bias point stability.
CHAPTER
5
5-1
Introduction
93
5-2
The dc Load
Line and
Bias Point
To study the effects of bias conditions on the performance of the
common emitter circuit, it is necessary to draw a dc load line on the
transistor output characteristics. Consider the circuit and characteristics
shown in Fig. 5-1.
If the circuit was to be used as an amplifier, the input terminals would
be base and emitter. The output would be taken from collector and emitter.
The emitter terminal is common to both input and output, so the configura-
tion is identified as a common emitter circuit.
Note that the polarity of the transistor terminal voltage in Fig. 5- 1(a)
is such that the base-emitter junction is forward biased, and the collector-
base junction is reverse biased. These are the normal bias polarities for the
device.
From Fig. 5- 1(a), the collector emitter voltage is
Therefore,
Vce = (supply volts)-(volt drop across R L ).
^ce ~ Vcc ~
(5-1)
94
(b) Common emitter characteristics and load line
Figure 5-1. Plotting the dc load line.
If the base bias voltage V B is such that the transistor is not conducting,
then l c — 0 and Vce=Vcc-(OxR l )=V cc = 20 V. Therefore, when 7 C = 0,
VCE = 20 V. This point is plotted on the output characteristics as point A.
Suppose that V B is increased until / c = 0.5 mA; then V CE — 20 V —
(0.5 mAXlO kft) = 20 V-5 V=15 V, and thus when / c = 0.5 mA, V CE =
15 V. This point (point B) is now plotted on the output characteristics.
Continuing the above process, several sets of corresponding values of I c and
V C E are obtained and plotted on the common emitter output characteristics:
I c = 1 mA, V CE = 10 V, point C
I c = 1.5 mA, Vce~^ V, point D
l c = 2 mA, V CE = 0 V, point E
The line drawn through these points is straight and is the dc load line for
R l = 10 kft. Since the load line is straight, it could be produced by plotting
only two points and drawing a line through them. The most convenient two
points in this case are point A and point E.
At point /l, / c = 0 and V CE = V cc = 20 V
V cc
At point E, V CE = 0 and l c — — = 2 mA
r l
The dc load line is a plot of I c against VCE for a given value of R L and
a given level of Vcc- Thus, it represents all collector current levels and
corresponding collector-emitter voltages that can exist in the circuit. For
example, a point plotted from 7 C = 1.5 mA and ^CE = 16 V would not appear
on the dc load line in Fig. 5-1. Therefore, the load line shows that this
combination of voltage and current levels could not exist in this particular
circuit. Knowing any one of I Ci I B , or V CE> it is easy to determine the other
two from the load line.
The load line in Fig. 5-1 applies only for the case of V cc = 20 V and
R l = 10 kft. If either of these conditions is changed, a new dc load line must
be drawn.
Draw the dc load line for the circuit and characteristics of Fig. 5-1
when R l is changed to 9 k 12.
solution
When 7 C = zero, V CE = F cc = 20 V.
Therefore, plot point A at / c = zero and V CE = 20 V.
When V CE = 0 V, I c = V cc / R L = 20 V/9 k« = 2.2 mA.
Therefore, plot point F at Vce~ 0 and 7 C =2.2 mA. Now join points A
and F together to draw the load line for R L S =9 kft.
95
The dc Load Line
and
Bias Point
Example 5-1
96
Transistor
Biasing
Figure 5*2- Bias point selection.
In designing a circuit, a point on the load line is selected as the dc bias
point, or quiescent point. This bias point specifies the I c and V C E that exist
when no input signal is applied. When an input signal is applied, I B varies
according to the signal amplitude and causes I c to vary, consequently
producing an output voltage variation.
Consider the 10-k£2 dc load line shown in Fig. 5-2, for the circuit of
Fig. 5- 1(a). Suppose the dc bias conditions are set up as at point Q.
At point Q: I B = 20 /aA, I c = 1 mA, and V CE = 10 V.
When I B is increased from 20 /a A to 40 /a A, I c becomes 1.95 mA and
V CE = V cc — (I c X R l ) = 20 V — ( 1 .95 mA X 10 k$2) = 0.5 V.
Therefore, increasing I B by 20 /aA (from 20 /aA to 40 /aA) caused V C E
to decrease by 9.5 V (from 1 0 V to 0.5 V), or a A I B =4-20 /aA caused a
A V CE = —9.5 V.
When l B is decreased from 20 f±A to 0 fiA, l c becomes 0.05 mA and
V CE = Vcc~( i c xR l) = 2Q V — (0.05 mAXlO kfi)=19.5 V, or a A/, = -20
p A caused a A V c = 4- 9.5 V.
Thus, if the circuit is biased to point Q, where I c — 1 mA and V CE = 10
V, an ac input could be provided to produce an output voltage swing (A ^ce)
of ±9.5 V.
Suppose, instead of being biased to point Q, the circuit is biased to point Q\ At
point Qf,
7 C = 0.525 mA and V CE = 14.75 V
AI b = ± 10 pA, A7 C = ±0.475 mA, AV CF = ±4.75 V
The maximum equal positive and negative variations in V CE are now
±4.75 V. This is also referred to as the maximum undistorted output , because
any larger output amplitude would be a distorted waveform; i.e., the
negative output change would be larger than the positive output change.
At all bias points above or below point (£, it is seen that the maximum
equal positive and negative variation in VCE will be less than ±9.5 V.
Therefore, for maximum undistorted output voltage variations, the bias
point must be selected at the center of the load line. In some cases,
maximum possible output voltage variation will not be required, and then
the bias point can be at any other suitable point on the load line.
A transistor with the output characteristics shown in Fig. 5-3 is
connected as a common emitter amplifier. If R L = 2.2 kS2, V cc = 18 V, and
I B = 40 pA, determine the device bias conditions and estimate the maximum
undistorted output.
solution
The circuit is the same as that shown in Fig. 5- 1(a), but with R, — 2.2 k£2
and V cc = 1 8 V.
UseEq. (5-1): V CE = V cc - I C R L .
When 7 C = 0,
Vce ~ ^cc = 1 8 V
Plot point A on Fig. 5-3 at 7 C = 0, V CE = 18 V.
When V CE = 0 ,
18 V
= V C fJ R-i. — 2 2 kfi
Plot point B on Fig. 5-3 at 7 C = 8.2 mA, V CE = 0 V.
•Draw the dc load line from points A to B. Where the load line
intersects the I B = 40 pA characteristic at point Q, read the bias conditions as
7 C = 4.25 mA and ^ = 8.7 V.
When I B is increased to 80 pA (point Q.i)> ^ CE is decreased from 8.7 to
1.2 V; i.e., AF C£ = 7.5 V. When I B is reduced to zero pA (point (£ 2 ), V CE
increases from 8.7 to 16.7 V, and AV CE = S V.
The maximum undistorted output is ± 7.5 V.
97
The dc Load Line
and
Bias Point
Example 5-2
98
Transistor
Biasing
5-3
Fixed
Current
Bias
The bias arrangement shown in Fig. 5-4 [and in Fig. 5- 1(a)] is known
as fixed current bias. The base current I B is fixed by the bias voltage Vcc and
the resistor R B .
From Fig. 5-4,
(5-2)
Note that because V CE > Vbe, and R b are constant quantities, I B remains fixed
at a particular level. In this circuit I B is not affected by the transistor h FE
value.
Figure 5-4. Fixed current bias.
Design of bias circuits must begin with a specification of the supply
voltage and the required l c and V CE . Alternatively, R L and V C£ may be
specified and I c calculated. The procedure is best understood by considering
a design example.
99
Ftxed
Current
Bias
Design a fixed current bias circuit using a silicon transistor having an Example 5-3
h FE value of 50 typical, 25 minimum, and 75 maximum. V cc is 10 V, and
the dc bias conditions are to be Vce~^ V and I c = 1 mA. Calculate the
maximum and minimum levels of I c and VCE-
solution
First design the circuit, using the typical value of h FE = 50.
value of R l
From Eq. (5-1)
^ce~ Vcc Ic^l
and
10 V-5 V
1 mA
-5 kfi
value of R b
I c _ (1X10~ 3 )
h FE 50
= 20 fiA
From Eq. (5-2),
and
10 V-0.7 V
20 nA
= 465 kS2
If h FE has a typical value of 50, then the bias conditions should be ^-5V
and I c ~ 1 mA as desired. Now calculate the bias conditions when h FE is 25
and 75.
100
Transistor
Biasing
5-4
Collector-
to- Base
Bias
When h FE — 25, I B remains equal to ( V cc — V BE )/ R B = 20 juA
and Ic—hFE 1 !} = 25 X 20 jiA
= 0.5 mA
V CE = V cc ~ I c R l = 1 0 V - (0.5 mAX5kfl)
= 7.5 V
When h FE = 75, I B remains equal to ( V cc — V BE )/ R B = 20 fi A
and ^c—hpE^B = 75 X 20 fi A
= 1.5 mA
V CE = V cc ~ = 1 0 v — ( 1 .5 mA X 5 kfi)
= 2.5 V
From Example 5-3 it is seen that, although the circuit was designed for
l c = 1 mA and V CE = 5 V, the actual bias conditions may be anywhere
between / c = 0.5 to 1.5 mA and ^CE — 2-5 to 7.5 V. This wide range results
from the spread in possible values of h FE . The fixed current bias technique is
not a very satisfactory method of obtaining good bias point stability.
In Example 5-3, R L and R B as calculated are not standard resistance
values. In practice the nearest standard values should be selected, and this
affects the actual I c and Vqe levels obtained. The following examples
continue to use nonstandard resistance values as calculated. This is to permit
comparison of the performance of the three basic bias circuits.
In the collector-to-base bias circuit (Fig. 5-5)) the base resistor R B is
connected to the collector of the transistor. This makes the circuit design a
little more complicated, but improves the dc bias conditions. To understand
how the bias stability is improved, observe that the voltage across R B is
Figure 5-5. Collector-to-base bias.
dependent upon K:e- If I c becomes larger than the design value, it causes an
increased voltage drop across R L . This results in a smaller level of which
in turn causes I B to be smaller than its design level. But since I c —^fe^B' Ic
will also tend to be reduced.
From Fig. 5-5,
101
Collector-
to-Base
Bias
Vcc ~ R l {I b + I c ) + Vce
(5-3)
and
^ce~ Ib^b + ^BE
(5-4)
Design a collector-to-base bias circuit for the conditions specified in
Example 5-3, and calculate the maximum and minimum levels of I c and
^ce-
solution
First design the circuit, using A a£ = 50.
From Eq. (4-7),
A
^FE
1 mA
50
= 20 pA
Example 5-4
Rearranging Eq. (5-4),
R» =
5 V — 0.7 V
20 pA
= 215 kfi
From Eq. (5-3),
Vcc Vqe
Ib + Ic
10 V-5 V
20 /xA -h 1 mA
= 4.9 kfi
The circuit has been designed to give V CE — 5 V and / c = 1 mA when
h FE = b0. Now determine the bias conditions when h FE is 25 and when h FE is
75. In this circuit I B does not remain constant when h FE changes.
From Eqs. (5-3) and (5-4),
kcc ~ Rl (I b^ Ic) 4 " I bRb 4 * ^be
102
Transistor
Biasing
Then, since I b —I c /^fe^
Vcc-Rl( T- +I c)+-r-R B +y I
\ n FE } h FE
=/c h(i +1 ) + 5
When h FE = 25,
10 v = / c [ 4 .9 ka(^ + 1) + ] +0.7 V
giving
/ c = 0.68 mA
Substituting I B = I c / h FE into Eq. (5-4),
v C E=-jrR B +v BE
= | °.68mA x215 kB j + 0 7 v = 655 V
For h FE = 75 y
10 V = / C j^4.9 +
215 kfi
75
+ 0.7 V
and
E = ( 11 75 mA X2l5ksj + 0.7 V=4.1 V
For the collector-to-base bias circuit in Example 5-4, / c = 0.68 to 1.19 mA
and Fce = 4' 1 to 6.55 V. This is an improvement over the fixed current bias
circuit.
5-5
Emitter
Current
Bias
(or Self-Bias)
An emitter current bias circuit is shown in Fig. 5-6. Resistors /?, and R 2
divide the supply voltage Vac to provide a fixed bias voltage ( V B ) at the
transistor base. Also, a resistor R E is included in series with the emitter
terminal of the transistor. The voltage drop across Fe * s F e — I E X R e , and
103
Emitter
Current
Bias
(or Self- Bias)
V e =Vb-V be .
V — V
Therefore, 1 E = - B — BE (5-5)
r e
if V be , I e z& V b /R e and is very stable no matter what the value of h FE .
Since I c ^I Ey the collector current is also a stable quantity in this circum-
stance.
The discussion above assumes that V B is an extremely constant level of
bias voltage. This requires that /?, || /? 2 be not very much larger than R E . If
R\ || R 2 is very much larger than R E , then the circuit performance becomes
similar to the fixed current bias circuit.
To obtain a very stable bias voltage, R l and R 2 should be selected as
small as possible, so that variations in I B have little effect on the level of V B .
However, since the ac input is coupled via C, to the transistor base (see Fig.
5-6), R x and R 2 should be made as large as possible to maintain a high input
resistance. A rule-of-thumb approach is to make I 2 (flowing through R x and
R 2 ) approximately equal to the collector current I c . When thermal stability is
considered, it will be seen that this rule-of-thumb can be very effective.
Using an approximation, this kind of bias circuit can be very' easily
analyzed to determine l c and ^CE' The approximation is normally quite
reasonable. Base current I B is assumed to be very much smaller than the
current / 2 through resistor R 2 . This allows V B to be calculated from the
supply voltage Vcc and potential divider R { and R 2 .
and
^cc x
*2
R i +R 2
(5-6)
(5-7)
f C~ / £
104
Transistor
Biasing
Figure 5-7. Emitter current bias showing bias voltage and source resistance.
Therefore,
Vcb-Vcc-Ib(Rl + Rb) (5-8)
To rigorously assess the performance of the emitter current biased circuit, it
should be redrawn as in Fig 5-7. The bias resistances are replaced with their
Thevenin equivalent circuit, in which V B = V cc XR 2 /(R x + 7? 2 ) and R B =
*lll*2-
From Fig. 5-7,
^cc — 4^4 ^ CE Re( 1 B **■ 4)
(5-9)
= 44s **“ ^BE ReVb 4)
(5-10)
Example 5-5
Using the circuit conditions specified for the last two examples, design
an emitter current bias circuit, and investigate the effects of h FE spread.
solution
As before, first design the circuit using the specified typical value of h FE = 50.
In this case it will be necessary to use V cc ~ 15 V, so that I c R L = b V,
V ce = 5 V, and V E = 5 V.
/A = 5V
l
L 1 mA
= 5 kft
or
and
Since Ig — Ic/ ^ fe »
— (4; + Ib)Re
105
Emitter
Current
Bias
(or Self-Bias)
Substituting values,
Let
then
and
5 V = ( 1mA +
1 mA
50
h
Iq 1 inA
, _ Vb .. >g+ K BE . 5V + 0.7V
2 I 2 / 2 1 rnA
= 5.7 kfl
^ B ~
*,=
I c _ 1 mA
Vcc-Vb
I 2 + I B
= 20 nA
15 V-5.7 V
1 mA + 20 /xA
= 9.1 kfi
Now calculate the bias conditions for h FE = 25 and 75:
and
V
^cc><
*L
r x + r 2
= 15 VX
5.7 kS2
9.1 kfl + 5.7 kfl
«5.8V
Rg~ R\ || R 2 = 5.7 k!2||9.1 kfi
= 3.5 k«
From Eq. (5-10),
V' t -I B R B +V BE + RA1 B + I c )
106
Transistor
Biasing
substitute
Jc_
hpE
Thus
Jc_
h FE
V'b = ~T~ R r + V n/r +
« j
which gives
— V dp — If
■+R>
n FE \ n FE
4 M
(i +l )
J _ £ DC*
{Rr/ ^Fe) + Re( 1 / kpE + 0
for h FE — 25,
r = 5.8V-0.7V
c (3.5 kfl/25) + 4.9 k£2(l/25 + 1)
= 0.97 mA
for h FE — 75,
r = 5.8 V-0.7 V
c (3.5 kfi/75) + 4.9 kfl( 1 /75 + 1 )
= 1 .02 mA
From Eq. (5-9),
Vce~ ^cc
For h FE = 25,
= 1 5 v “ (°- 97 mA X 5 kfl) - 4.9 kfl( °' 97 ^ lA + 0.97 mA j
= 5.2 V
For h FE = 75,
V CE =\5 V-(1.02 mAX5 kfl) — 4.9 kfl( LQ ^f I } A + 1.02 mA)
= 4.9 V
For the emitter current bias circuit in Example 5-5, I c is 0.97 to 1.02
mA, and V CE is 4.9 to 5.2 V.
Examples 5-3 to 5-5 show the three types of basic bias circuits. Each
circuit employs a transistor with a typical v* value of 50 and maximum and
minimum values of 75 and 25, respectively. Each circuit was designed for
Vqe = 5 V and 7 C = 1 mA. The maximum and minimum levels of I c and V CE
were calculated as:
For fixed current bias,
7 C = 0.5 to 1.5 mA and V CE — 2.5 to 7.5 V
For fixed collector to base bias,
7 C = 0.68 to 1.19 mA and V CE = 4. 1 to 6.55 V
For emitter current bias,
7 C = 0.97 to 1.02 mA and V CE = 4.9 to 5.2 V
Clearly, the emitter current bias circuit is the most stable of the three.
Transistors can be seriously affected by temperature. Two of the most
temperature-sensitive quantities are the base-emitter voltage ^be and the
collector- base reverse saturation current I cbo . The temperature coefficient
of is approximately —2.2 mV/°C for a silicon transistor,
and — 1.8 mV/°C for a germanium device. I CB0 approximately doubles for
each 10°C temperature increase.
An increase in I CB0 will cause I c to increase, and an I c increase will
raise the temperature of the collector-base junction. The junction tempera-
ture increase will generate more minority carriers, and so increase f CB0 still
further. The effect is cumulative, so that a considerable increase in 7 C may
be produced. This could result in a significant shift in the dc operating
point, or, in the worst case, 7 C may keep on increasing until the collector-
base junction is burned out. This effect is known as thermal runaway.
Measures taken to avoid it are similar to those required for good bias
stability with spread in h FE values.
Changes in V BE may also produce significant changes in 7 C and
consequently in the dc operating point. However, because of the possibility
of thermal runaway, the I CB0 changes are by far the most important. The
thermal stability of a circuit is assessed by deriving a stability factor S.
S =
yic_
^IcBO
(5-H)
The minimum value that S can have is one; i.e., if I CBO increases by 1 /xA, 7 C
will increase by at least 1 /xA. For S' = 50, A7 C = 50X A7 Cfio . A stability factor
of 50 is considered poor, while S= 10 is good.
5-6
Comparison
of Basic
Bias circuits
5-7
Thermal
Stability
107
5-7.1 To find S for a given circuit, an expression for I c is derived and then
Evaluation altered to study the effect of changes in the various currents. From Eq. (4-6),
$ a general expression relation I B , I CBO > and I c is
Ic ~ h feIb ( 1 + h fe)Icbo
When I CB0 changes by A I CB o> Ib changes by A I B and I c changes by
A/ c , so the equation becomes:
or
A I c — ^fe^Ib 4 " ( 1 4 * I 1 fe)^Icbo
A Id A Icro
1 hFE JT c ~ < ' i + hFE) ~U^
klcBO _ 1 ~ ^Fe(^Ib/^Ic)
A In
1 4* kp .
Ajc 1 h FE
A IcBO 1 — ^Fe(^Ib/^Ic)
(5-12)
Equation (5-12) is a general expression for S. To evaluate S , an
expression for A I B / A I c must be derived for each particular circuit.
5-7.2
5 for Fixed
Current Bias
From Eq. (5-2),
/« =
When I B changes by A I B , ^cc and Vbe are unaffected, and since I c is not
involved in the equation,
Substituting into Eq. (5-12),
For fixed current bias,
1 4 - h FE
1-0
= 14 * h FR
(5-13)
In the bias design examples, h FE ranged from 25 to 75. This gives a
value of S from 26 to 76. Thus, the fixed current bias circuit has poor
thermal stability as well as poor stability against h FE spread.
108
From Eqs. (5-3) and (5-4),
^cc RlUc ^b) "*■ Rb^b
= 'c*£ ■*■ *b(Rl “*■ "*■ ^BE
5-7.3
5 for
Collector-
to-Base Bias
When I CBO changes by A/ Cfio , l B changes by A/ fl and l c changes by A/ c ,
there is no effect upon Vcc and ^fl£* and the equation becomes
0 = A/ c /? i + A/*(/? L + /? fl )
or - M c R l = bI B (R L + /?*)
*V.
A/ C +
Substituting this expression into Eq. (5-12),
For collector to base bias,
(5-14)
Using the h FE and resistance values from Example 5-4, S ranges from 17 to
28.
This is an improvement over the fixed current bias stability factor, but
in many cases it may be unacceptable. From the expression for S , it is seen
that, for a small value of S, R B must be as small as possible.
From Eq. (5-10),
V'b ~ ^cR E + /*(/?£ + Rb) Kb£
When I CB0 changes by A I CBO , I B changes by A I B and I c changes by A/ c ,
there is no change in V B and Kb£> and the equation becomes
0 — A IqRe "*■ A/jb( R b + R b )
or — &I c R e = AI b (R e + R b )
~Re
A/ c
Substituting into Eq. (5-12),
For emitter current bias
1 + h FE
Re
Re + r b
)
(5-15)
5-7.4
5 for
Emitter
Current Bias
109
110
Transistor
Biasing
5-8
AC Bypassing
and the
AC Load Line
5 - 8.1
AC Bypassing
5 - 8.2
The AC
Load Line
For I 2 ~ Iq* as * n Example 5-4, S^1.7, which is a very good stability factor.
Also, for R b = R e , S&2; for R B = 5R E , 5^6; and for R B <giR E , Sczl.
It is seen that the emitter current bias circuit can be the most stable of
all three circuits considered. This is the case for temperature variations, as
well as for effects of h FE spread.
In the discussion on the collector-to-base bias circuit, it was explained
that an increase in I B would produce a decrease in ^CE’ which tends to
cancel the original increase in I B . This, of course, is the effect that produces
good dc bias stability. However, the same conditions exist when an ac signal
is applied to the base for amplification. The voltage change at the collector
tends to cancel the ac input signal, and this can result in the circuit having a
very low ac gain, as well as affecting its input impedance. The effect is
termed ac degeneration , and it must be eliminated if reasonable ac voltage
amplification is to be achieved.
Figure 5-8(a) shows how ac degeneration is eliminated in the collector-
to-base bias circuit. Instead of using a single bias resistor, two approximately
equal resistors, R Bl and R B2 , are employed. The two must add up to the
required value of R B . A bypass capacitor (C B ) is connected from the junction of
R Bl and R B2 to the low-voltage supply terminal, as shown. C B behaves as a
short circuit to ac signals, and the ac equivalent of the circuit is then as
shown in Fig. 5-8(b). R Bl and R B2 are in parallel with the input and output,
respectively, and since they are large-value resistances they have virtually no
effect on the ac gain of the circuit. The dc bias stability is, of course,
unaffected by the presence of C B .
Emitter current biased circuits also suffer ac degeneration, and a
bypass capacitor C E must be employed, as shown in Fig. 5-9. From the
circuit analysis in Chapter 6 the expression for the voltage gain of a common
emitter circuit with a resistance in series with the emitter terminal is
A = ~ ^FE R L
h u + R E{ l+fl fi)
Thus, it is seen that the presence of R E can keep the amplifier gain uselessly
low. C E has the effect of ac short circuiting R E to achieve a reasonable
voltage gain.
The total dc load in series with the transistor in Fig. 5-9 is (R L + R E ).
Thus, the dc load line is drawn for the resistance (R L + R E ). With R E
bypassed by Ce> the ac load is R L , and a new ac load line must be drawn to
Figure 5-8. Elimination of ac degeneration in collector-to-base bias circuit.
Figure 5-9. Elimination of ac degeneration in emitter current biased circuit.
Ill
112
Transistor
Biasing
Example 5-6
describe the circuit ac performance. When no signal is applied, the transistor
voltage and current conditions are as indicated at the quiescent point (point
(?) on the dc load line (see Fig. 5-2). When an ac signal is applied, the
transistor voltage and current vary above and below point Q. Therefore, the
Q, point is common to both the ac and dc load lines. Starting from the ()
point, the ac load line is drawn by taking a convenient collector current
change (A/ c ), and calculating the corresponding collector emitter voltage
change (A V c = — kI c R L ). The current and voltage changes are then
measured from point Q to obtain another point on the ac load line. The ac
load line is then drawn through this point and point Q.
The common emitter circuit shown in Fig. 5-9 has V cc = 20 V, R L = 3.9
H2, R e = 1.2 k£2, R x = 12 kfi, and R 2 = 2.2 kfi. R E is bypassed to ac signals by
the large capacitor C E , and the transistor employed has the characteristics
shown in Fig. 5-10. Draw the dc and ac load lines for the circuit.
solution
Total dc load = R L + R E = 3.9 k£2 + 1 .2 kfi = 5. 1 k£2
and
When I c = 0,
Vce~ ^cc Ic(Rl + Re)
Vce~ t'cc
= 20 V
Figure 5-10. Plotting the ac load line.
Plot point A on Fig. 5-10 at 7 C = 0 and K C£ = 20 V. When V CE = 0,
Therefore,
0= v cc -i c (r l + r e )
^C~
Vcc
Rl + Re
20 V
5.1 kfl
= 3.92 mA
Plot point B on Fig. 5-10 at I c = 3.92 mA and F C£ = 0.
Draw the dc load line through points A and B.
The approximate bias conditions can be quickly determined by assum-
ing that the base current ( I B ) is too small to affect the base bias voltage ( V B ).
Thus,
and
^ccX
*2
/?J + /?2
20 VX2.2 kfi
12 kft + 2.2 kfi
I E R E = V b~ Vbe = 3.1 V-0.7 V = 2.4 V
2.4 V
1.2 kS2
= 2 mA
Mark the bias point (point ()) on the dc load line at 7 C = 2 mA (Fig.
5-10). The ac load is R L = 3.9 kfi.
Taking A/ c = 1 mA, AF C£ = -M C R L = -(1 mAX3.9 kft)=-3.9 V.
Therefore, when 7 C increases by 1 mA (from point ()), V CE decreases by 3.9
V. Plot A/ c and ^CE on Fig. 5-10 to obtain point C as another point on the
ac load line. Draw the ac load line through points () and C.
113
Glossary of
Important
Terms
DC load line. Load line plotted on transistor characteristics to represent all G lossary of
circuit conditions. Important
Terms
DC bias point. Voltage and current conditions that exist in a circuit when
no signal is applied. Point on dc load line.
Quiescent point (()). Same as dc bias point.
Fixed current bias. Method of biasing a transistor in which base current is
held constant.
Collector-to-base bias. Transistor bias circuit in which the base is con-
nected via a resistor to the collector.
Emitter current bias. Transistor bias circuit in which a resistor is con-
nected in the emitter circuit.
Self-bias. Same as emitter current bias.
114
Transistor
Biasing
Review
Questions
Problems
Thermal runaway. Transistor destruction by overheating, due to unstable
bias circuit.
Thermal stability factor (5). The ratio of variation in I c to variations in
^CBO'
AC degeneration. Loss of ac circuit gain, due to factors which produce
good dc bias stability.
5-1. Sketch a fixed-current bias circuit (a) using an npn transistor; (b)
using a pnp transistor. In each case show the supply voltage polarity
and current directions.
5-2. For a fixed-current bias circuit, derive an equation relating I c to the
supply voltage, circuit resistors, and transistor h FE value. Also derive
an equation for the transistor collector voltage V c .
5-3. Repeat Question 5-1 for collector-to-base bias.
5-4. Repeat Question 5-2 for collector-to-base bias.
5-5. Repeat Question 5-1 for emitter-current bias.
5-6. Repeat Question 5-2 for emitter-current bias (a) using an approxi-
mate method; (b) for a rigorous analysis.
5-7. Compare the three basic bias circuits with regard to the stability of
collector current I c against changes in h FE .
5-8. Discuss the thermal stability of a transistor circuit, and define the
stability factor S. Compare the three basic bias circuits with regard to
stability factor S.
5-9. Explain what is meant by ac degeneration , and show how it may be
eliminated in collector-to-base bias and emitter current bias circuits.
5-1. For the common emitter circuit and output characteristics shown in
Fig. 5-1, plot the dc load line for the following conditions:
(a) V cc = 15 V, R l = 7.5 kfi.
(b) V cc — 1 2 F,* L = 8k£2.
In each case, select the best dc bias point, and specify it in terms of I c
and V CE .
5-2. A circuit with the same configuration and transistor characteristics as
shown in Fig. 5-1 is to have the following dc bias conditions:
V cf = 9 V, 7 c = 2mA
If V cc is 18 V, plot the bias point on the characteristics, draw the
load line, and determine the required value of R L .
5-3. For a fixed-current bias circuit, 7? B = 200 kfl, R L = 2 kfl, and V cc =
10 V. Assuming V BE = 0J V, find the dc operating point when
h fe — 50. Also determine the changes in operating point when h FE has
a minimum value of 40 and a maximum value of 60.
5-4. A transistor having the output characteristics shown in Fig. 4-14 is
connected as a common emitter amplifier. If R L = 1.2 k£2, F’ cc =
7.5 V, and / s = 40 /*A, determine the device bias conditions, and
estimate the maximum peak-to-peak undistorted output voltage.
5-5. A fixed current bias circuit has /? L = 3.3 k!2 and V cc =15 V. The
transistor has a typical h FF = 60, with minimum and maximum values
of 30 and 90, respectively. Select a value of R g to give V CE — b V for
the typical h FE value. Also determine the upper and lower limits of
^ ce •
5-6. A collector-to-base bias circuit is to be designed to have a V CE of
12 V. R l = 2.2 kfi, T cc = 20 V, and the transistor h FE ranges from 40
minimum to 80 typical to 120 maximum. Determine the required
value of R b and calculate the upper and lower limits of VCE-
5-7. A collector-to-base circuit has R L = s 3.3 kfi, V cc = 1 5 V, and R B =
330 kJ2. The silicon transistor employed has an h FE ~ 60 typical, 20
minimum, and 100 maximum. Determine the typical, minimum, and
maximum levels of ^CE’
5-8. Design a collector-to-base bias circuit using a silicon transistor which
has h FE = 80 typical, 60 minimum, and 100 maximum. A 25-V supply
is to be used, and the dc bias conditions are to be V CE — 10 V and
I c = 3 mA. Calculate the maximum and minimum levels of ^ce-
5-9. The emitter current bias circuit shown in Fig. 5-6 has R L = 2.2 kft,
R e —-3.3 kfi, 7?, =6.8 kfi, R 2 = 4.7 kft, and V cc = 1 5 V. The transistor
employed is silicon and has h FE = 150 typical, 100 minimum, and 200
maximum. Calculate the typical, minimum, and maximum levels of
v ce-
5-10. Design an emitter current bias circuit using a silicon transistor with
h FE = 60 typical. The supply is V cc = 30 V, and the bias conditions
are to be V C E = 10 V and l c — 1 mA. Determine values for R t , R E> /?,,
and R 2 . Also calculate the maximum and minimum levels of V CE if
maximum h FF = 80 and minimum h FE = 40.
5-11. An emitter current bias circuit is to be designed to have v ce~& v -
The available supply is 1^ = 20 V, and the transistor has an h FE
which ranges from 40 minimum to 80 typical to 120 maximum. Ix>ad
resistance R E = 6 kft. Select suitable values for R E and bias resistances
R x and R 2 , and calculate the maximum and minimum levels for ^ce-
5-12. Determine the stability factor S for each of the circuits in Problems
5-3, 5-6, and 5-9.
5-13. The circuit designed in Question 5-11 uses a transistor with the
characteristics shown in Fig. 5-1. Draw the dc load line, determine
the bias conditions, and draw the ac load line.
5-14. Draw the dc and ac load lines for the circuit of Question 5-9. The
transistor characteristics are as shown in Fig. 5-10.
115
Problems
CHAPTER
6
6-1
Introduction
6-2
Common
Emitter
Circuit
Basic
Transistor
Circuits
There are three basic transistor circuit configurations — common emitter,
common collector, and common base. All transistor circuits, however complicated,
are based on these three configurations.
The common emitter circuit is by far the most frequently used of the
three. It has good voltage gain and high input impedance. The common
collector circuit has a voltage gain of only 1 , but it also has a very high input
impedance and a very low output impedance. The common base circuit
combines good voltage gain with the disadvantage of a very low input
impedance. However, the common base circuit can operate satisfactorily at
much higher frequencies than the common emitter circuit.
For each of the basic circuits, and for circuits consisting of more than
one stage, the gains and impedances may be calculated from a knowledge of
the A-parameter equivalent circuit.
An npn transistor is shown in Fig. 6-1 with a load resistor (R L = 10 k£2)
in series with the collector terminal. A collector supply voltage ( V cc — 20 V)
is provided with a polarity that reverse biases the collector-base junction. A
116
117
Common
Emitter
Circuit
base current l B is also provided via R B > and this results in a forward bias
( ^be) at base-emitter junction. (This is fixed current bias as described in
Section 5-3.)
A signal voltage V s having a source resistance R s is capacitor coupled
via Cj to the transistor base. The output is derived via another capacitor C 2
connected to the transistor collector. Both capacitors are open circuit to
direct currents, but offer a very low impedance to ac signals. If the signal
source were direct connected instead of capacitor coupled, there would be a
low resistance path from the base to the negative supply line, and this would
affect the circuit bias conditions. Similarly, an external load directly con-
nected to the transistor collector might alter the collector voltage.
Assume that R B is selected to give a base current of 7^ = 20 fiA. Also,
let the dc current gain factor of the transistor be h FE = 50. Then
Ic^^fe^b
= 50 X 20 X I0" 6 = 1 mA
The voltage drop across R L is 7 C 7? L = 1 mAX 10 k£2 = 10 V, and the collector
to emitter voltage V CE is V cc — (I C R L ) = 20 V— 10 V= 10 V.
The circuit dc conditions have been established as 7^ = 20 fiA> 7 C *=
1 mA, V CE = 10 V, V cc = 20 V.
If V BF is increased until I B = 25 fiA,
Ic^^fe^b
= 50 X 25 X 1 0 ' 6 = 1 .25 mA
The voltage drop across R, is 7 C 7?, = 1-25 mAX 10 kfi= 12.5 V, and L*
V cc - I c R l = 20 V - 1 2.5 V = 7.5 V.
When 1 B is 20 ptA, V CE ** 10 V 7 , and when l B is 25 /iA, r c£ * 7.5 V.
118
Basic
Transistor
Circuits
Hence, for an increase in I B of 5 pA , ^CE decreases by 2.5 V (i.e., V CE
changed by the same amount as the voltage change across R L ).
Similarly, if P BE is decreased until I B is 15 pA, I c becomes = 50 X 15
X10~ 6 = 0.75 mA and 7^ = 0.75 mAXlO kfl = 7.5 V. Thus, V CE =
20 V — 7.5 V= 12.5 V. Therefore, for a 5-/xA decrease in I B , V CE increases
by 2.5 V.
The variation in base-emitter voltage could be produced by the ac
signal V s . This might require a signal amplitude of perhaps ± 10 mV. If
V s = ± 10 mV produces V 0 = ±2.5 V, the signal may be said to be amplified
by a factor of
Vj V s = 2.5 V/10 mV = 250
or circuit amplification = 250.
The transistor current and voltage variations have no effect on the
supply voltage ( V cc ). So, when assessing the ac performance of the circuit,
V C c can be treated as a short circuit. The coupling capacitor C x also
becomes a short circuit to ac signals. Redrawing the circuit of Fig. 6-1 with
Vcc and C x shorted gives the ac equivalent circuit shown in Fig. 6-2.
In Fig. 6-2 the circuit input terminals are the base and the emitter,
and the output terminals are the collector and the emitter. Thus, the emitter
is common to both input and output, and the circuit is designated common
emitter , or sometimes grounded emitter . It is also seen from the figure that
resistors R B and R L are in parallel with the circuit input and output
terminals, respectively.
6-3
Common
Emitter
h-Parameter
Analysis
The A-parameter equivalent of the common emitter circuit in Fig. 6-1
is shown in Fig. 6-3. Figure 6-3 is drawn simply by replacing the transistor in
the common emitter ac equivalent circuit (Fig. 6-2) with its A-parameter
equivalent circuit. When an external emitter resistance ( R E ) is included in
the circuit, as shown in Fig. 6-4(a), the A-parameter equivalent circuit
becomes that of Fig. 6-4(b).
Figure 6-2. Common emitter ac equivalent circuit.
119
Common Emitter
h-Parameter
Analysis
Figure 6-4. CE circuit with emitter resistance and h-parameter equivalent circuit.
The current directions and voltage polarities shown in Figs. 6-3 and
6-4(b) are those that occur when the input signal goes positive. The
/t-parameter circuits could be analyzed rigorously to obtain exact expressions
for voltage and current gains as well as input and output impedances.
However, with a knowledge of the circuit operation and of typical ^-parame-
ter values, approximations may be made to quickly produce useful and
reasonably accurate expressions for calculations of circuit performance.
6 - 3.1 Looking into the device base and emitter terminals (Fig. 6-3), h u is
Input se en in series with h re V 0 . For a CE circuit h re is normally a very small
Impedance quantity, so that the voltage fed back ( h re V 0 ) from the output to the input
circuit is much smaller than the voltage drop across h u . Thus,
( 6 - 1 )
A typical value of h u is 1 .5 kfi.
When an external emitter resistance is connected in the circuit (Fig.
6-4), the calculation of Z { becomes a little more complicated.
K - h K + I e R e ( again ignoring h re V 0 )
= hK + R Eh + R E h fJb
= h[h„+R E { i + a a )]
and
Therefore,
Z, = h„ + R E (\+h f ,)
( 6 - 2 )
An examination of Eq. (6-2) shows that it is possible to look at a CE
circuit with an external emitter resistance and very quickly estimate its
input impedance. For example, in Fig. 6-4(a), if R E = 1 kfi, h u — 1.5 kft, and
hj e = 50, Z i is calculated as 52.5 kfi.
Equations (6-1) and (6-2) give the input impedance to the device base.
The actual circuit input impedance is R B in parallel with Z t [see Figs. 6-3
and 6-4(b)]. Therefore,
z;=R B \\z t
(6-3)
6-3.2 Since output voltage variations have little effect upon the input of a
Output CE circuit, only the output half of the circuit need be considered in
Impedance determining the output impedance. Looking into the collector and emitter
terminals, a large resistance ( 1 / h oe ) is seen. Thus,
C 6 - 4 )
Z 0 is the device output impedance. The actual circuit output imped-
120
ance is Z 0 in parallel with R L .
%-l/K. Il* t (6-5)
Since 1 / h oe is typically 1 and R L is usually very much less than 1
Mft, the circuit output impedance is approximately R L . Using this informa-
tion it is possible to tell the approximate output impedance of a CE circuit
just by looking at it. If R L in Figs. 6-3 and 6-4 is 10 kft, then the circuit
output impedance is approximately 10 k£2.
121
Common Emitter
h-Parameler
Analysis
Voltage gain = A v = V o / V t
From Fig. 6-3, V 0 = I C R L and V t = I b h u . Therefore,
6-3.3
Voltage Cain
( 6 - 6 )
The minus sign indicates that V 0 is 180° out of phase with V r (When
V t increases, V 0 decreases, and vice versa.) Knowing the appropriate h-
parameters and R L , the voltage gain of a CE circuit can be quickly
estimated. Using typical values such as R t = 10 k£2, hj t — 50, and /t„= 1.5 kS2,
a typical CE voltage gain is —330.
With an external emitter resistance (R E ) in the circuit,
V, = I b h u + I t R E
-'A +**('* +4)
-/A+* £ /,(i+V)
= / *[ A » +fl £( 1+A /.)]
and
A K '■ R ‘ - ~ h/ ' R ‘
° K /»[*„+«£(! + */,)] K + r <A' + h „)
(6-7)
Usually /? £ (1 +hj e )^>h le so that
~ Rl/
Using this expression, the voltage gain of a CE circuit with an external
emitter resistance can easily be estimated. If in Fig. 6-4 = 10 kft and
/?£= 1 k S2, the circuit voltage gain is approximately — 10.
It is interesting to note that Eqs. (6-6) and (6-7) can each be written as
— fy,(load resistance)
" (input resistance)
6-3.4
Current Gain
6-3.5
Power Gain
4
h
Therefore,
A, = h fe
( 6 - 8 )
This expression is true for GE circuits both with and without R E .
However, it is the device current gain, not the circuit current gain. Examina-
tion of Fig. 6-3 or Fig. 6-4(b) shows that the signal current ( I s ) divides
between R B and Z-.
The voltage developed across R B and Z i in parallel is
V t =
R B XZ,
R b + Z{
and l b = Vj Z { . Therefore,
h
Z t
R b X Z-
R b + Z i
i s R b
R b + Z i
and
/ =
The circuit current gain is
a;
i, LRb
4 h{R B +z,)
A’ =
hj e R B
R b + Z t
(6-9)
Once again, knowing the appropriate h -parameters, the circuit current
gain can be quickly estimated just by looking at the circuit. For such typical
values as hj e = 50, h it = 1 .5 kfi, and R b = 33 kfi, the CE circuit current gain is
approximately 48.
The power input P- — V t X I t and power output P 0 =V 0 X I 0 . Therefore,
the power gain A p = {Pj P t ) = ( V 0 X 7J/( V- X /•) = ( VJ V t ) X (/„//•)
or A p = A 0 XA t (6-10)
122
Equation (6-10) gives the device power gain. To determine the circuit
power gain, the circuit current gain A[ must be employed.
A; = A d XA,' (6-11)
Using the typical values previously calculated, ^, = 50 and A 0 = 330, a
typical CE power gain is 16,500. If an unbypassed emitter resistance ( R E ) is
included in the circuit, the value of A v is reduced and, consequently, the A p is
also reduced.
Without R e in the Circuit
Input impedance
Circuit input impedance
Output impedance
Circuit output impedance
Circuit voltage gain
Current gain
Circuit current gain
Power gain
Circuit power gain
With R e Included in the Circuit
Input impedance Z t za h u + R E ( 1 + hj t )
Circuit input impedance Z'mR B \\Z l
Voltage gain A V ^RJ R E
The common emitter circuit has good voltage gain with phase inver-
sion,' i.e., the output voltage decreases when the input voltage increases, and
vice versa. The CE circuit also has good current gain and power gain, and
relatively high input and output impedances. As a voltage amplifier, the CE
circuit is by far the most frequently used of all three basic transistor circuit
configurations.
Z t zah u = 1.5 kfi typically
z;~r b \\z.
Z e zss\/h ot = 1 M£2 typically
z:~R L \\\/h„
h ft R L
A « — - — =330 typically
h u
A t as hj e = 50 typically
...
R„+z,
A p = A v X A, = 1 6,500 typically
a;-a.xa:
In the common emitter circuit shown in Fig. 6-5 the device parameters
are A„ = 2.1 kfl, hj t = 75, and A^ = 10 -6 S. Calculate the input and output
impedances, and the voltage, current, and power gains.
123
Common Emitter
h-Parameter
Analysis
6 - 3.6
Summary of
Typical CE
Circuit
Performance
Example 6-1
124
Basic
Transistor
Circuits
+ ^cc
Figure 6-5. Circuit for Example 6-1.
solution
From Eq. (6-1), Z i &zh u = 2.1 k£2.
From Eq. (6-3), the circuit input impedance is
Z{ = 2. 1 kfl||250 kfl = 2.09 kfl
From Eq. (6-4), Z 0 t&l/h 0e =l Mfi, and from Eq. (6-5), the circuit
output impedance is
Z 0 '=l Mfi||5 k£2 = 4.98 kfl
From Eq. (6-6),
-75X5 kfi
2.1 kfl
-179
From Eq. (6-8), A,^h /e = 75, and from Eq. (6-9), the circuit current
gain is
75X250 kfi
250kfl + 2.1kfi
A' = 1 79 X74.4« 13,300
From Eq. (6-11),
Determine the effect on the performance of the common emitter circuit Example 6-2
in Example 6-1 when a 1-kfi emitter resistance is included in the circuit.
solution
From Eq. (6-2), 2^ = 2.1 kfi-f (76X1 k!2) = 78. 1 k£2, and from Eq. (6-3), the
circuit input impedance is
Z/ = 78.1 k£2||250 k£2 = 59.5 kfl
From Eqs. (6-4) and (6-5), the circuit output impedance is
Z 0 ' = 4.98 k ft
From Eq. (6-7),
— 75X5 kft
2.1 kfl + (76Xl k Q)
From Eq. (6-8), A t z&75, and from Eq. (6-9), the circuit current gain is
a;
75X250 k ft
59.5 kfl + 250 kU
From Eq. (6-11)
A' p = 4.8X60.6 = 291
In the common collector circuit, the load resistor (R L ) is in series with
the transistor emitter terminal. In the circuit shown in Fig. 6-6, the collector
supply is 20 V and the base bias voltage V B is derived from ^cc via the
6-4
Common
Collector
Circuit
Figure 6-6. Common collector circuit.
125
126
Basic
Transistor
Circuits
potential divider R j and R 2 . In this case, V B is not equal to the base-emitter
junction voltage Vbe, but is equal to the sum of V BE and V E .
Suppose I E = 1 mA; then V E =I E XR L = 1 mAXlO k£2=10 V. If
V BE = 0.7 then V B = V BE + V E — \Q.l V and the collector-emitter voltage
V CE = V cc - 1^ = 20 V — 10 V= 10 V.
If the transistor dc current gain (h FE = I c / I B ) is 50, then I E /I B also
approximately equals 50. For I E = 1 mA, 7 a w(l X 10 _3 )/50 = 20 jiA.
The dc conditions of the circuit are: I B = 20 /uA, I E = 1 mA, V CE — 10 V,
V cc = 20 V, and V B = 10.7 V.
As in the case of the common emitter circuit, any increase or decrease
in V B causes I B to vary, and consequently produces a variation in I E and V E .
If I B is made to vary by ±5 /uA, then I E increases or decreases by
approximately h FE XAI B . A/ £ = 50X( ±5 X 10 -6 ) or ±0.25 mA. The varia-
tion in V E is AV E = A I E X R L = ± 0.25 mA X 10 k£2 = ± 2.5 V.
Since V B = { V BE + V E ), any increase or decrease in V E requires an
equal variation in V B . For AV E = ±2.5 V, AV B zz ±2.5 V.
It can also be stated that an input voltage variation of A V B = ± 2.5 V
at the base produces an output at the emitter of approximately A V E = ± 2.5
V. Thus, the emitter voltage may be said to follow the base voltage, and this
gives the circuit its other name, which is emitter follower.
The supply voltage and coupling capacitors (in Fig. 6-6) may be
replaced with short circuits in order to study the ac performance. This gives
the common collector ac equivalent circuit of Fig. 6-7. Note that R B is the
parallel combination of R { and R 2 . The input terminals are base and
collector, and the output terminals are the emitter and the collector. Hence,
the name common collector (or grounded collector ).
6-5
Common
Collector
h -Parameter
Analysis
Figure 6-8 shows the ^-parameter equivalent of the practical common
collector circuit of Fig. 6-6. The CC h -parameter circuit is drawn by
replacing the transistor in the common collector ac equivalent circuit (Fig.
6-7) with its ^-parameter equivalent circuit. The current directions and
voltage polarities shown in Fig. 6-8 are those that occur when the input
signal goes positive.
/. =/l
c
c
Figure 6-8. Common collector h-parameter equivalent circuit.
127
Common
Collector
h-Parameter
Analysis
In making approximations to arrive quickly at expressions for CC
gains and impedances, it is necessary to note that h rc = 1; i.e., all of V 0 is fed
back to the input.
6 - 5.1
Input
Impedance
and
= *„ + V? £ (6-12)
Equation (6-12) is similar to the expression for the input impedance of
a CE circuit with an external emitter resistor [Eq. (6-2)]. Using Eq. (6-12), it
is possible to look at a CC circuit and very quickly estimate its input
impedance. If R L is 1 k£2, h H is 1.5 k!2, and h f( is 51, Z t is calculated as 52.5
k 12.
The input impedance determined from Eq. (6-12) is, of course, the
input impedance of the transistor. To obtain the circuit input impedance,
the parallel combination of R B and Z t must be calculated.
Z; = R B \\Z t ( 6 - 13 )
V t = l b h u + v o
= hK + /a
= I b h tc 4 - R L I b h f(
= h( h u+ h /c R L)
In the CC circuit any variation in output voltage will have a signifi-
cant effect on the input circuit. To determine Z 0 , the signal voltage is
assumed to be zero, and /„ is calculated in terms of V 0 .
6 - 5.2
Output
Impedance
and
128
Basic
Transistor
Circuits
With 1^. = 0, I t is produced by V 0 :
/ =
and
Therefore,
h /c V 0
K_ ** + (Rb\\Xs)
(6-H)
Note that the output impedance is {h u 4- the total impedance in series
with the base terminal) all divided by h fc . It is interesting to compare this to
the input impedance, which is (h u + hj c tim^s the impedance in series with
the emitter terminal). As with Z iy it is possible to look at a CC circuit and
quickly estimate Z 0 . For h tc = 1.5 k S2, R B = 5 kfi, R s = 5 kft, and fy. = 51, Z 0 is
calculated as 78.4 fl.
Once again the above equation for output impedance refers to the
device only. For the circuit output impedance, R L is in parallel with Z 0 .
z: = R l \\Z 0 (6-15)
Since R L is usually much larger than Z 0
Z>Z 0
6 - 5.3
Voltage Cain
and
A.-K/V,
V=I,R L = h fc I„R L
h=(K~K)/K
Therefore,
and
V 0
A v
W
K
K Wl/K
K i +(h /t R L /hj
129
Common
Collector
h- Para meter
Analysis
(6-16)
This agrees with what was previously discovered about the CC ampli-
fier, i.e., that it has a voltage gain of approximately 1, and that there is no
phase shift between input and output.
A = U'.=Uh
(6-17)
6-5.4
Current Gain
Equation (6-17) gives the device current gain. Since the signal current
I s divides between R B and Z i (see Fig. 6-8), the circuit current gain is smaller
than the device current gain. Using the same reasoning employed to arrive
at the current gain for the CE circuit [Eq. (6-9)], the CC circuit current gain
is
a;=
Kb + Z,
(6-18)
For the CC circuit R B is usually very much smaller than Z 0 so that R B
has quite a significant effect upon the circuit current gain. Using the typical
values previously employed, Z t = 52.5 kS2, R B = 5 kfi, and hj c = 51, A t is 51 and
A\ becomes 4.4.
The equation for CC power gain is derived exactly as for the CE 6-5.5
circuit [Eq. (6-10)]: Power Gain
and since A v ^\,
A p = A 0 X A,
A p ~A,
The circuit power gain is
(6-19)
( 6 - 20 )
130
Basic
Transistor
Circuits
6-5.6
Summary of
Typical CC
Circuit
Performance
Example 6-3
Using the typical values of A t and A\ already calculated, a typical
value of Ap is 51 and A' p is 4.4.
Input impedance
Circuit input impedance
Output impedance
Circuit output impedance
Voltage gain
Current gain
Circuit current gain
Power gain
Circuit power gain
Z i mh u + h fc R L = 52.5 kS2 typically
z;~R B \\z t
h u + (R B \\Rs)
Z o ^ = 78.4 £2 typically
h fc
z:~r l \\z 0
A.~l
A { = typically
h f‘ R *
R B +Zi
Ap^A.
a;~a;
It is seen that the common collector circuit provides current gain and
power gain, but no voltage gain. The input impedance is also very high, and
the output impedance is very low. This high Z--low Z Q characteristic allows
the amplifier to be applied where a low impedance load is to be supplied
with a signal from a high impedance source. In this application it is known
as a buffer amplifier .
In the common collector circuit in Fig. 6-9, the transistor parameters
are h u = 2.\ k£2 and ^ = 76. Calculate the circuit input and output imped-
ances, and the voltage, current, and power gains.
+ K:c
Figure 6-9. Circuit for Example 6-3.
solution
From Eq. (6-12); Z t « 2.1 kft + (76x5 k«) = 382.1 k 0, and from Eq. (6-13),
the circuit input impedance is
Z; ==382.1 kfij|10 kftjjlO k£2||10 kfi = 4.94 kfl
From Eq. (6-14), Z 0 «[2.1 k£2 + (l kftjjlO kfijjlO kfl)]/76 = 38.6 fl.
From Eq. (6-15) the actual circuit output impedance is
Z; = 38.6fl||5 kfl = 38.3fl
From Eq. (6-16), A 0 t&\.
From Eq. (6-17), A t = 76.
From Eq. (6-18), the actual circuit current gain is
76x(10kfl||10kfl)
' 382.1 kfl + (10 kB||10 kfl)
From Eq. (6-20), the power gain is
A e X A' =1X0.98 = 0.98
The common base circuit shown in Fig. 6-10 has its load resistance
( R l ) connected in series with the collector terminal of the transistor. An
emitter resistance ( R E ) is also included to avoid short circuiting the ac input,
which is applied to the transistor emitter terminal. The base voltage ( V B ) is
131
Common
Base
Circuit
6-6
Common
Base
Circuit
Figure 6-10. Common base circuit.
132
Basic
Transistor
Circuits
the sum of I E R E and Vbe- V b is derived from Vcc by the potential divider R 1
and R 2 . A capacitor C B is provided at the transistor base so that V B will not
vary when an input voltage is applied to the transistor emitter. The output is
taken from the transistor collector terminal as shown.
For the circuit of Fig. 6-10, let I E = 1 mA.
Then
V e = I e R e =\ mAX5kfi = 5 V,
and V b -V e +V be =SJ V (for a silicon transistor).
Also, I B ^I E / h FE = 20 /iA (typically, for h FE = 50),
and
Vce = ^cc ~ Ic^l ~ Vcc ~ I E (Rl + R E )
= 20 V- 1 mA(10 k£2 + 5 kfi)
= 5 V
and
The circuit dc conditions are now defined as I C ^I E = 1 mA, V B =
5.7 V, V ce ^5 V, and V c = 10 V.
An ac input signal {V^ at the emitter will cause the base-emitter
voltage (Vbe) to change, thus changing I B and J c .
When V i is positive going, ^be is reduced. This causes I B to be reduced,
and consequently I c becomes smaller. If V BE is reduced (by + VJ until
I b =15 h A, then I c = h FE l B = 50X15 jiA = 0.75 mA, and V c = V cc — I C R L =
20 V — (0.75 mAX 10 kS2) = 12.5 V.
When I B = 20 pA, V c = 10 V, and when + V { changed l B to 15 pA, V c
became 12.5 V; i.e., V c changed from 10 to 12.5 V.
It is seen that the input of + V { has produced an output of +2.5 V.
Similarly, an equal input of — V t would increase V BE , I B , and / c . and
produce an output of —2.5 V.
The ac equivalent circuit is drawn as before by replacing the supply
voltage and capacitors with short circuits, giving the circuit shown in Fig.
6-11. V- is applied between the base and the emitter, and the output is taken
from the base and the collector. Thus, the base terminal is common to both
input and output, and the circuit is called a common base circuit. Note that
the emitter resistor ( R E ) is in parallel with the input terminals.
6-7
Common
Base
h -Parameter
Analysis
The h -parameter equivalent of the practical common base circuit of
Fig. 6-10 is shown in Fig. 6-12. As always, this is done by substituting, the
transistor A-parameter circuit into the ac equivalent circuit (Fig. 6-11). Once
again the current directions and voltage polarities (in Fig. 6-12) are shown
for a positive-going input signal. It is important to note that Fig. 6-12 is
133
Common
Base
^-Parameter
Analysis
Figure 6-11. Common base ac equivalent circuit.
B
Figure 6-12. Common base /j-parameter equivalent circuit.
drawn on the assumption that the base of the transistor is ac shorted to
ground via capacitor C B (see Fig. 6-10). If C B is not present, the parallel
combination of R { and R 2 appears in series with the transistor base terminal,
and the A-parameter equivalent circuit becomes that shown in Fig. 6-13,
where R B = As w iH ^ seen, the omission of C B can seriously affect the
circuit performance.
In the CB circuit, only a fraction of the voltage is fed back to the
input; i.e., h rb is very small. Therefore, ( h rb V 0 ) can be neglected when
deriving approximate expressions for CB gains and impedances.
Neglecting ( h rb X V 0 ) in Fig. 6-12 gives
(6-21)
A typical value of h tb is 30 S2. When capacitor C B is absent, Z x must be
determined from Fig. 6-13.
v = i ,h, b + l t R B -l ( R B
— I,K t, + — h h jb R B
= ^,[^i + Rb “ ^P>^b\
6-7.1
Input
Impedance
/<
l o = A
134
Basic
Transistor
Circuits
A - /.
Figure 6-13. h-parameter equivalent of CB circuit without bypass capacitor at the base.
and
Therefore,
Z, = k, b + R B (l-h fi ) (6-22)
Using typical values of R } =33 k!2 and R 2 = 2 2 k!2, R B is calculated as
13.2 k!2. For A i6 = 30 12, /^ = 0.98, and R B = 13.2 k!2, a typical value of Z i is
294 12. This is considerably larger than the 30-12 value of Z t when the base
shunting capacitor is present. Once again, it is possible to very quickly tell
the circuit input impedance, almost just by looking at the circuit.
Equations (6-21) and (6-22) give the input impedance to the emitter
terminal of the transistor. The actual circuit input impedance is Z { in
parallel with R E .
Z' = Z t \\R E
(6-23)
6-7.2
Output
Impedance
Looking into the collector and base terminals of the CB circuit, a large
resistance {\ / h ob ) is seen. Since the output circuit has little effect upon the
input of a common base circuit, the output impedance may be taken as
W Thus >
4«T- (6-24)
Kb
As always, the equation for Z 0 gives the device output resistance. The
actual circuit output resistance is R L in parallel with Z 0 .
Z 1 = R l\\ Z o
( 6 - 25 )
R L is usually much smaller than 1 / h^, so the circuit output impedance
is approximately R L . Here again a circuit output impedance can be quickly
estimated just by looking at the circuit.
K
v t
135
Common
Base
^-Parameter
Analysis
6-7.3
Voltage
Cain
From Fig. 6-12, V 0 = I e R L and V^I t h tb - Thus,
'A
or
h/b^L
Kb
(6-26)
Using typical values of A^ = 0.98, R L = 10 ktt, and ^ = 30 the
voltage gain is 327. This is similar to the typical voltage gain calculated for
the CE circuit. No minus sign is present in the CB voltage gain equation,
indicating that the output voltage is in phase with the input voltage. Note
also that Eq. (6-26) was derived for the circuit with the base bypass
capacitor included (Fig. 6-12). When C b is absent, V 0 and V ( arc derived as
follows from Fig. 6-13:
K-Wl
and
= KKb + ~ I^Ra
-4[a*+«*0-V)1
i,r l
A "~ 4[A,.+«*(1-V)]
V)
(6-27)
Again taking typical values of ^ = 0.98, 7?^ = 10 kft, A lA »30 ft, /?, =
33 kft, and R 2 = 22 kft, A v is 33.3. This is significantly smaller than the
typical voltage gain of 327 obtained when C B is included in the circuit. Note
that Eqs. (6-26) and (6-27) can each be written as
hjb X (output impedance)
0 input impedance
6 - 7.4
Current
Gain
6 - 7.5
Power
Gain
6 - 7.6
Summary
of Typical
CB Circuit
Performance
A,=
4
/•
4
4
( 6 - 28 )
A typical value of is 0.98. Equation (6-28) applies for the circuit
both with C B included and without C B . Once again, the expression devel-
oped for current gain represents the current gain of the device. The signal
current is divided between R E and Z t , giving a lower value of circuit current
gain than that obtained by the use of Eq. (6-28).
a;
h/b^E
(6-29)
Since R E is usually much greater than Z { for a CB circuit, the value of
A' is usually approximately equal to h ib .
The formula for CB power gain is the same as for all other circuits.
A p = A 0 XA { (6-30)
Where A[ is significantly different from A-, the circuit power gain
becomes
A p = A v XA' (6-31)
Using the typical values of A v = 327 and A i = 0.98, A p is 320. Without
C B in the circuit, a typical A v is 33.3 and A p is 32.7.
With C B Included in the Circuit
Input impedance
Circuit input impedance
Output impedance
Circuit output impedance
Voltage gain
Current gain
Circuit current gain
Power gain
Circuit power gain
Z ' « h ib — 30 typically
z;**h ib \\R E
Z 0 zn — - = 1 typically
Kb
Kb
hfiRr
A v tt-^= 327 typically
Kb
A i = hfl = 0.98 typically
A' =
h/b^E
R E + Z t
A p = A v XA i = 320 typically
Ap = A 0 X A {
136
With C B Absent from the Circuit
Input impedance
Circuit input impedance
Voltage gain
b + R b ( 1 bp)
z ;=r e k
137
Common
Base
6-Parameler
Analysis
The common base circuit provides voltage gain and power gain, but no
current gain. Like the common emitter circuit, it has a high output imped-
ance. But unlike the common emitter circuit, its input impedance is very
low, and this renders it unsuitable for most voltage amplifier applications. It
is normally applied only for very high frequency voltage amplification.
For the common base circuit in Fig. 6-14, the transistor parameters are Example 6-4
h tb = 27.6 £2, ^ = 0.987, and = 1 0 — 6 S. Calculate the values of input and
output impedance, and the voltage, current, and power gains for the circuit.
solution
From Eq. (6-21),
27.6 £2
From Eq. (6-23), the circuit input impedance is
Z/i=»27.6 £2||5 k£2«27.4£2
R.
1
Figure Circuit for Example 6-4
From Eq. (6-24),
138
Basic
Transistor
Circuits
Example 6-5
r«l M8
10-e
and from Eq. (6-25), the circuit output impedance is
z;=*jz 0 «iok8
From Eq. (6-26),
0.987 X 10 k8 ocft
^-—2710 358
From Eq. (6-28),
A- = 0.987
From Eq. (6-29), the actual circuit current gain is
„ 0.987X5 k8
1 _ 27.6 Q + 5 kfi 98
From Eq. (6-31), the power gain is
A p = A 0 X A' — 358 X 0.98 = 351
Calculate the new values of input impedance and voltage gain for the
circuit of Fig. 6-14 when capacitor C B is removed from the circuit.
solution
, 18 k8x6k8
fl 18 kfi + 6 kSJ
=4.5 kQ
From Eq. (6-22),
^ = 27.6 8 + 4.5 k8( 1-0.987) = 86.1 8
From Eq. (6-23), the circuit input impedance is
Z[ = 86. 1 8||5 k8 = 84.6 8
A =
0.987X10 k8
27.6 8 + 4.5 k8( 1-0.987)
= 115
From Eq. (6-27),
When the output of one circuit (or one stage of an amplifier) is 6-8
connected to the input of another stage, as shown in Fig. 6- 15(a), the circuits Cascaded
are said to be connected in cascade. A signal applied at the input is
amplified by the first stage and then further amplified by the second stage. If Qrcuits
stage 1 has a voltage gain of 100, and stage 2 has a voltage gain of 200, then
the overall voltage gain is (100 X 200) or 20,000. In calculating the gain of
the first stage it must be noted that the input impedance of stage 2 is in
parallel with the load resistance of stage 1, and this affects the voltage gain
of stage 1 .
The first step in analyzing the circuit of Fig. 6- 15(a) is to draw the ac
equivalent circuit by replacing the supply voltage and all capacitors with
short circuits. This gives the circuit shown in Fig. 6- 15(b). The transistor
r
n
r
V,
1 ;
L
>
U 7
k 1“
♦
(b) ac equivalent circuit of two stage CE amplifier
(c) h parameter equivalent circuit for two stage CE amplifier
Figure 6-15. Two-stage cascaded CE amplifier, ac equivalent, and h-parameter equiv-
alent circuit.
139
140
Basic
Transistor
Circuits
A-parameter equivalent circuits are next substituted into the ac equivalent
circuit to give the A-parameter circuit of Fig. 6- 15(c). The circuit is then
analyzed stage by stage.
Example 6-6
In the circuit of Fig. 6-15, both transistors have hj e = 100 and h u = 2 k£2.
Also, /? LI = 7? £2 = 4.7 kfl and = = k£2. Calculate the input and
output impedances of the circuit, and the overall voltage, current, and
power gains.
solution
Circuit input impedance:
f 2 kfl X 330 kfi
Z '' h ^ R “' 2kJ2 + 330kfi _1 '" kn
and the input impedance of stage 2 is
Z l2 — A l(f || R b 2 — 1 .99 kfi
The load on stage 1 is
4.7 kflx 1.99 kfi
u 4.7 kG+ 1.99 kS2 ~ 14 kn
The voltage gain for stage 1 is
, h /,{ R n\\ z a) 100X1.4 k« „„
Av h u 2 kU 70
The voltage gain for stage 2 is
_ _ 100X4.7 k SI _„ 35
* h ie 2 kft
The overall voltage gain is
A V = A V j X A v2 = 70 X 235 = 1 6,450
The current gain for stage 1 is
where Z t is the device input impedance.
100X330 kil _
— - ■ = 99 4
330 kft + 2kn
Current I el in Fig. 6- 15(c) is divided between h u2 and the parallel
combination of *L I and R B2 -
A h /<2( R B2\\ R Li) _ 100X(4.7 k!2||330 kS2)
,2 ( R B2\\ R Li) + h u2 (4.7 ktt||330 kS2) + 2 kS2
100X4.63 kJ2
4.63 kS2 + 2 kS2 598
The overall current gain is
A, = A a XA , 2 = 99.4 X 69.8 = 6938
The power gain is
A p = A v XA t = 1.645X 10 4 X 6.938 X 10 3 = 1.14X 10 8
The circuit output impedance is
Z V ^R L 2 = 4.7 k 12
Common emitter circuit. Transistor circuit in which the input is applied
between base and emitter, and the output is taken across collector and
emitter; used as a voltage amplifier.
Common collector circuit. Transistor circuit in which the input is applied
between base and collector, and the output is taken across emitter and
collector; used as a high-input impedance, low-output impedance
circuit.
Common base circuit. Transistor circuit in which the input is applied
between emitter and base; and the output is taken across collector and
base; used as a high-frequency amplifier.
Emitter follower. Same as common collector circuit .
Buffer amplifier. Amplifier with a high-input resistance, a low-output
resistance, and a gain of 1; e.g., a common collector circuit.
6-1. Sketch a practical common emitter circuit showing all current dirrcc-
tions and voltage polarities. Identify input and output and all compo-
nents.
141
Review
Questions
Glossary of
Important
Terms
Review
Questions
142
Basic
Transistor
Circuits
6-2. List the characteristics of a GE circuit and state its usual application.
6-3. Sketch the ac equivalent circuit for a CE circuit. Also sketch the
h -parameter equivalent for the CE circuit. Identify all components
and state typical values.
6-4. Sketch a practical CE circuit with an emitter resistance included.
Show how the inclusion of R E affects the A -parameter equivalent
circuit.
6-5. Repeat Question 6-1 for a common collector circuit.
6-6. Repeat Question 6-2 for a CC circuit.
6-7. Repeat Question 6-3 for a CC circuit.
6-8. Repeat Question 6-1 for a common base circuit.
6-9. Repeat Question 6-2 for a CB circuit.
6-10. Repeat Question 6-3 for a CB circuit.
Problems
6-1. A common emitter circuit uses a transistor with hj e = 40, h u = 1 k£2,
and — 10 -6 S. Load resistance R L is 3.3 kS2 and bias resistance
/? b = 120 kfi. Calculate the input impedance, output impedance,
voltage gain, current gain, and power gain.
6-2. If the circuit described in Problem 6-1 has a 330-ft emitter resistance
included, calculate the new values of all impedances and gains.
6-3. A common collector circuit employs a transistor with A^ = 40 and
h k = 1 k£2. The load resistance R L = 20 k£2, and the bias resistances are
7?! = 33 kfi, /? 2 = 47 kfl. The signal source has a resistance /? 5 = 600 £2.
Determine all impedances and gains for the circuit.
6-4. A common base circuit uses a transistor with h ib — 50 £2, = 0.99, and
h ob = 10 -6 S. The value of R L is 3.9 k£2 and R E — 2.2 k£2. Determine all
gains and impedances for the circuit.
6-5. The circuit of Problem 6-4 has bias resistances R l = 27 k£2 and
R 2 = 18 k£2. If no bypassing capacitor is provided at the base of the
transistor, calculate the new values of input impedance, voltage gain,
and power gain for the circuit.
6-6. A two-stage common emitter amplifier uses transistors which each
have hj t = 80 and h u = 1.5 k£2. R u — R L2 — 8.2 k£2 and R Bl — R B2 — 220
k£2. Calculate the input and output impedances of the circuit, and
the overall voltage, current, and power gains.
6-7. A two-stage amplifier consists of two identical common emitter stages
as described in Problem 6-1. Calculate the overall voltage and
current gains of the circuit.
6-8. The common collector circuit described in Problem 6-3 is capacitor
coupled to the output of the common emitter circuit in Problem 6-2.
Calculate the overall voltage and current gains of the circuit.
Transistor and
integrated
Circuit
Fabrication
The methods employed to manufacture a transistor determine its
electrical characteristics, and thus dictate the applications for which it may
be used. For example, low-current, fast-switching transistors must be de-
signed differently from high-power transistors.
An integrated circuit (IG) consists of many components making up a
complete circuit in one small package. The major types of IG’s are monolithic ,
thin-film , thick-film , and hybrid circuits. For mass production, the monolithic
process is the most economical, but it does have some disadvantages.
Current Gain. Good current gain requires that most charge carriers from
the emitter pass rapidly to the collector. Thus, there should be little outflow
of charge carriers via the base terminal, and there should be few carrier
recombinations within the base region. These conditions dictate a very
narrow, lightly doped base region.
High Power. High-power transistors must have large emitter surfaces to
provide the required quantities of charge carriers. Large collector surface
143
CHAPTER
7
7-1
Introduction
7-2
Effects of
Transistor
Construction
on Electrical
Performance
144
Transistor and
Integrated
Circuit
Fabrication
7-3
Processing of
Semiconductor
Materials
areas are also required to dissipate the power involved without overheating
the collector-base junction.
Frequency Response. For greatest possible frequency response, the base
region should be very narrow in order to ensure a short transit time of
charge carriers from emitter to collector. Input capacitance must also be a
minimum, and this requires a small area emitter-base junction, as well as a
highly resistive (i.e., lightly doped) base region.
Since power transistors require large emission surfaces, and high-
frequency performance demands small emitter-base areas, there is a conflict
in high-frequency power transistors. To keep the junction area to a mini-
mum and still provide adequate charge carrier emission, the emitter-base
junction is usually in the form of a long thin zigzag strip.
Switching Transistors. Fast switching demands the same low junction
capacitances that are required for good high-frequency performance. A good
switching transistor must also have low saturation voltages and a short storage
time (see Section 8-7). For low saturation voltages, the collector regions must
have low resistivity. Short storage time demands fast recombinations of
charge carriers left in the depletion region at the saturated (i.e., forward
biased) collector-base junction. This fast recombination is assisted by addi-
tional doping of the collector with gold atoms.
Breakdown and Punch-Through. Since the collector-base junction is op-
erated with reverse bias, the usable collector potential is limited by its
reverse breakdown voltage. To achieve high breakdown voltages, either the
collector region or the base region must be very lightly doped.
The depletion region at the collector-base junction penetrates deepest
into the most lightly doped side. If the base is more lightly doped than the
collector, the collector-base depletion region will penetrate deep into
the base. If it spreads far enough into the base, it may link up with the
emitter-base depletion region. When this happens, a state of punch-through is
said to exist, and dangerously large currents may flow. To avoid punch-
through, the collector region is sometimes more lightly doped than the base.
The collector-base depletion region then spreads into the collector, rather
than the base.
Preparation of Silicon and Germanium. Silicon is one of the commonest
elements on the earth. It occurs as silicon dioxide (Si0 2 ) and as silicates, or
mixtures of silicon and other materials. Germanium is derived from zinc or
copper ores. When converted to bulk metal, both silicon and germanium
contain large quantities of impurities. Both metals must be carefully refined
before they can be used for device manufacture.
Semiconductor material is normally poly crystalline after it has been
refined. This means that it is made up of many individual formations of
atoms with no overall fixed pattern of relationship between them. For use in
transistors the material must be converted into single crystal material; i.e., it
must be made to follow a single atomic formation pattern throughout.
In its final refined form for electronic device manufacture, the silicon
or germanium is in single crystal bars about 2.5 cm in diameter and perhaps
30 cm long. The bars are sliced into disc-shaped wafers about 0.4 mm thick,
and the wafers are polished to a mirror surface. Several thousand transistors
are fabricated upon the surface of each wafer; then it is scribed and cut like
glass.
Diffusion and Epitaxial Growth. When wafers of n-type material are
heated to a very high temperature in an atmosphere containing p - type
impurities [Fig. 7- 1 (a)] some of the impurities are absorbed or diffused into
each wafer. The outer layer of the n-type material is converted into p- type.
The process can be continued by further heating the material in an
atmosphere containing n-type impurities. Thus, the wafer can have an outer
rt-type layer, with a />-type layer just below it, and an n-type center. This is
145
Processing of
Semiconductor
Materials
n-type
epitaxial layer
pdoped
by diffusion
(c) The epitaxial process
Figure 7-1. Diffusion and epitaxial growth.
146
Transistor and
Integrated
Circuit
Fabrication
the diffusion process illustrated in Fig. 7- 1(a) and (b). Since the process is very
slow (about 2.5 jum/hour), very narrow diffused regions can be accurately
produced by careful timing.
The epitaxial process [Fig. 7-l(c)] is similar to the diffusion process,
except that atoms of germanium or silicon are contained in the gas
surrounding the semiconductor wafer. The semiconductor atoms in the gas
grow on the wafer in the form of a very thin layer. This layer is single crystal
material, and may be p - type or n-type, according to the impurity content in
the gas. The epitaxial layer may then be doped by the diffusion process.
7-4
Transistor
Fabrication
Alloy Transistors. For manufacture of alloy transistors, single crystal «-type
wafers are cut up into many small sections or dice, which each form the
substrate for one transistor. A small pellet of p - type material is melted on
one side of the substrate until it partially penetrates and forms an alloy with
the substrate [Fig. 7-2(a)]. This process, which forms a /^-junction, is then
repeated on the other side of the substrate to form a pnp transistor. One of
the /^-junctions has a large area, and one has a small area. The small-area
junction becomes the emitter-base junction, and the large one becomes the
collector-base junction. One reason for this is that the large area junction
will most easily collect most of the charge carriers emitted from the small-
area junction. Another more important reason is that most of the power
dissipation in the transistor occurs at the collector-base junction. Suppose a
silicon transistor has a collector current of 7 C =10 mA and a collector-
emitter voltage of Vce = 10 V. The total power dissipated in the transistor is
P= F C£ X/ C =10 VX 10 mA= 100 mW
Figure 7-2. Alloy and microalloy transistors.
The emitter-base voltage is V BE = Q1 V,and the collector-base voltage is
y, cb= VcE~ ^£*10 V-0.7 V = 9.3 V
The power dissipated at the emitter-base junction is
K m X/ c = 0.7VX1 0mA = 7mW
At the collector-base junction, the power dissipated is
*cfi x/ c = 9.3 VX10mA= 93 mW
Microalloy Transistors. Because very narrow base widths are difficult to
obtain with alloy transistors, they cannot be made to perform well at high
frequencies. To improve the high-frequency performance, holes are first
etched partially into the substrate from each side, leaving a very thin portion
between. By a plating process, surfaces of impurity material are formed on
each side of the thin n-type portion [Fig. 7-2(b)]. Heat is then applied to
alloy the impurities into the base region. This process results in very thin
base regions and good high-frequency performance.
Microalloy Diffused Transistors. In microalloy transistors, the collector-
base depletion region penetrates deeply into the very thin base. Thus, a
major disadvantage is that punch- through can occur at very low collector
voltages. In microalloy diffused transistors the substrate used is initially
undoped. After the holes are etched in each side of the wafer to produce the
thin base region, the base is doped by diffusion from the collector side. The
diffusion can be carefully controlled so that the base region is heavily doped
at the collector side, with the doping becoming progressively less until the
material is almost intrinsic at the emitter. With this kind of doping, the
collector-base depletion region penetrates only a short distance into
the base, and much higher punch-through voltages are achieved.
Diffused Mesa. In the production of mesa transistors, the thin wafer is kept
as a whole disc (i.e., it is not diced first). Several thousand transistors are
simultaneously formed on the wafer, by the diffusion process.
As illustrated in Fig. 7-3 the main body of the wafer becomes the
rt-type collectors, the diffused /^-regions become the bases, and the final n
regions are the emitters. Metal strips are deposited on the base and emitter
surfaces to form contacts.
The individual transistors could be separated by the usual process of
scribing lines on the surface of the wafer and breaking it into individual
units. This would give a very rough edge, however, and there would likely be
high leakage between collector and base. So, before cutting the disc, the
transistors are isolated by etching away the unwanted portions of the
diffused area to form separating troughs between devices. This leaves the base
and emitter regions projecting above the main wafer which forms the
collector region. This is the mesa structure. The narrow base widths which
can be achieved by the diffusion process make the mesa transistor useful at
very high frequencies.
147
Transistor
Fabrication
146
Transistor and
Integrated
Circuit
Fabrication
/7-type collector
Figure 7-3. Mesa transistors.
Epitaxial Mesa, One of the disadvantages of the process just described is
that because the collector region is highly resistive diffused mesa transistors
have a high saturation voltage (see Sect. 8-7). Such devices are unsuitable for
saturated switching applications. This same characteristic (high collector
resistance) is desirable to give high punch-through voltages. One way to
achieve both high punch-through voltage and low saturation levels is to
employ the epitaxial process.
Starting with a low-resistive (i.e., highly doped) wafer, a thin, highly
resistive epitaxial layer is grown. This layer becomes the collector, and the
base and emitter are diffused as before. The arrangement is illustrated in
Fig. 7-4. Now the punch-through voltage is high because the collector-base
depletion region spreads deepest into the lightly doped collector. Saturation
voltage is low, because the collector region is very narrow, and the main
body of the wafer through which collector current must flow has a very low
resistance.
Diffused p- type emitter
Diffused /7-type base
High resistive
epitaxial layer
(p-type collector)
Low resistive
substrate
(heavily doped)
Figure 7-4. Epitaxial mesa transistor.
Diffused Planar Transistor. In all the previously described transistors the
collector-base junction is exposed (within the transistor package), and
substantial charge carrier leakage can occur at the junction surface. In the
planar transistor (Fig. 7-5) the collector-base junction is covered with a
layer of silicon dioxide. This construction gives a very low col lector -base
leakage current. I CB0 may be typically 0. 1 nA.
Annular Transistor. A problem which occurs particularly with pnp planar
transistors is the induced channel. This results when a relatively high voltage is
applied to the silicon dioxide surface, e.g., a voltage at one of the terminals.
Consider the pnp structure shown in Fig. 7-6. If the surface of the silicon
dioxide becomes positive, minority charge carriers within the lightly doped
p - type substrate are attracted by the positive potential. The minority charge
Figure 7-6. Annular transistor.
150
Transistor and
Integrated
Circuit
Fabrication
carriers concentrate at the upper edge of the substrate and form an n-type
channel from the base to the edge of the device. This becomes an extension
of the n-type base region and results in charge carrier leakage at the exposed
edge of the collector-base junction.
The problem arises because the />-type/ substrate is highly resistive. If it
were heavily doped with p- type charge carriers, the concentration of n-type
carriers would be absorbed; i.e., electrons would be swallowed by holes. The
introduction of a heavily doped p- type ring around the base, as in Fig. 7-6,
interrupts the induced channel and isolates the collector-base junction from
the device surface. The annual transistor, therefore, is a high-voltage device
with the low collector-base leakage of the planar transistor.
7-5
Integrated
Circuit
Fabrication
Monolithic Integrated Circuits. In a monolithic integrated circuit all compo-
nents are fabricated by the diffusion process on a single chip of silicon.
Component interconnections are provided on the surface of the structure
and external connecting wires are taken out to terminals as illustrated in
Fig. 7-7(a). Although the monolithic circuit has distinct disadvantages, the
vast majority of integrated circuits use this type of construction because it is
the most economical process for mass production.
Thin-Film Integrated Circuits. Thin-film integrated circuits are con-
structed by depositing films of conducting material on the surface of a glass
or ceramic base. By controlling the width and thickness of the films, and
using different materials selected for their resistivity, resistors and conductors
are fabricated. Capacitors are produced by sandwiching a film of insulating
oxide between two conducting films. Inductors are made by depositing a
spiral formation of film. Transistors and diodes cannot be produced by
thin-film techniques; tiny discrete components must be connected into the
circuit.
One method employed to produce thin films is vacuum evaporation , in
which vaporized material is deposited on a substrate contained in a vacuum.
In another method, called cathode sputtering , atoms from a cathode made of
the desired film material are deposited on a substrate located between a
cathode and an anode.
Thick-Film Integrated Circuits. Thick- film integrated circuits are some-
times referred to as printed thin-film circuits. In this process silk- screen printing
techniques are employed to create the desired circuit pattern on a ceramic
substrate. The screens are actually made of fine stainless steel wire mesh,
and the inks are pastes which have conductive, resistive, or dielectric
properties. After printing, the circuits are high temperature fired in a
furnace to fuse the films to the substrate. Thick-film passive components are
fabricated in the same way as those in thin-film circuits. As with thin-film
circuits, active components must be added as separate devices. A portion of a
thick-film circuit is shown in Fig. 7-7(b).
151
Integrated
Circuit
Fabrication
Conductors
(b) Enlarged portion of
thick-film 1C
Figure 7-7. Construction of monolithic, thick-film, and hybrid integrated circuits.
Integrated circuits produced by thin- or thick-film techniques usually
have better component tolerances and give better high-frcqucncy perfor-
mance than monolithic integrated circuits.
Hybrid or Multichip Integrated Circuits. Figure 7-7(c) illustrates the
structure of a hybrid or multichip integrated circuit. As the name implies, the
circuit is constructed by interconnecting a number of individual chips. The
active components are diffused transistors or diodes. The passive components
may be groups of diffused resistors or capacitors on a single chip, or they
may be thin-film components. Wiring or a metalized pattern provides
connections between chips.
152
Transistor and
Integrated
Circuit
Fabrication
Like thin- and thick-film IC’s, multichip circuits usually have better
performance than monolithic circuits. Although the process is too expensive
for mass production, multichip techniques are quite economical for small
quantities and are frequently used as prototypes for monolithic integrated
circuits.
7-6
Integrated
Circuit
Components
Transistors and Diodes. The epitaxial planar diffusion process described in
Section 7-3 is normally employed for the manufacture of IC transistors and
diodes. Collector, base, and emitter regions are diffused into a silicon
substrate, as illustrated in Fig. 7-8, and surface terminals are provided for
connection.
In discrete transistors the substrate is normally used as a collector. If
this were done with transistors in a monolithic integrated circuit, all transis-
tors fabricated on one substrate would have their collectors connected
together. For this reason, separate collector regions must be diffused into the
substrate.
Even though separate collector regions are formed, they are not
completely isolated from the substrate. Figure 7-8 shows that a pn -junction is
formed by the substrate and the transistor collector region. If the circuit is to
function correcdy, these junctions must never become forward biased. Thus,
in the case of a jfr-type substrate, the substrate must always be kept negative
with respect to the transistor collectors. This requires that the substrate be
connected to the most negative terminal of the circuit supply.
n - type
emitter
_p-type
base
n-type
collector
p-type substrate
4
Substrate
borders
Figure 7-8. Effect of IC collector-substrate junctions.
The unwanted, or parasitic junctions , even when reverse biased, can still
affect the circuit performance. The junction reverse leakage current can be a
serious problem in circuits that are to operate at very low current levels. The
capacitance of the reverse- biased junction can affect the circuit high-
frequency performance, and the junction breakdown voltage imposes limits
on the usable level of supply voltage. All these factors can be minimized by
using highly resistive material for the substrate; i.e., if it is very lightly
doped, it will behave almost as an insulator.
Integrated circuit diodes are usually fabricated by diffusion exactly as
transistors. Only two of the regions are used to form one /^-junction, or the
collector region may be connected directly to the base region so that the
device operates as a saturated transistor.
Resistors. Since the resistivity of semiconductor material can be altered
with doping density, resistors can be produced by doping strips of material as
required. The range of resistor values that may be produced by the diffusion
process varies from ohms to hundreds of kilohms. The typical tolerance,
however, may be no better than ±5%, and may even be as high as ±20%.
On the other hand, if all resistors are diffused at the same time, then the
tolerance ratio can be good. For example, several resistors having the same
nominal value may all be +20% in error and have actual resistance values
within a few percent of each other.
Another method of producing resistors for integrated circuits uses the
thin-film technique. In this process a metal film is deposited on a glass or
silicon dioxide surface. The thickness, width, and length of the film are
regulated to give a desired resistance value. Since diffused resistors can be
processed while diffusing transistors, the diffusion technique is the least
expensive and, therefore, the most frequently used.
Capacitors. All /w-junctions have capacitance, so capacitors may be pro-
duced by fabricating suitable junctions. As in the case of other diffused
components, parasitic junctions are unavoidable. Both the parasitic and the
main junction must be kept reverse biased to avoid direct current flow. The
depletion region width and, therefore, the junction capacitance also vary
with changes in reverse bias. Consequently, for reasonable stability in
capacitor values, a dc reverse bias much greater than signal voltages must be
maintained across the junction.
Integrated circuit capacitors may also be fabricated by utilizing the
silicon dioxide surface layer as a dielectric. A heavily-doped n-region is
diffused to form one plate of the capacitor. The other plate is formed by
depositing a film of aluminum on the silicon dioxide which forms on the
wafer surface. With this type of capacitor, voltages of any polarity may be
employed, and the breakdown voltage is very much larger than that for
diffused capacitors. The junction areas available for creation of integrated
circuit capacitors arc very small indeed, so that only capacitances of the
order of picofarads are possible.
153
Integrated
Circuit
Components
7-7
Transistor and
Integrated
Circuit
Packaging
Low-power transistors may simply be encapsulated in resin and the
connecting leads left protruding [Fig. 7-9(a)]. This has the advantage of
cheapness, but offers a limited range of operating temperature. In another
method of low-power transistor packaging [illustrated in Fig. 7-9(b)], the
device is hermetically sealed in a metal can. The transistor is first mounted
with its collector in contact with a heat-conducting metal base plate. Wires,
which are insulated from the base plate, pass through the plate for emitter
and base connections. The collector connecting wire is then welded directly
to the heat-conducting plate, and the covering metal can is finally welded to
the base plate.
For high-power transistor packaging, a sealed can (TO -3) is usually
employed [Fig. 7-10(a)]. In this case, however, the heat-conducting plate is
much larger and is designed for mounting directly on a heat sink. Connect-
ing pins are provided for the base and the emitter, and the collector
connection is made by means of the metal base plate. This is not the only
form of power transistor package. For higher power dissipation there are
stud-mounted devices [Fig. 7-1 0(b)], and for lower dissipation applications
plastic packages are used [Fig. 7-10(c)].
Integrated circuits, like all semiconductor devices, must be packaged to
provide mechanical protection and terminals for electrical connection.
Several standard packages in general use are illustrated in Fig. 7-11.
(a) Plastic encapsuled
transistor (To - 92 package)
154
(b) Transistor in sealed can (To - 5 or To -18)
Figure 7-9. Low-power transistor packaging.
(b) Stud mounted type (c) Plastic package
Figure 7-10. Power transistor packages.
Metal
can
14 pin plastic
dual-inline
8 pin plastic
•dual-in-line
Bottom
view of
can
10
Ceramic
flat pack
Figure 7-11. Integrated circuit packages.
155
156
Glossary of
Important
Terms
Glossary of
Important
Terms
The metal can type of container provides electromagnetic shielding for
the IC chip, which cannot be obtained with the plastic or ceramic packages.
The plastic dual-in-line package is much cheaper than other packages, and
is widely used for general industrial and consumer applications where
high-temperature performance is not required. Ceramic or metal containers
are necessary where a circuit is subjected to high temperatures. Flat packs
and dual-in-lines are much more convenient for circuit board use than cans,
because of their lead arrangement and because they are flatter and allow
greater circuit densities. TO-3 type cans [Fig. 7- 10(a)] are used for packag-
ing integrated circuits that dissipate a lot of heat, e.g., voltage regulators.
Large integrated circuits such as microprocessor units use the dual-in-line
type of package with perhaps 40 connecting pins.
Single crystal material. Semiconductor material in which the atoms are
aligned into a definite pattern throughout.
Diffusion process. Process in which semiconductor material is heated in
atmosphere containing impurity atoms which soak, or diffuse, into the
material.
Epitaxial growth. Layer formation of silicon or germanium atoms upon
semiconductor wafer when it is heated in an atmosphere containing
semiconductor atoms.
Alloy transistor. Device manufactured by a process in which small pellets
of semiconductor are melted into a semiconductor wafer.
Microalloy. Transistor manufacturing technique in which holes are etched
in a wafer before the alloying process.
Microalloy diffused. Extension of microalloy technique with impurities
diffused into base region.
Diffused mesa. Diffused transistor with base and emitter regions raised
above the main body of the semiconductor wafer.
Epitaxial mesa. Mesa transistor which is formed by epitaxial growth
process.
Diffused planar. Diffused transistor in which collector-base junction is
buried inside the wafer.
Annular transistor. Diffused planar transistor with added ring of heavily
doped substrate around the base region.
Thick-film IC. Integrated circuit constructed by silk-screen printing tech-
niques, using conducting and insulating inks.
Hybrid IC. Integrated circuit constructed by interconnecting several indi-
vidual chip components in one package.
Multichip IC. Same as hybrid IC.
Monolithic integrated circuit. Integrated circuit in which components are
fabricated on a single chip of silicon.
Thin-film IC. Integrated circuit constructed by depositing thin metallic
films on a glass or ceramic base.
7-1. Explain the various requirements that must be fulfilled in the fabri-
cation of transistors for maximum performance with respect to (a)
current gain, (b) power dissipation, (c) frequency response, (d)
switching response, (e) breakdown voltage.
7-2. Describe the process of preparing semiconductor material for device
manufacture.
7-3. Explain the process of diffusion and epitaxial growth, and discuss
their application to transistor manufacture.
7-4. Describe the microalloy and microalloy diffusion techniques for tran-
sistor manufacture. Explain the advantages and disadvantages of
these transistors.
7-5. Using sketches, explain the diffused mesa and epitaxial mesa transis-
tors. Discuss the reason for the mesa construction and the advantages
and disadvantages of mesa transistors.
7-6. Explain the manufacturing process for diffused planar and annular
transistors, and discuss their advantages and disadvantages.
7-7. Show that most of the power dissipation in a transistor occurs at the
collector-base junction.
7-8. Briefly explain the thin-film and thick-film methods of integrated
circuit manufacture, and discuss their advantages and disadvantages.
7-9. Using illustrations, explain the fabrication process for monolithic
integrated circuits. Discuss the advantages and disadvantages of
monolithic IC’s.
7-10. Draw a sketch to show the construction of two diffused integrated
circuit transistors. Sketch the circuit diagram of the two devices,
showing the parasitic components. Explain the circuit and state any
precautions necessary in the use of the device.
7-11. Briefly explain how diodes, resistors, and capacitors are fabricated in
monolithic integrated circuits.
7-12. Draw sketches to illustrate typical transistor and integrated circuit
packages. Briefly explain.
Review
Questions
157
CHAPTER
8
8-1
Introduction
8-2
The
Transistor
Data Sheet
Transistor
Specifications and
Performance
The electrical characteristics for each type of transistor are specified on
a data sheet published by the device manufacturer. The specifications must
be correctly interpretated if transistor failure is to be avoided and optimum
performance achieved. The maximum power that may be dissipated in the
device is normally listed for a temperature of 25° C. This must be derated
for operation at higher temperatures. Transistor cutoff frequency is usually
defined for the case of a common base circuit. There is an equation which
relates the common emitter cutoff frequency to the common base cutoff
frequency. Other items that depend upon the circuit configuration are input
capacitance, noise figure, current gain, and switching time.
To select a transistor for a particular application, the data sheets
provided by device manufacturers must be consulted. Portions of typical
data sheets are shown in Figs. 8-1 and 8-2.
Most data sheets start off with the device type number at the top of the
page, a descriptive title, and a list of major applications of the device. This is
158
2n3903 (SILICON)
2n3904
V c , = 60 V
l c = 200 mA
= 4.0 pf (mix)
(TO-92)
NPN silicon annular transistors, designed lor gen-
eral purpose switching and amplifier applications ,
features one-piece, injection- molded plastic package
for high reliability. The 2N3903 and 2N3904 are com-
plementary with types 2N3905 and 2N3906, respectively .
MAXIMUM RATINGS (Ta = 25*C unless otherwise noted)
Characteristic
Symbol
Rating
Unit
Collector-Base Voltage
V CB
60
Vdc
Collector- Emitter Voltage
v CEO
40
Vdc
Emitter-Base Voltage
V EB
6
Vdc
Collector Current
k;
200
mAdc
Total Device Dissipation @ T A = 60°C
PD
210
mW
Total Device Dissipation @ T A = 25°C
Pd
310
mW
Derate above 25°C
2.61
mW/°C
Thermal Resistance, Junction to Ambient
® JA
0.357
°C/mW
Junction Operating Temperature
Tj
135
°C
Storage Temperature Range
T stg
-55 to +135
°c
ELECTRICAL CHARACTERISTICS <Ta = 25*0 unless otherwise noted)
[ Characttmtic 1 Symbol ~ j Min \ Mix j Unit ~|
OFF CHARACTERISTICS
CoUector-Bkee Breakdown Volume
- 10 MAdc. lg * 0)
® v CBO
60
-
Vdc
CoUector-Eoutter Breakdown VolU«e*
Oc • 1 mAdc)
® V CEO*
40
-
Vdc
Eminer-Bkke Breakdown Voltagr
(1 E • 10 MAdc. lc ■ 0)
® V EBO
e
-
Vdc
Collector Cutoll Current
< V CE • *° v <*. v OB * 3 Vdc)
*cex
-
so
nAdc
Sue Cutoll Current
<V C£ - 40 Vdc. V OB • 3 Vdc)
*BL
-
so
nAdc
•Pvl.e Teet Pul&e Width 300 M»ec. Duty Cycle . 21 V QB Beer Emitter Revere* Bia«
Figure 8-1. Typical transistor data sheet
159
2 N 3903, 2 N 3904 (continued)
ELECTRICAL CHARACTERISTICS (continued)
| Chyefrrittk [Symbol | Min 1 Mm | Uwt 1
ON CHARACTERISTICS
DC Current Gain *
h FE*
_
Gc - 0.1 mAdc, Vq£ - 1 Vdc)
2N3903
20
—
2N3904
40
—
(1^ - 1.0 mAdc, V CE - 1 Vdc)
2N3903
33
_
2N3904
70
—
OC - 10 mAdc, V CE - 1 Vdc)
2N3903
50
150
2N3904
100
300
Gc - 50 mAdc, V CE - 1 Vdc)
2N3903
30
_
2N3904
30
—
Gc - 100 mAdc, V CE - 1 Vdc)
2N3003
13
—
2N3904
30
—
Collector* Emitter Saturation Voltage*
V CE(ut)*
Vdc
Gc - 10 mAdc, Ig “ 1 mAdc)
—
0.2
Gc - 50 mAdc, 1 B - 3 mAdc)
—
0.3
Bue- Emitter Saturation Voltage*
V BE(«at)*
Vdc
(lc - 10 mAdc, lg ■ 1 mAdc)
0.65
0.65
«C " 50 mAdc, 1 B - 5 mAdc)
—
0.93
SMALL SIGNAL CHARACTERISTICS
High Frequency Current Gain
2N3903
Kel
2.3
-
-
(IC - 10 mA, V CE - 20 V, 1 - 100 me)
2N3904
3.0
Current-Gain- Bandwidth Product
2N3903
t T
230
—
me
(l c = 10 mA, V CE * 30 V, 1 - 100 me)
2N3904
300
Output Capacitance
Cob
Pi
(V CB - 5 Vdc, I E - 0, 1 - 100 he)
4
Input Capacitance
c lb
Pi
(V 0B ■ 0.5 Vdc. lc - 0, 1 - 100 he)
_
e
Small Signal Current Gain
2N3903
h re
30
200
—
(Ic ■ 1.0 mA, V CE - 10 V, 1 * 1 he)
2N3904
100
400
Voltage Feedbach Ratio
2N3903
•Ve
0.1
5.0
X10' 4
Gc - 1.0 mA, V C£ - 10 V, 1 • 1 he)
2N3904
0.5
8.0
Input Impedance
2N3903
Ne
0.5
a
Kohma
Gc - 1.0 mA, V C£ * 10 V, 1- 1 he)
2N3904
1.0
10
Output Admittance
b oe
pmboa
Gc - 1.0 mA, V C£ - 10 V, i - 1 he)
Both Type*
1.0
40
Nolee Figure
NF
db
(1C - 100 |iA, V C£ ■ 5 V, R» • 1 Kohma,
Nolae Bandwidth • 10 epa to 13. 7 he)
2N3903
—
6
2N3904
—
5
SWITCHING CHARACTERISTICS
Delay Time
V C C “ 3 Vdc, V 0B - 0-3 Vdc,
lC - 10 mAdc, 1 B1 " 1 mA
l d
-
33
oaec
Rlae Time
*T
-
33
naec
Storage Time
Vcc - 3 Vdc lc ■ lOmAdc. “JJJ
I5I - Ig2 • 1 mAdc
175
200
naec
Fall Time
*r
-
50
nmec
•Pulae Teet: Pulse Width - 300 u«e c. Duty Cycle - 2% V QB - Bue Emitter Reveree BUj
Figure 8-1. (cont.)
160
TYPE 2N3055
N-P-N SINGLE-DIFFUSED MESA SILICON POWER TRANSISTOR
FOR POWER-AMPLIFIER APPLICATIONS
mechanical data
Alt JEOEC TO) DIMENSIONS AND NOTES ASE AteilCAHI
IMC COUECTO* IS IN ElECTIICAl CONIACT WITH THE CASE
si t-ct" r3»*
DIMENSIONS ARE IN INCHES
absolute maximum ratings at 25'C case temperoture (unless otherwise noted)
Collector-Base Voltage . ... 100 V
Collector-Emitter Voltage (See Nate 1) 70 V
Emitter-Bose Voltage ... . . .... 7 V
Continuous Collector Current , 1 j A
Continuous Base Current 7 ^
Continuous Device Dissipation at (or below) 25*C Cose Temperature (See Nolo 2) . . . . 115 W
Operating Cose Temperature Ronge -65*C to 200*C
Storage Temperature Range ~65*C to 200*C
lead Temperature Si Inch horn Case lor 10 Seconds 235*C
setts I. till nlo •*»!•*> wSm is. l a to* (1
t fc’.H iimwlf n Mt*( ran ai n< ran at 0 4S n/it%
‘electrical characteristics at 25‘C case temperature (unless otherwise noted)
f AN AMITE It
TEST CONDITIONS
MIN
MAX
UNIT
T|*jcio
CollNfor -Emitter Breakdown Voltage
lc 200 m». 1, - 0.
St. Not. 1
V
Tinicu
(olltrtor emitter Breakdown Yottogt
f e 200 m*. R. - 100 n
70
V
■cio
Collector Cutotf Currsnt
Vet 3 JO V. I, 0
07
m*
let*
Collector Cutoff (urrtnt
Vet 100 V, V« = -I S v
t
V c , = 100 V. V, -I.J ».
t c 110*C
)0
l|«o
Emitter Cutoll Current
V„ - 1 v. Ic o
I
mA
Static Forward (urrtnt Traniftr Ratio
Vd - «V. Ic 4A,
Sea Holt! J and 1
20
70
Tct ~fV. le 10 *.
Sta Nairn J ond 1
J
Va
Bait limtttf Valto^r
Vc. < V. Ic IS,
Sat Not.. ) ond 4
11
»
V Cilul|
Collector ( mitter Soturctron Valtogt
1, 100 mA, I c 4 A.
f, - J J A. I c 10 A.
Sat Netai J ond 4
Sat Natai J ond i
1 1
•
*
hi.
Small Signal (anrmon Emitter
forward Cuntnl Trontlir Rotio
Vet - * V. Ic 1 ».
1 1 kNt
It
120
U
Small- Signal (emman Emitter
Forward (urnnt Traniftr Rotio
Cutoff Frequency
Vc. « V. Ic 1 A.
Sea Not. 1
"
kN,
thermal characteristics
Figure 8-2. Data sheet for high power transistor. (Courtesy of Texas Instruments, Inc )
161
162
Transistor
Specifications and
Performance
usually followed by mechanical data in the form of an illustration showing
the package shape and dimensions, as well as indicating which leads are
collector, base, and emitter.
The absolute maximum ratings of the transistor at a temperature of
25 °C are listed next. These are the maximum voltages, currents, etc., that
the device can take without breaking down. It is very important that these
ratings never be exceeded; otherwise, failure of the device is quite possible.
For reliability, the maximum ratings should not even be approached. Also,
the maximum ratings must be adjusted downward for operation at tempera-
tures greater than 25 °C. Following the absolute maximum ratings, there is
normally a complete list of electrical characteristics for the device. Again,
these are specified at 25 °C, and allowances are necessary for variations of
temperature. A complete understanding of all the quantities specified on a
data sheet will not be achieved until circuit design is studied. Some of the
most important quantities are defined below. It is important to note that the
ratings of a given transistor are stated for specified circuit conditions. If these
conditions change, the ratings are no longer valid.
BV cb0 Collector-base breakdown voltage — dc breakdown voltage for
reverse-biased collector-base junction.
BV CE o Collector-emitter breakdown voltage — collector to emitter dc
breakdown voltage with base open circuited.
BV ebo Emitter-base breakdown voltage — emitter to base reverse-bias
dc breakdown voltage.
V BE Base-emitter voltage — dc voltage drop across forward-biased
base-emitter junction.
^C£(sat) Collector-emitter saturation voltage — collector to emitter volt-
age with device in saturation.
I CB o or Collector cutoff current — dc collector current with collector-
I c0 base junction reverse biased and emitter open circuited.
I CES Collector cutoff current — dc collector current with collector-
base junction reverse biased and base short circuited to emitter.
I CEO Collector cutoff current — dc collector current with collector-
base junction reverse biased and base open circuited.
I EBO or Emitter cutoff current — reverse-biased emitter-base dc current
I E0 with collector open circuited.
h FE Static forward current transfer ratio — common emitter ratio of
dc collector current and base current, h FE = I c Pb-
CU Common base output capacitance — measured between collector
and base.
C„ Common emitter output capacitance — measured between collec-
tor and emitter.
NF Noise figure — ratio of total noise output to total noise input
expressed as a decibel (dB) ratio (Section 8-4) for a specified
bandwidth and bias conditions. Defines the amount of noise
added by the device.
4 . or 4
fhfo OT fa t
Common emitter cutoff frequency — common emitter operating
frequency at which the device current gain falls to 0.707 of its
normal (mid-frequency) value.
Common base cutoff frequency — as above for common base.
Maximum Power Dissipation. Consider the data sheet for the
2N3903 and 2N3904 transistors, Fig. 8-1. The absolute maximum ratings at
25°C free air temperature show that the collector-emitter voltage should not
exceed 40 V, and that the collector current should not exceed 200 mA. The
total device dissipation of 310 mW at a maximum free air temperature of
25°C means that ( I c ) must not exceed 310 mW. For example, if the
maximum I c of 200 mA is to be employed, then maximum VcE should be
(310 mW)/(200 mA)= 1.55 V. It is important to note that if the free air
temperature is greater than 25 °C, then the device maximum power dissipa-
tion must be reduced.
A 2N3904 transistor is employed in a circuit in which its V CE will be 20
V. The circuit is to be operated at a free air temperature of 125°C.
Determine the maximum value of I c that can be used.
solution
From the data sheet for the 2N3904, the 310 mW maximum power dissipa-
tion must be derated linearly at 2.81 mW/°C for temperatures greater than
25° C.
Free air temperature for circuit = 125°C.
° C in excess of 25°C= 125 - 25 = 100°C.
Device must be derated by (2.81 mW/° C)X(100°C)«281 mW.
Maximum device dissipation at 125°C,
/ > = 310 mW — 281 mYV= 29 mW
The device dissipation is V CE X l c . Thus,
20FX/ Wm „ ) -29m\V
29 mW
20 V
1 .45 mA
163
Power
Dissipation
8-3
Power
Dissipation
Example 8-1
164
Transistor
Specifications and
Performance
Example 8-2
Maximum Power-Dissipation Curve. For power transistors it is sometimes
necessary to draw a maximum power- dissipation curve on the output characteris-
tics. To draw this curve, the greatest power that may be dissipated at the
highest temperature at which the device is to be operated is first calculated.
Then using convenient collector-emitter voltage levels, the corresponding
collector current levels are calculated for the maximum power dissipation.
Using these current and voltage levels, the curve is plotted on the device
characteristics.
Assuming that the device characteristics given in Fig. 8-3 are for a
2N3055 transistor, plot a maximum power-dissipation curve for a case
temperature of 78°C.
solution
Case temperature for device = 78°C.
° C in excess of 25°C = 78-25 = 53°C.
Device must be derated by 0.66 W/° CX53°C = 35 W.
Maximum device dissipation at 78°C=115 W — 35 W = 80 W.
F*d = V ce ^ h
Figure 8-3. Transistor maximum power-dissipation curve.
or
When V CE = 60 V, / c = 80 W/60 V=1.3 A.
Plot point 1 on the characteristics at V CE = 60 V, I c
= 1.3 A.
When V CE — 40 V,
80
7 ‘=40= 2A
Point 2
When V CE = 20 V,
/ =^-4A
' c 20 4A
Point 3
When V CE =\0 V,
/ = E= 8a
c 10
Point 4
Now draw a curve through the above points to obtain the maximum
power-dissipation curve. The transistor voltage and current conditions must
at all times be maintained in the portion of the characteristics below the
maximum power-dissipation curve.
165
Decibels
and
Frequency
Response
Decibels. When the output power of an amplifier changes from P { to
P 2 , the power change is expressed as the log of their ratio:
Power change = log 10 | j
= 10 log,
(bels)
|~j decibels (dB)
( 8 - 1 )
8-4
Decibels
and
Frequency
Response
Thus, the decibel is a unit of power change.
The output power dissipated in a load resistance is
P =
Yl
Power change = 10 log 10
W*L
dB
”10 log, o
£
l 7 .
2
dB
20 log
Yl
V.
dB
(8-2)
Also,
166
Transistor
Specifications and
Performance
Example 8-3
Example 8-4
Power change = 101og 10
Q*l
dB
= 201og 10
dB
(8-3)
By means of Eqs. (8-2) and (8-3), power changes can be calculated in
decibels using either voltage ratios or current ratios.
The output power from an amplifier is 50 mW when the signal
frequency is 5 kHz. When the frequency is increased to 20 kHz, the output
power falls to 25 mW. Calculate the decibel change in output power.
solution
From Eq. (8-1),
Power change = 101og, 0
£t
p,
dB
[ 25 mW I
=101 o Mm^J
= 101 °gio[ 0 - 5 ]
= — 101og„[2]
= -10(0.3) = -3dB
The output voltage of an amplifier is measured as 1 V at 5 kHz and
0.707 V at 20 kHz. Calculate the decibel change in output power.
solution
From Eq. (8-2),
Power change = 201og 10
= 201og lo
1 2
0.707
dB
M]
— ““•"[aw]
= -20 log 10 [ 1.414]
= -20(0.15) = — 3 dB
It is seen from Examples 8-3 and 8-4 that the output power of an
amplifier is reduced by 3 dB when the measured power falls to half its
normal level, or when the measured voltage falls to 0.707 of its normal level.
Frequency Response. Figure 8-4 shows a typical graph of amplifier output
voltage or power plotted versus frequency. It is found that the output
normally remains constant over a middle range of frequencies and falls off at
low and high frequencies, due to the effects explained below. The gain over
this middle range is termed the mid-frequency gain. The low' frequency and
high frequency at which the gain falls by 3 dB are designated f x and / 2 ,
respectively. This is normally considered the useful range of operating
frequency for the amplifier, and the frequency difference (y* 2 — /j) is termed
the amplifier bandwidth ( B ).
Frequencies /, and / 2 are sometimes termed the half- power or 3-dB
points. This is because, as shown in Example 8-3, the power output is — 3 dB
from its normal level when P 2 is half P x . When the amplifier output is
expressed as a voltage on the graph of frequency response, the 3-dB points
(/, and / 2 ) occur when V 2 is 0.707 V r This is shown in Example 8-4.
The fall off in amplifier gain at low frequency is due to the effect of
coupling and bypass capacitors. Recall that the impedance of a capacitor is
X c = 1 /(2fl/C). At medium and high frequencies, the factor / makes X e very
small, so that all coupling and bypass capacitors behave as short circuits. At
low frequencies, X { increases and some of the signal voltage is potentially
divided across the capacitors [see Fig. 8-5(a)]. As the signal frequency gets
lower, the capacitor impedances increase and the circuit gain continues to
fall.
All transistors have capacitances between their terminals (Section 4-8).
As shown in Fig. 8-5(b), there are also stray capacitances (CJ, which are the
capacitances between connecting wires and ground. All these capacitances
are very small, so that at low and medium frequencies their impedances are
very high. As frequency increases, the impedance of the stray capacitances
falls. When these impedances become small enough, they begin to shunt
167
Decibels
and
Frequency
Response
Figure 8-4. Typical amplifier frequency response.
168
Transistor
Specifications and
Performance
(a) Loss of signal voltage across coupling
and bypass capacitors at low frequency
Vs
Portion of l 0
lost via stray
capacitance
(b) Loss of output current via stray
capacitance at high frequency
Figure 8-5. Effect of stray capacitances on amplifier gain.
away some of the input and output currents and thus reduce the circuit gain.
As the frequency gets higher and higher, the circuit gain continues to fall
until it becomes too small to be useful. It can be shown that the upper 3-dB
point for the amplifier can occur when the reactance of the stray capaci-
tance is equal to the load resistance value.
Even if no external stray capacitances were present, the device internal
capacitances, and the transit time of charge carriers across the transistor
junctions and through the semiconductor material, limit the circuit
frequency response. This limitation is expressed as a cutoff frequency f a , which
is the frequency at which the transistor current gain falls to 0.707 of its gain
at low and medium frequencies. The cutoff frequency can be expressed in
two ways, the common emitter cutoff frequency (f a f) or the common base cutoff
frequency (f a f)<f at is the frequency at which the common emitter current gain
(h f( ) falls to 0.707 X (mid-frequency h /( ). f ab is the frequency at which the
common base current gain (h^) falls to 0.707 X (mid-frequency h ^). It can be
shown that
169
Decibels
and
Frequency
Response
(a- 4 )
For maximum bandwidth the stray capacitance should be kept to a
minimum. Also f a should be several times greater than the signal frequency
(/) at which the reactance of the stray capacitance equals the amplifier load
resistance.
A transistor with/, A = 5 MHz and hj t = 50 is employed in a common
emitter amplifier. The stray capacitance at the output terminal is measured
as 100 pF. Determine the upper 3-dB point (a) when R L = 10 kS2 and (b)
when R l = 100 k£2.
solution
(a) R l = 10 ktt. From Eq. (8-4),
The stray capacitance reduces the amplifier gain by 3 dB when
1
2 trfC,
= /?£ = 1 0 ktt
1
1
2 itC s R L 2t r X 100X 10 _,2 X 10X 10 3
E 159 kHz
Since / a# </„/ 2 =/ a< = 100 kHz.
(b) R l = 100 kU.
1
2 irC t R L 2?rX 100 X 10" 12 X 100 X 10 3
s 15.9 kHz
Example 8-5
Since/, </ a ,,/ 2 =/,= 15.9 kHz.
8-5
Miller
Effect
In Example 8-5 it is assumed that the transistor internal capacitances
are very much smaller than the (external) stray capacitance. The internal
capacitances can be very important, however, and, as will be shown, they
tend to have their greatest effect at the input terminals of the transistor.
Figure 8-5(b) shows that a collector-base capacitance (C (b ) and a
base-emitter capacitance (C u ) exist between the transistor terminals.
Assume that an input signal ( -1- Fj) is applied to the base of the transistor
shown in Fig. 8-5(b). If the circuit voltage amplification is A 0 , then the
collector voltage change is
AV c =-A v XV,
Note that because of the phase shift between input and output, the
collector voltage is reduced by (A 0 X F') when the base voltage is increased by
V t . This results in a total collector-base voltage reduction of
LVcB-Vi + AM
- w+4)
Since C cb is the capacitance between collector and base, the voltage
across C cb is also changed by A V CB . Using the formula Q= C X A F, it is found
that the charge supplied to the input of the circuit is
Q=C a XV,(l+A)
or
Q=(l+A,)C, t XV t
Thus, the collector-base capacitance appears to be (1 + Af)C cb ; i.e., the
capacitance is amplified by a factor of (1 +A V ). This is known as the Miller
effect.
The total input capacitance (C in ) to the transistor is (\+A v )C cb in
parallel with C^:
C in =C b* + 0 +A ,) C cb C 8 * 5 )
At high frequencies, the value of C in reduces the input impedance of
the circuit and affects the frequency response.
Example 8-6
A transistor used in a common emitter circuit has hj t — 75, h u = 2 k£2,
C eb = 4 pF, and = 10 pF. If the circuit load resistance is 5 k£2, calculate the
value of C^.
170
solution
From Eq. (6-6),
*fi*L
7 5X5 k fl
2kfi
171
Transistor
Circuit
Noise
From Eq. (8-5),
C in = 10 pF + (l + 188)4 pF
= 10 pF + 756 pF = 766 pF
Unwanted signals at the output of an electronics system' are termed
noise. The noise amplitude may be large enough to swamp the wanted
signals; consequently, the noise level dictates the minimum signal amplitude
that can be handled. Noise originates as atmospheric noise from outside the
system and as circuit noise generated within resistors and devices.
Consider a conductive material at room temperature. The motion of
free electrons drifting around within the material constitutes a flow of many
tiny random electric currents. These currents cause minute voltage drops,
which appear across the ends (or terminals) of the material. Because the
number of free electrons available and the random motion of the electrons
are both increased as temperature rises, the generated voltage amplitude is
proportional to temperature. This unwanted, randomly varying voltage is
termed thermal noise.
Thermal noise is generated within resistors, and when the resistors are
at the input stage of an amplifier, the noise is amplified and produced as an
output. Noise from other resistors is not amplified as much as that from the
resistors right at the input; consequently, only the input stage resistors need
be considered in noise calculations.
Noise is also generated within a transistor, and again the input stage
transistor is the most important because its noise is amplified more than that
from any other stage.
Since thermal noise is an alternating quantity, its rms output level
from any amplifier is dependant upon the bandwidth of the amplifier. It can
be shown that the rms noise voltage generated in a resistance is
8-6
Transistor
Circuit
Noise
e H = V4 kTBR (8-6)
where k = Boltzmann’s constant = 1.374 X 10 _23 J/K
(i.e., joules per degree Kelvin)
T= absolute temperature
R = resistance in ohms
B = circuit bandwidth
172
Transistor
Specifications and
Performance
Consider the circuit of Fig. 8-6(a). R x and R 2 are bias resistances; e s is a
signal voltage with source resistance R s . The total noise generating resistance
in parallel with the amplifier input terminal is
* c =/y (*.ii*>)
In the noise equivalent circuit, Fig. 8-6(b), e n is the noise voltage
generated by R G . It is also seen from Fig. 8-6(b) that if the amplifier input
resistance is /?, then the noise voltage is potentially divided, so that
e m = e n X
R t
r,+r g
( 8 - 7 )
If the amplifier voltage gain is A v , the output noise due to R c is
n = A„
( 8 - 8 )
(b) ac equivalent input
circuit for noise
Figure 8-6. Amplifier and equivalent input circuit for noise.
173
Transistor
Circuit
Noise
To specify the amount of noise produced by a transistor, manufac-
turers usually quote a noise figure ( NF ). To arrive at this figure, the transistor
noise output is measured under specified bias conditions, and with a speci-
fied source resistor, temperature, and noise bandwidth.
The noise figure defines the amount of noise added by the transistor to
the noise generated by the specified resistance ( R c ) at the input. Note that
R c is the combined bias and signal source resistances, as seen from the
amplifier input.
The noise for a 2N4104 transistor is specified as follows:
At 25°C free air temperature
And for a load resistance R Lt the noise output power due to R c i
P * R,
(8-9)
Parameter
Test Conditions
Mm Max
NF
spot noise
figure
V CE = 5 V,/ c - 30/4A,
F c =10kC2,/=10Hz
15dB
V c£ = 5 V,/ c = 30 pA,
F c = 10 kfi,/= 100 Hz
4dB
V CE = 5 V,/ c = 5/iA,
R c ~ 50 ktt,/= 1 kHz
ldB
^^V,/ c = 5/iA,
R c = 50 kfl,/ = 10 kHz
ldB
The fact that NF is defined as a spot noise figure means that the noise
has been measured for a bandwidth of 1 Hz. The bias conditions are
specified because the transistor noise can be affected by ^CE and I c .
The noise factor , F, is the total circuit noise power output divided by
noise output power from source resistor. The noise figure NF is the decibel
value of F.
NF= 101og 10 F (8-10)
If the transistor were completely noiseless,
total noise output power = noise output power due to R G
or
NF= 101og 10
noise power from source resistor
noise power from source resistor
=*0dB
174
Transistor
Specifications and
Performance
Example 8-7
Obviously, the smallest possible noise figure is the most desirable. If the
circuit in which the transistor is employed does not have the value of source
resistance and the bias conditions specified, then the specified noise figure
does not apply. In this case the noise figures can still be used to compare
transistors, but for accurate estimations of noise a new measurement of noise
figure must be made.
The total noise output power due to R c and the input transistor is
p N -( noise factor X P n )
( 8 - 11 )
An amplifier with B~ 1 to 10 kHz, /?, = 25 kS2, and R c = 50 kfi uses a
2N4104 as the input transistor. The transistor bias conditions are I c = 5 juA
and and the amplifier has a voltage gain of 30. Calculate the
output noise amplitude at 25 °C.
solution
From the 2N4104 specification, for K r/r = 5 V, I r = 5 uA, R r = 50 kfi, and
/= 1 to 10 kHz, NF= \dB.
From Eq. (8-10), NF= 10 log 10 F:
Noise factor F— antilog -yyy
ldB
= analog
= 1.26
From Eq. (8-6),
*„= V4* TBR g
k~ 1.37X 10“ 23
T=25°C = (273 + 25) K [i.e., 298 K (degrees Kelvin)]
B= 1 to 10 kHz = 9 kHz
R g = 50 kS2
*„= V4X1.37x10~ 23 X298X9X10 3 x 50X10 3
= 2.7 jLtV
From Eq. (8-7),
Pi + Pc
2,7/lVX 25 kft + 50 kfi
= 0.9 /iV
From Eq. (8-8),
e no ~ A V X e m = 30 X 0.9 fiV = 27 fiV
175
Transistor
Switching
From Eq. (8-11),
1.26 X
(27 mV)
Rl
2
and F rt 2 //? £ , where F n = total rms noise output voltage:
V 2
t= L26x
(27 >.V)
2
f; = ^1.26X(27 m V) 2 = 30.3 mV
Transistor as a Switch. When a transistor is used as a switch, it is
either biased off or biased on to its maximum possible collector current level.
Figure 8-7 illustrates the two conditions. In Fig. 8-7(a) the base input
voltage polarity is such that the transistor is biased off. In this case, the only
current flowing is the collector base leakage current I co (sometimes designated
Icbo)‘
V CE ~ ^CC “
At cutoff
^CE = ^CC - Ico Rl ~ ^cc
In Fig. 8-7(b), V B biases the transistor on to the maximum possible I c
level. I c is limited only by V cc , R L > and the minimum possible voltage across
the transistor.
8-7
Transistor
Switching
Figure 8-7. Transistor switching circuit.
176
Transistor
Specifications and
Performance
IrR,
V CE~ Vcc IcRjL
Therefore,
Now consider the output characteristics and dc load line for the circuit
of Fig. 8-7. This is shown in Fig. 8-8 and is drawn by the usual process of
plotting point A at I c = 0 and Vce=V cc , and point B at V C E = 0 and
7 C = V cc / R l . When 1 B = 0, / c = / C o> and the transistor is said to be cut off.
The region of the characteristics below I B = 0 is termed the cutoff region.
When I B is a maximum, V CE = V CE (sat) , and the transistor is said to be
saturated. The region of the characteristics to the left of T C£ . (sat j is termed the
saturation region. The region between saturation and cutoff is the active region
in which a transistor is biased for amplification. ^C£(sat) is the minimum
possible collector-emitter voltage for the device, and is referred to as the
transistor saturation voltage. It is seen that F C£(sat) is dependent upon the I c
level. For the 2-kl2 load line shown as the broken line in Fig. 8-8, T C£ . (sat j is
smaller than for R L = 1 k£2.
Figure 8-8. Characteristics and load line for transistor switch.
The circuit of Fig. 8-7 uses a 2N3904. transistor and has ^=10 V
and R l = 1 kft. Determine the value of ^CE when the transistor is (a) cut off
and (b) saturated.
solution
(a) At cut-off I c = I co . From the Off Characteristics section of the 2N3904 data
sheet in Fig. 8-1, the collector cutoff current is 7 co = fcEX = ^® n A maximum.
(Note that l CEX is the collector cutoff current for a specified bias and supply voltage.)
V CE = ^CC ~ IcO^L
= 10 V-(50 nAXl kO)
= 10 V-50 jtiV = 9.99995 V
(b) At saturation
V CE ~0
V C c ~ Ic^L
and
v cc
Rl ''
10 V
: 1 kfi
= 10 mA
From the 2N3904 data sheet F C£(Mt) = 0.2 V max at I c = 10 mA.
F C£ <0.2 V
Example 8-8
K C£ ( ut ) is typically around 0.2 V for a silicon transistor, while ^ BE is
typically 0.7 V. Consider the circuit in Fig. 8-7(b) once again. If ^£. = 0.7 V
and v ce ~ 0-2 V, then the transistor base is 0.5 V more positive than the
collector. This means that the collector- base junction, which is usually
reverse biased, is in fact forward biased when the transistor is in saturation.
With the collector-base junction forward biased, fewer charge carriers from
the emitter are drawn across to the collector, and the device current gain is
lower than normal. For saturation to occur, the transistor must have a
certain minimum value of h FE , which depends upon the particular circuit
conditions.
In Example 8-8, R B = 2.7 k£2, V BE = 0.7 V, and f / £ = 2 V. (a) Calculate Example 8-9
the minimum h FE for saturation, (b) If V 8 is changed to 1 V, and the
transistor minimum h FE is specified as 50, will the transistor be saturated?
177
178
Transistor
Specifications and
Performance
solution (a)
I c has already been calculated as 10 mA.
The voltage across R B is ( V B — V BE ):
, V B -V BE 2 V— 0.7 V
Ib ~ R b = 2.7 kSJ = 0 481mA
l c 10 mA
hpE 1 B 0.482 mA 2 °' 8
Thus, A F£(min) for the transistor must be at least 20.8 for saturation to occur.
solution (b)
, Vb- v B e 1-0.7 A
R b 2.7kfi _0IllmA
I c = hpE = 50X0.1 11 mA = 5.55 mA
Since I c is required to be 10 mA for saturation, the device will not be
saturated.
Glossary of
Important
Terms
Switching Speed. Another important characteristic of a switching transis-
tor is its operating speed. Consider Fig. 8-9. When the base input current is
applied, the transistor does not switch on immediately. This is because of the
junction capacitance and the transit time of electrons across the junctions.
The time between the application of the input pulse and the commencement
of collector current flow is termed the delay time (t d ) (Fig. 8-9). Even when
the transistor begins to switch on, a finite time elapses before I c reaches its
maximum level. This quantity is known as the rise time ( t r ). The rise time is
specified as the time required for I c to go from 10% to 90% of its maximum
level. The turn-on time ( t on ) is the sum of t r and t d . (See Fig. 8-9). Similarly,
when the input pulse is removed, I c does not go to zero until after a turn-off
time (t 0 ff ), made up of a storage time (t s ) and a fall time (tf).
The fall time is specified as the time required for I c to go from 90% to
10% of its maximum level. The storage time is the result of charge carriers
being trapped in the depletion region when a junction polarity is reversed.
When a transistor is in saturation, both the collector-base and emitter-base
junctions are forward biased. At switchoff, both junctions are reverse biased,
and before I c begins to fall the stored charge carriers must be withdrawn or
made to recombine with opposite-type charge carriers. For a fast-switching
transistor, t on and t of{ must be of the order of nanoseconds.
Decibel (dB). Unit of power change: power change= 101og(/ > 1 / P 2 ) dB.
Half-power points (f x and ff). Low and high frequencies at which an
amplifier output power is half its mid-frequency output power. Also,
179
Glossary of
Important
Terms
the frequencies at which an amplifier output voltage is 0.707 of its
mid-frequency output voltage.
Bandwidth ( B ). Difference between half-power points. Zf = (/ 2 — /,).
Common emitter cutoff frequency {J h j. or f a ^. The high frequency at
which a transistor hj t falls to 0.707 X (mid-frequency hj t ).
Common base cutoff frequency or f^). The high frequency at which
a transistor h ^ falls to 0.707 X (mid-frequency h ^).
Miller effect. Amplification of device input capacitance.
Noise. Unwanted signals at the output of an electronic system.
Thermal noise. Temperature-dependent noise generated within resistances
and semiconductor bulk material.
Noise factor (/’). (Total noise output power)/(noise output power from
source resistance).
Noise figure (AF). Decibel value of noise factor.
Cutoff region. Region of transistor common emitter characteristics below
/*- 0.
Saturation region. Region of transistor common emitter characteristics
between V CE = V CE(tMt) and V CE = 0.
Active region. Region of transistor characteristics between saturation and
cutoff.
180
Transistor
Specifications and
Performance
Review
Questions
Problems
Saturation voltage ( V C E^ t) )- Level of Vce when the voltage drop across R L
is so large that the transistor collector-base junction is forward biased.
Delay time ( t d ). Time between application of input pulse and commence-
ment of transistor collector current.
Rise time (f r ). Time required for I c to go from 10% to 90% of its maximum
level.
Turn-on time ( t on ). Sum of t T and t d .
Storage time (f f ). Time between removal of input pulse and commence-
ment of I c decrease.
Fall time (tj). Time required for I c to go from 90% to 10% of its maximum
level.
Turn-off time (* o££ ). Sum of t s and t f .
8-1. List and define the most important quantities specified on a transistor
data sheet for (a) small-signal transistors, (b) high-power transistors,
(c) switching transistors, (d) high-frequency transistors.
8-2. Derive the equations which are employed to calculate power change
at the output of an amplifier, using power, voltage, and current
ratios.
8-3. Explain why the output power of an amplifier falls at low and high
frequencies. Sketch the typical graph of amplifier frequency response,
and identify the important points on the graph.
8-4. Discuss Miller effect and derive an equation for amplifier input capaci-
tance.
8-5. Explain thermal noise , and discuss the various sources of noise which
occur within a transistor circuit. Identify the most important noise
sources, and explain why they are important. Define noise figure and
noise factor for a transistor.
8-6. Sketch typical output characteristics and dc load line for a transistor
used as a switch. Identify the various regions of the characteristics,
and briefly explain. Explain the importance of I co and T C£(sat) .
8-7. Sketch the waveforms of input and output currents for a switching
transistor. Show the various switching times involved and explain the
origin of each.
8-1. (a) A 2N3904 transistor is required to dissipate 200 mW of power.
Calculate the maximum free air temperature at which it can operate,
(b) If the device is to be operated at a maximum free air temperature of
80 °C and is to have a collector current of 2 mA, determine the
minimum level of V CE that may be employed.
8-2.(a)A 2N3055 transistor is to be operated at a maximum case tempera-
ture of 125°C. Using the output characteristics in Fig. 8-2, draw the
maximum power dissipation curve for the device at this temperature.
(b) For the T = 78°C curve shown on Fig. 8-3, draw the dc load line for
the smallest possible value of R L when the circuit supply voltage is 50
V. Determine the value of
8-3. The output power from an amplifier is 100 mW when the signal
frequency is 1 kHz. When the signal frequency is increased to 25
kHz, the output power falls to 75 mW. Calculate the decibel change
in output power.
8-4. The output voltage of an amplifier is 2 V when the signal frequency
is 1 kHz. Calculate the new level of output voltage when it has fallen
by 4 dB.
8-5. A transistor employed in an amplifier has hj e = 75 and =12 MHz.
Stray capacitance at the amplifier output terminal is 100 pF. De-
termine the upper 3-dB point (a) when R L =5 k£2, (b) when R L = 20
kfi.
8-6. The transistor referred to in Problem 8-5 is connected as an amplifier
with R l = 15 kft. The upper 3-dB frequency of the amplifier is found
to be / 2 =7 5 kHz. Calculate the value of stray capacitance at the
transistor collector terminal.
8-7. The input capacitance of a common emitter circuit is measured as
800 pF. The load resistance of the circuit is 7 k ft, and the transistor
parameters are hj e — 60, h u = 1.5 k ft. If the base-emitter capacitance is
15 pF, calculate the value of collector- base capacitance.
8-8. A transistor with h /e = 100, h u — 2.2 kft, C c(> = 3 pF, and C^ = 8 pF is
connected as an amplifier with R L = 6.8 kft. Calculate the value of
the amplifier input capacitance C in . Also calculate the new' value of
C in when a 100-pF capacitor is connected (a) between emitter and
base, (b) between collector and base, (c) between collector and
emitter.
8-9. An amplifier which uses a 2N4104 transistor at the input has lower
and upper 3-dB points at 2 kHz and 10 kHz, respectively. The
transistor bias conditions are F C£ .=5 V and / c «=5 jliA, and the
amplifier voltage gain is 40. Calculate the noise output voltage at
25°C if R c = 50 kft and /?, = 10 kft.
8-10. A transistor amplifier with A v = 100, j9=15kH 7 and 7? ( = 12kft has
input bias resistors equivalent to R G — 33 kft. If the maximum noise
voltage at the output is not to exceed 100 juV rms, determine the
largest noise figure for the input transistor.
8-11. A 2N3904 transistor employed as a switch has 1^ = 25 V and
R l = 2.7 kft. Calculate the value of Vca when the transistor is (a) cut
off, (b) saturated.
8-12. A transistor switching circuit arranged as in Fig. 8-7 has R L =* 2.7 kft,
V cc = 25 V, R b - 4.7 kft, F fl =1.6 V, and F^-0.3 V. (a) Calculate
the minimum transistor h FE for saturation, (b) If R L is changed to I
kft and h FE is specified as 40 minimum, will the transistor be
saturated?
181
Problems
CHAPTER
9
9-1
Introduction
Basic Multistage
and integrated
Circuit Amplifiers
An amplifier may be classified according to the function it performs,
the frequency range over which it operates, the coupling method between
stages, or how the output transistors are biased.
A small- signal amplifier, also known as a preamplifier, performs the
function of amplifying small voltage signals. A power amplifier, or large signal
amplifier, accepts relatively large input voltages, and drives an output current
through a low-impedance load. Audio frequency, intermediate frequency, high
frequency, radio frequency, and video are prefixes employed to identify amplifiers
designed for a particular frequency range.
A dc amplifier can amplify dc or steady-state input voltages. Most
integrated circuit amplifiers are dc amplifiers; they also generally have
differential amplifier input stages. The differential amplifier has two input
terminals and does not employ any bypass capacitors.
Many IC amplifiers are known as operational amplifiers. This means that
they have very high internal gain, high input impedance, low output
impedance, two input terminals, and one output terminal.
182
Amplifiers may be described as direct coupled , capacitor coupled , or trans- 183
former coupled , indicating the interstage coupling method. C Coupled
Audio power amplifiers are classified as class A (output transistors Two-Stage
biased to give V cc )> class B, (output transistors biased at cutoff), and Circuit
class AB, (output transistors partially biased on). Circuit efficiency and lack
of output distortion are prime considerations with audio power amplifiers.
In Section 6-8 a capacitor-coupled two-stage amplifier is ac analyzed
to determine the circuit gains and impedances. Each stage of that circuit is a
simple fixed-current bias common-emitter arrangement. Figure 9-1 shows
two capacitor-coupled emitter-current biased stages. This circuit functions in
the same way as the circuit in Fig. 6-15; an ac input signal is amplified by
the first stage, and then further amplified by the second stage. The proce-
dure for ac analysis of the circuit is similar to that in example 6-6.
9-2
Capacitor-
Coupled
Two-Stage
Circuit
Design Approach. When designing any amplifier, it is necessary to work to
a specification which might state supply voltage, amplifier gain, frequency
response, signal source impedance, and load impedance.
Obviously, each stage of the amplifier must be designed to operate
satisfactorily from the available supply voltage. Designing for a particular
value of voltage gain normally requires the use of negative feedback to stabilize
the gain. The use of an unbypassed emitter resistor, as discussed in Section
6-3, is one method of providing negative feedback. Equation (6-7) shows
that, in this case, the stage gain is stabilized at R L )/ R E - The circuit
in Fig. 9-1 has no provision for negative feedback; thus, it is designed to
achieve the largest possible voltage gain.
Figure 9-1. Two-stage capacitor-coupled amplifier
184
Basic
Multistage
and
Integrated
Circuit
Amplifiers
The simplest approach to the design of a two-stage amplifier (such as
in Fig. 9-1) is to make each stage identical. Then, when stage 2 has been
designed, the stage 1 components are selected as R l — R 5y R 2 — R 6 , R 3 — R 7 ,
R 4 = R 8 , C 2 = C 4 , and C x = C 3 .
R l and R e Selection. From Eq. (6-6), the voltage gain of each stage is
Since A v ccR Ly designing for the largest voltage gain normally requires the
selection of the largest possible values of R L (i.e., R 3 and R 7 in Fig. 9-1).
The collector current for each transistor might be selected to give the
greatest h fe value, again to achieve greatest A v . However, a large collector
current results in a small value of R L (for a given value of *V), and so a
large value of I c may actually give a lower voltage gain, even though h fe may
be relatively large.
For a given level of Io the largest possible voltage drop Vrl (in Fig.
9-2) gives the greatest value of collector load resistor:
Therefore, to make Vrl large, V E and Vce should be held to a minimum.
The collector-emitter voltage should typically be at least 3 V to ensure that
the device is operating in its active region. This allows a maximum output
swing of about ±1 V, which is usually adequate for a small-signal amplifier.
For good bias stability the voltage drop ( V E ) across the emitter resistors
should be much larger than the transistor base-emitter voltage ( V BE ). That
Figure 9-2. Currents and voltages in common emitter circuit.
This is because V E — V B — V BE (see Fig. 9-2), and when V E ^> V BE , any
variation in ^be (due to temperature change or other effects) has only a
slight effect upon V E . Thus, the emitter current and collector current remain
fairly stable at
185
Capaotor-
Coupled
Two-Stage
Circuit
Once V E and V C E are decided, V RL can be determined:
Vhl-Vcc~Vce~V e
Then R L and R E are calculated:
V RL V E
r l =~t and R s**-r
*c J c
Bias Resistors. In Section 5-5 it is explained that the potential divider
resistors (/?, and R 2 in Fig. 9-2) should be made as small as possible for good
bias stability. The rule-of-thumb suggested there was to let the potential
divider current (/ 2 in Fig. 9-2) be equal to the transistor collector current.
However, in the circuit in Fig. 9-1, the second-stage bias resistors R b and R 6
also affect the input impedance of stage 2 and constitute a load capacitor
coupled to stage 1. This reduces the total load resistance at the collector of
stage 1, and because A v <xR Lt the gain of stage 1 is reduced.
It is seen that, to give the largest possible stage 1 gain, R b and R 6
should be selected as large as possible. The two conflicting requirements are
(1) bias resistors as small as possible for good bias stability, and (2) bias
resistors as large as possible for high input impedance and good first-stage
gain. A reasonable compromise is achieved by selecting the potential divider
current as / 2 »/ c /l0. This keeps / 2 »/ B while also resulting in fairly large
values of potential divider resistors.
Capacitors. The coupling and bypass capacitors should be chosen to have
the smallest possible capacitance value. This is both for economy (large
capacitance values are more expensive) and to minimize the physical size of
the circuit. Since each capacitor has its highest impedance at the lowest
operating frequency, the capacitor values are calculated at the lowest signal
frequency that the circuit has to amplify.
The circuit low 3-dB frequency (/,) is determined by the bypass
capacitors (C 2 and C 4 in Fig. 9-1). Using Eqs. (6-6) and (6-7), it can be
shown that the low 3-dB frequency for each stage occurs when the bypass
capacitor has a value of
186
Basic
Multistage
and
Integrated
Circuit
Amplifiers
Example 9-1
or
Substituting
‘ 1 + */,
X = \(2 nfC),
(9-1)
When Eq. (9-1) is employed to calculate C 2 and C 4 in Fig. 9-1, it is
found that at f x each stage gain is 3 dB below its mid-frequency gain. This
means that at/j the overall amplifier gain is 6 dB below its mid-frequency
value. For a 3-dB reduction in overall gain at /,, the bypass capacitors must
be calculated to give a 1.5-dB reduction in each stage gain. The equation for
the bypass capacitors now becomes
1 + h /<
' E= 257(0.65/, )A„
(9-2)
The coupling capacitors should have very little effect on the overall
amplifier gain at the low'est signal frequency. To achieve this, the impedance
of each coupling capacitor is made equal to one tenth of the load impedance
in series with it:
i _ z;
2 mf x C 10
giving
Q =
10
2 */,z;
(9-3)
Design a two-stage, capacitor-coupled, small-signal amplifier (as in
Fig. 9-1) to meet the following specification. Supply voltage V cc = 1 8 V,
lowest operating frequency /, = 100 Hz, and voltage gain A v is as large as
possible. Use 2N3904 transistors (data sheet in Fig. 8-1), and make I c —
1 mA.
solution
Design stage 2 first and refer to the components as numbered in Fig. 9-1.
For good bias stability,
*'«.»(>'«£ -0.7 V)
Take ^«5V.
For maximum let V CE = 3 V:
V R1 = 18V — 5V — 3V
= 10 V
„ _Vri _ 10 V
* 7 “ I c ~ 1mA
= 10 kQ (this is a standard resistor value;
see Appendix 1 )
1 mA
(use a 4.7-kfl standard value)
8 /
l C
= 5 kfl
187
Capacitor-
Coupled
Two- Stage
Circuit
VR 8 now becomes
I c XR 6 =\ mA X 4.7 kfl = 4.7V
and
V B = V BE + ^8 = 0-7 V 4-4.7 V = 5.4 V
Let
*6 =
/ c= lmA
6 10 10
V B _ 5.4 V
I c 100 ^lA
= 100 /iA
= 54 kfi (use a 47-kfl standard value)
I 6 now becomes
Vr
*6
5.4 V
47 kG
1 15 \xA
Referring to the 2N3904 data sheet in Fig. 8-1:
At 7 C = 1 mA, h FE(atin) = 70 and
lc
^FEX min)
1 mA
70
14 \i\
188
Basic
Multistage
and
Integrated
Circuit
Amplifiers
V Rb = V cc - V R6 = 18 V — 5.4 V= 12.6 V
and
R V ** - 12>6V
5 I 6 + I B 115 jtiA + 14 jiA
?«98 k£2 (use 100 k£2, the next higher standard
value)
From Eq. (9-2),
c«-
1
257 ( 0 . 65 /,)^
From the 2N3904 data sheet,
h fe = 100 and h it = 1 kft
i + ioo
4 277(0.65 X 100 Hz)l k£2
= 247 fiF (use 250-juF standard value;
see Appendix 2)
Z; = tf 5 ||/? 6 || h u = 100 k£2||56 kfl|| 1 kfl = 973
From Eq. (9-3),
' 3 2 77/, X Z[
= 10
277X 100 Hz X 973 Q
= 16 jliF (use 18-juF standard value)
For the first stage , 7?, = 7? 5 =100 kfl, R 2 = R 6 = 56 kS2, R 3 = R 7 = 6. 8 kfl, R 4 =
R e = 4.7 kfl, C 2 =C 4 = 250 jliF, and C, = C 3 = 18 fiF.
9-3
Direct-
Coupled
Two-Stage
Circuit
The two-stage amplifier shown in Fig. 9-3 is known as a dc feedback pair.
The base of (? 2 is directly connected to the collector of Q.,, and Qi is biased
via R 3 to the emitter of Q 2 . Comparing this circuit to the capacitor-coupled
two-stage amplifier in Fig. 9-1 shows a considerable savings in components.
The bias resistors (/?,, i? 2 , R 5 , and R 6 ) in Fig. 9-1 are eliminated in Fig. 9-3,
and only a single resistor (R 2 ) is employed in biasing. As well, the emitter
resistor and bypass capacitor are eliminated from the first stage, as is the
coupling capacitor between stages.
189
Direct-
Coupled
Two-Stage
Circuit
The redrawn circuit in Fig. 9-4 shows that Q, is biased from its own
collector, via transistor () 2 , which behaves as an emitter follower (as far as
the biasing of (?, is concerned). The biasing arrangement for is, in fact, a
variation of the collector-to-base bias circuit discussed in Section 5-4. Q. 2 is
emitter current biased, with emitter resistor R 4 stabilizing the emitter
current. Q 2 base voltage is derived from (), collector; consequently, Q 2 bias
stability is only as good as Q , stability.
Because collector-to-base bias is not as stable as emitter-current bias,
the bias conditions in this circuit (when h FE and/or temperature varies) will
not remain as constant as those in the circuit of Fig. 9-1. However, the
stability is adequate for many purposes, and the saving in components (and
space) is frequently a major advantage.
The circuit derives its name (DC feedback pair) from the fact that the
first and second stage are direct coupled (DC), and also because there is
voltage feedback from the collector of Qj to its base. As explained in Section
5-4, when the level of Ic\ is larger than intended, the (increased) voltage
drop across R x results in a lower than intended collector voltage y cl . This, in
turn, reduces the voltage drop across bias resistor R 2 , and consequently cuts
down on the level of base current to Q,. Since I c ^h FE I B , the lower base
current reduces the collector current level. Thus, there is feedback, which
tends to stabilize I c .
The negative feedback results in ac degeneration (see Section 5-8) if its
effect on the (ac) signal is not eliminated. Capacitor C 2 shorts the ac
190
Basic
Multistage
and
Integrated
Circuit
Amplifiers
(a) DC feedback pair
(b) Collector -
to-base bias
Figure 9-4. The bias circuit for Q 1 in a DC feedback pair is similar to a collector-to-base
bias circuit.
feedback to ground and eliminates ac degeneration on stage 1 . C 2 also
eliminates the ac degeneration on stage 2 by making R 4 look like an ac short
circuit to ground (again see Section 5-8).
The design approach to the dc feedback pair is fairly similar to that
taken in designing the two-stage capacitor-coupled amplifier. Only one
capacitor (C 2 ) determines the low-frequency cutoff point for the circuit.
Equation (9-1) applies. The input impedance is /? 2 ||^j, anc * is calculated
to have an impedance equal to one tenth of this value at frequency f v , using
Equation (9-3).
Example 9-2 Design a DC feedback pair (as in Fig. 9-3) to operate from a supply of
V cc = 12 V. Take I c = 2 mA, and assume that the transistors have h FE = 100,
hj e = \00, and h u = 2 kfl. The low 3-dB frequency for the circuit is to be
f x = 150 Hz.
solution
As in Example 9-1, make V R{ and V*4 as large as possible for good gain.
Take F C£(min) = 3 V.
For V E » V BE , let K R4 «5 V.
^«3 = V CC~ K CE~ Kt‘
R.= V *> 4V
S 12V — 3V — 5V = 4V
I c 2 mA
= 2 kfi (use 1.8-kfl standard value; see Appendix 1)
n K «4 5V
4 ~ I c 2 mA
= 2.5 kfl (use 2.2-kft standard value)
, now becomes
I c R a = 2 mA X 2.2 kfi = 4.4 V
^2=^4+^ = 4.4V + 0.7V=5.1 V
V C x=V B 2 = 5.1 V
Vr i ~ Vcc ~ ^ci “ 1 2 V — 5. 1 V
= 6.9 V
_ 2 _ 2 mA
100
= 20 fiA
I R , = / c , + I B2 = 2 mA + 20 /iA
= 2.02 mA
6.9 V
/», 2.02 mA
K \- , -
= 3.4 kfi (use 3. 3-kS2 standard value)
r^-^i=4.4V-0.7V
= 3.7 V
I c i _ 2 mA
^B\ L —
h FE
= 20 juA
100
R,=
3.7 V
From Eq. (9-1),
I BX 20/iA
= 185 kfl (use 180-kft standard value)
Co =
1 + K.
1 + 100
2irf x h u 2tf X 150 HzX2 kfl
= 54 pF (use 56-/utF standard value; sec
Appendix 2)
Z m = /t,„ 1| R 2 = 2 kft || 1 80 kfi = 1 .98 kfl
191
Direct-
Coupled
Two-Stage
Circuit
From Eq. (9-3),
192
Basic
Multistage
and
Integrated
Circuit
Amplifiers
9-4
The
Differential
Amplifier
9 - 4.1
Basic
Circuit
10 10
1 2 ir/jZ* 2 ttX 150 HzX 1.98 kfi
= 5.4 juF (use 5.6- juF standard value)
The differential amplifier is widely applied in integrated circuitry
because it has both good bias stability and good gain without requiring large
bypass capacitors.
Figure 9-5 shows the basic differential amplifier circuit. If transistors
Q j and Q .2 are assumed to be identical in all respects and have equal base
voltages, then
Tc-l /iT'
The total emitter current
I E remains virtually constant no matter what the h FE value of the transistors.
Figure 9-5. Basic differential amplifier.
Since anc * ^C 2 ~^E 2 > collector currents also remain con-
stant, and / C |«/c 2 *
In addition, V CI = F C2 = ( ^cc - ^c^z.)> assuming R tl = /? L2 .
Since I F is independent of transistor h FE variations, I c and V c are also
substantially independent of h FE , and it is seen that the differential amplifier has
excellent bias stability.
193
The
Differential
Amplifier
Recall from Eq. (6-7) that the voltage gain of the single-stage common 9-4.2
emitter amplifier in Fig. 9-6(a) is Voltage
Cain
A - ~*/A
* K+0 + h /*) R E
where R E is an external resistance in series with the transistor emitter
terminal.
Looking from Q,i emitter toward in Fig. 9-6(b), the resistance
“seen” is the Z x to a CB circuit; i.e., R = h lbi . Therefore, for a signal applied
at the base of Qj, () 2 ma Y be replaced with h tbj to give the single-stage
equivalent circuit of Fig. 9-6(c). Now applying the equation for single-stage
gain, and neglecting R E since it is typically much larger than h tbjt the gain of
the circuit in Fig. 9-6(c) is
h * l + ( l + k f' l ) h * t
It can be shown that
v-
1 I + K.
Therefore,
~ h R L
h u> + (l +h /e t ) h u a /( l+h f* a )
If the transistors are matched, as is usually the case in differential
amplifiers, then = hj tj and h Uf — h Uj and
A y —
- h f *R L
2h u
( 9 - 4 )
This is the voltage gain from one input to one output of a differential
amplifier. It is also half the gain available from a similar single transistor
stage with R E bypassed; but note that for the differential amplifier no bypass
capacitor is required.
194
Basic
Multistage
and
Integrated
Circuit
Amplifiers
gain of single stage
CE amplifier
hfe
h ,e + H + hfe) R E
(c) Singie-stage representation
of one side of differential
amplifier
h iey + ( 1 +
Figure 9-6. Comparing the voltage gain of a differential amplifier to a single-stage
common emitter amplifier.
Another way to consider the voltage gain of this circuit is to think of
the signal voltage ( F 5 ) being equally divided across h Ui and h ie , as shown in
Fig. 9- 7(a). Therefore, when the input is positive, the signal voltage devel-
oped across the base-emitter of £), is V s /2, positive on the base. Across the
base-emitter of Q 2 » Ks/2 appears positive on the emitter. This is illustrated in
Fig. 9-7(b). Q,i receives the signal at its base and behaves as a common emitter
amplifier, while O 2 receives the signal at its emitter (its base voltage
195
The
Differential
Amplifier
(a) Showing that l/ s is equally divided between and
<b) Showing that V s causes ~ to be applied as a CE
V* 1
input to O, and as a CB input to O,
(c) Showing output signals at 0, and 0 2 collectors
for input to O, base
Figure 9-7. Showing how an input to Q, produces outputs from Q, and Q 2 .
remaining constant) and behaves as a common base amplifier. Since common
emitter and common base voltage gains are equal,
- V s A /A
Output at Q, c ” ~ 2~ * —j - —
+ V, x A /A
~T —
and
Output at Qj2c
9-4.3
Input
and Output
Impedances
9-4.4
Inverting
and
Noninverting
Input
9-4.5
Common
Mode Gain
For common emitter the output is antiphase to input, while for
common base the output is in phase with the input. Therefore, the input and
output voltages are as shown in Fig. 9-7(c).
From Eq. (6-2), the input impedance for a CE circuit with an external
emitter resistance is
Z x = h u + ( 1 + hj e )R E
From Fig. 9-7(a), the external resistance connected to the emitter of Q,,
is R E \\h ib ^. Since R E (usually), R E can be neglected.
Taking h ib 2 in series with emitter,
Z i = h u+( X + h fe) h ib 2
Since h tb = h xe /( 1 4- hj t ), and assuming matched transistors,
Z = 2h te (9-5)
or Z x = 2 X ( Z x for a single-stage CE circuit)
As was the case for CE and CB circuits, the (circuit) output impedance
at the transistor collectors is
Z' 0 ~R l (9-6)
Figure 9-8 shows a differential amplifier with an emitter follower (Q. 3 )
connected to provide a low-impedance output. Note that if a positive-going
input is provided at terminal 1 , the output is also positive going. If a positive
going input is provided at terminal 2, the output is negative going. In this
circumstance, terminal 1 is referred to as the noninverting input, while terminal
2 is called the inverting input .
Note that in Fig. 9-8 the supply voltages are identified as + v cc and
— Vcc- They could, for example, be ± 9 V or ± 1 2 V, and the input and
output terminals could be close to ground level when no signal is present.
If in-phase signals are applied to terminals 1 and 2 at the same time,
the input is referred to as a common mode input. In this case the transistors are
operating in parallel, and the emitter current change is
(Fig. 9-9)
A/ £ i as A/ £2 = j — 2 ~fT E
*N
and AI c zszAI e
196
Figure 9-8. Differential amplifier with emitter follower output, showing inverting and
noninverting inputs.
197
The
Differential
Amplifier
The voltage change at transistor collectors is A V c , where A V c «
-A/ c fl L = (- V s R l )/{ 2R e ), and hV 0 = kV c because Qj is an emitter
follower.
The common mode gain is
198
Basic
Multistage
and
Integrated
Circuit
Amplifiers
Figure 9-10. Differential amplifier with constant-current tail.
A good amplifier should reject common mode signals; thus, the com-
mon mode gain should be as small as possible. This might be achieved by
increasing the value of but then the dc values of emitter and collector
currents would be reduced. The usual way to overcome this problem is to use
a constant- current tail as shown in Fig. 9-10. In this circuit I E =
{V BA — Vbe)/ ^E’ an< ^ remains constant no matter how V B1 and V B2 vary.
The ac resistance now “seen” from the emitters of j and Q 2 is the collector
resistance (1 / hj) of () 4 , which might typically be 1 MS2. Therefore, common
mode gain is very small.
2X(1/AJ
(9-8)
Example 9-3 The differential amplifier shown in Fig. 9-10 has R L1 = R L2 — 10 k£2 and
R e = 3.9 ktt. The supply voltage is ± 1 2 V, and the voltage at the base of () 4
is — 3.5 V. If () j and (? 2 bases are grounded, calculate the voltage at the () !
and Qjz collectors. Assume and Q 2 are perfectly matched and that for
each transistor ^£ = 0.7 V.
solution
4 = ( Qj base voltage with respect to ground) — ( ^cc)
= -3.5 V+12 V = 8.5 V
and
I e R e = V B4 - ^ £ =8.5V-0.7V = 7.8V
_ 7.8 V 7.8 V 0
' E R r 3.9 kfl 2 mA
Ie\ ~ Ie2~ 2 “ *
I r .^i I F , = 1 mA
199
The
Differential
Amplifier
and
^C2~ ^£2 — ^ rrL ^
*C2= ^cc“ / c /? L = 1 2 v-(l mAX10kfi)»2 V
For the circuit of Example 9-3, calculate the voltage gain, input Example 9-4
impedance, output impedance, and common mode gain if h u = 1 ktt, = 50,
and h ot = 1 X 1 0 _ 6 S.
solution
From Eq. (9-4),
From Eq. (9-5),
From Eq. (9-6),
From Eq. (9-8),
A„ =
2 K.
50 X 10 kfl
2 X 1 kfi
= 250
Z=2h = 2kft
z;»/? L = iokfi
* L
2x(l/0
10 kR
2x 1 X10 6
-5X10' 5
a cm“
9-5
1C
Differential
Amplifiers
Figure 9-11 shows the circuit of 'a CA3002 integrated circuit amplifier
manufactured by RCA. Transistors^ and Q, 6 are emitter followers provid-
ing high input resistance. Q.J and 0,2 are main differential amplifier
transistors of the circuit. has no load resistor because no output is taken
from its collector. R 3 and R+ are small resistances which help to match the
emitter currents of (>i and (> 2 . Resistors R 7 , R e , and ^? I0 provide bias to
constant current transistor (? 4 , and diodes D l and D 2 compensate for
temperature variations in the base-emitter voltage of (? 4 . Q, 3 is an emitter
follower for low output resistance.
It is important to note that the component tolerance is not critical for
the differential amplifier. For example, R L and R L in Fig. 9-5 could be 10
kfl±20% so long as they are closely matched to each other. Also, the
absolute current gain values for (?! and () 2 are not important, so long as h FE
is closely matched to h FE .
In monolithic integrated circuit fabrication, all transistor parts are
diffused at the same instant; therefore, all transistors have similar perfor-
Figure 9-11. Circuit of CA3002 integrated circuit amplifier. (Courtesy of RCA Corp.)
200
mance. Similarly, all resistors are diffused at the same instant, and thus all
resistors having the same nominal value tend to match each other closely.
These facts, and the lack of a requirement for large bypass capacitors, make
the differential amplifier ideal for application to integrated circuits.
In Figs. 9-12 and 9-13, condensed specifications are presented for
CA3002 and /iA741 IC amplifiers, respectively. There are significant dif-
ferences in the performances of these two circuits, so it is important to note
that the CA3002 is designed to operate over a wide frequency range, while
the fiA741 is intended to be a general-purpose operational amplifier. An
operational amplifier is essentially a high input impedance, low output imped-
ance high-gain circuit, with inverting and noninverting input terminals.
201
1C
Differential
Amplifiers
CA3002
IF AMPLIFIER
General-purpose amplifier used in video amplifier, product and AM detector
applicatons. 10-lead JEDEC MO-006- AF package;
MAXIMUM RATINGS
Positive DC Supply Voltage V*
Negative DC Supply Voltage V-
Input Signal Voltage (Single-ended)
Total Device Dissipation
Temperature Range:
Operating
Storage
-1-10 V
-10 V
—3.5 V
300 mW
-55 to 125 *C
-65 io 200 *C
TYPICAL CHARACTERISTICS (At ambient temperature = 25 a C, V* = +6V,
V- = — 6V)
Static Characteristics
Input Unbalance Voltage
Input Unbalance Current
Input Bias Current
Quiescent Operating- Voltage:
Terminal 2 connected to V-. terminal
4 not connected
Terminals 2 and 4 connected to V - ....
Device Dissipation
Dynamic Characteristics
Differential Voliage Gain (Single-Ended
Input and Output, f = 1.75 MHz) ....
— 3-dB Bandwidth
Maximum Output Voltage Swing
Noise Figure
(R. = 1 kO, f = 1.75 MHz)
Parallel Input Resistance
(f = 1.75 MHz)
Parallen Input Capacitance
(f = 1.75 MHz)
Output kesistance (f = 1.75 MHz)
3rd Harmonic Intermodulation
Distortion
AGC Range (Maximum Voltage Gain to
Complete Cutoff, f = 1.75 MHz)
V,c
2.2
mV
I.C
2.2typ; 10 max
I,
20 typ; 36 max
2.8
V
3.9
V
Pt
55
mW
AdIFI
19 min; 24 typ
dB
BW
11
MHz
V 0UI (P-P)
5.5
V
NF
4 typ; 8 max
dB
R,.
100
kO
c,.
4
PF
R„,
70
n
IMD
—30 min; —40 typ
dB
AGC
60 min: 80 typ
dB
Figure 9-12. Condensed specification for RCA CA3002 IC amplifier. (Courtesy of RCA
Corp.)
202
Basic
Multistage
and
Integrated
Circuit
Amplifiers
FAIRCHILD LINEAR INTEGRATED CIRCUITS /xA741
ELECTRICAL CHARACTERISTICS (V s = ±15 V, T A = 25’C unless otherwise specified)
PARAMETER
CONDITIONS
MIN.
TYP
MAX
UNITS
Input Offset Voltage
R s < 10 kn
10
50
mV
Input Offs«t Current
30
200
nA
Input Biss Currant
200
500
nA
Input Resistance
0.3
1.0
Mn
Large Signal Voltage Gem
R t > 2kn. V^, = ±10V
SO, 000
200.000
Output Voltige Swing
R^ > )0kn
±12
±14
V
R t > 2kn
±10
±13
V
Input Voltage Range
±12
±13
V
Common Mode Rejection Ratio
R s < 10 kn
70
90
dB
Supply Voltage Rejection Ratio
r s < io kn
30
150
xV/V
Power Consumption
50
BS
mW
Transient Response (unity gam)
V,„ = 20 mV. R v = 2 kn.
C^ < 100 pF
Risetime
0.3
XI
Overshoot
SO
%
Slew Rate (unity gain)
R l > 2 kn
OS
V/xs
The following specifications apply tor
— 55*C < T A < +12S‘C-
Input Offset Voltage
R s < 10 kn
60
mV
Input Offset Current
500
nA
Input Bias Current
1.5
xA
Large Signal Voltage Gam
R t > 2kn. V^, = ±10V
25,000
Output Voltage Swing
R t > 2 kn
±10
V
Figure 9-13. Condensed specification for /tA741 1C amplifier. (Courtesy of Fairchild
Semiconductors)
Some of the most important terms used in the specifications are
defined as follows:
Open-loop voltage gain. The ratio of output voltage to input voltage, i.e.,
the circuit internal gain.
Differential voltage gain (single-ended input and output). The ratio of
output voltage to input voltage at either one of the two inputs, i.e., same as
the open-loop gain.
Common-mode rejection ratio. The ratio of the amplifier open-loop gain
to its common mode gain.
Input bias current. The base current to the input transistors. 203
Input offset current. The difference between the base currents of the input Differential
transistors. Amplifiers
Input unbalance current. Same as input offset current.
Input offset voltage. The necessary difference between bias voltages at the
input transistors to obtain zero output voltage.
Input unbalance voltage. Same as input offset voltage.
Input resistance. The ratio of input voltage change to input current
change, measured at one input terminal.
Output resistance. The ratio of output voltage change to output current
change.
Slew rate. Rate of change of output voltage, expressed in volts per micro-
second.
The specified 24-dB typical gain for the CA3002 is a voltage gain of
approximately 16, while the typical voltage gain for the /tA741 is specified as
200,000. However, the bandwidth of the CA3002 is 1 1 MHz, while that of
the /tA741 is less than 100 kHz when the gain is reduced to approximately 24 dB
(see the open-loop frequency response graph).
The circuit symbol employed for IC amplifiers is shown in Fig. 9-14,
together with a typical ftA741 dual-in-line package and a terminal number-
ing diagram. The output terminal is always at the point of the triangle as
shown, and the input terminals are at the opposite side. The inputs are
usually identified by 4- and — , indicating the noninverting input and the
inverting input, respectively. Other terminals are used for connecting the
positive and negative supplies and in some cases for connection of external
components.
Dual-in line package
and numbering diagram
Figure 9-14. Operational amplifier circuit symbol, package, and numbering system.
9-6
Basic 1C
Operational
Amplifier
Circuits
9 - 6.1
The
Voltage
Follower
The IC operational amplifier lends itself to an infinite variety of
applications. Perhaps the very simplest application is the voltage follower
circuit shown in Fig. 9-1 5(a). The inverting input terminal is connected
directly to the output terminal. The noninverting input becomes the single
input terminal of the circuit.
The output of the voltage follower follows the input voltage. This is
easily seen by examining the basic operational amplifier circuit diagram in
Fig. 9- 15(b). As in Fig. 9- 15(a), the inverting terminal (2) is connected
directly to the output terminal ( 6 ). If terminal 3 is grounded, terminal 6
(and terminal 2 ) must also be at ground level.
Note that the bias resistors ( R 2 and Rf) at the base of (£3 potentially
divide the collector voltage of Q 2 , so that V 0 can be lower than V C 2-
Suppose terminal 6 were slightly above ground level; then terminal 2
would be more positive than terminal 3, and consequently more collector
current would flow in This would cause an increased voltage drop across
and thus lower the base voltage of Q 3 and the output voltage. The circuit
would settle only when the voltage at terminal 2 is again equal to that at
terminal 3, i.e., when V 0 = V t . Similarly, any movement of the output in a
negative direction would produce a feedback effect which pulls the output
back up until the inverting and noninverting input voltages are again equal.
When the input voltage at terminal 3 is increased or decreased, the
feedback effect makes the output voltage follow the input faithfully. The
actual difference between input and output voltage can be calculated from
the output voltage level and the amplifier gain.
Suppose the voltage follower has an input of 5 V. The output should
also be 5 V, and to produce this output voltage there must be a voltage
difference between the two input terminals, i.e., between terminals 2 and 3
in Fig. 9- 15(a) and (b). This input voltage difference is sometimes termed a
differential input. The differential input is
V
y . = 2
dif amplifier open loop gain
To calculate the maximum differential input voltage, use the minimum
value of M. From the /xA741 data sheet in Fig. 9-13, the minimum value of
large-signal voltage gain is 50,000. Therefore, for V 0 mb V,
V
d,f 50,000
= 0.1 mV
This means that when the input voltage (at terminal 3 in Fig. 9-15) is 4-5 V,
204
205
Basic 1C
Operational
Amplifier
Circuits
(b) Basic operational amplifier circuit
connected as a voltage follower
Figure 9-15. 1C operational amplifier voltage follower,
the output voltage is actually
[/ = 5 V - 0. 1 mV = 4.9999 V
Terminal 2 is then 0.1 mV below the level of terminal 3, and 0.1 mV is the
minimum differential input necessary to cause the output to change by
approximately 5 V.
206
Basic
Multistage
and
Integrated
Circuit
Amplifiers
9-6.2
Noninverting
Amplifier
Like an emitter follower circuit, the voltage follower has a high input
impedance, a low output impedance, and a gain of 1 . The voltage follower
performance is very much superior to that of an emitter follower. Its input
impedance is normally much higher than that of the emitter follower, and
its output impedance can be much lower. Also, as explained above, the
difference between input and output is typically less than 0.1 mV with a
voltage follower. For an emitter follower, the input-output voltage dif-
ference may be 0.7 V with a silicon transistor or 0.3 V for a germanium
device.
The noninverting amplifier circuit in Fig. 9-16 behaves very similarly
to the voltage follower circuit. The major difference is that, instead of all the
output voltage being fed directly back to the inverting input terminal (as in
the voltage follower), only a portion of it is fed back. The output voltage is
potentially divided by R 2 and R 3 before being applied to terminal 2.
There is normally very little voltage drop across R { in this circuit, so
that V t effectively appears at terminal 3. As for the voltage follower, the
output voltage changes until the voltage at terminal 2 (inverting input) is
equal to the voltage at (noninverting input) terminal 3. Therefore, the
voltage across R 3 is V-.
The current I 2 is always selected very much larger than the input bias
current to the operational amplifier. This means that I 2 effectively flows
through R 2 and R 3 .
h=
%
(9-10)
Figure 9-16. Noninverting amplifier.
The output voltage at terminal 6 ( V 0 ) appears at one end of R 3 . Since
R 2 is grounded, V 0 appears across (R 2 + 7? 3 ), and
r
2 * 2 + *3
(9-H)
The circuit voltage gain is
From Eqs. (9-10) and 9-11,
207
Basic 1C
Operational
Amplifier
Circuits
K-VJ, and K = I 2 (R 2 + R 3 )
Therefore,
A-
/? 2 +/f 3
“ A”
(9-12)
The design procedure for the noninverting amplifier begins with
selection of I 2 very much larger than the input bias current I B of the
operational amplifier. R 2 and R 3 are calculated from the equations derived
above. There is a small voltage drop at each input terminal of the opera-
tional amplifier due to I B X (bias resistance). R } is made approximately
equal to the parallel equivalent resistance of R 2 and R 3 to ensure that these
voltage drops are approximately equal at each input terminal.
Design a noninverting amplifier circuit using a fiA741 IC operational Example 9-5
amplifier. The output voltage is to be approximately 2 V when the input is
50 mV.
solution
l 2 ^> 1 B
For the j^A741, /fl (mAX ) = 500 nA.
Let
/ 2 = 100x/ fi = 100X500 nA
= 50 juA
From Eq. (9-10),
208
Basic
Multistage
and
Integrated
Circuit
Amplifiers
50 mv
50 /xA
= 1 k£2 (standard resistor value)
From Eq. (9-11),
V
*• = f
2 V
50 fiA
= 40 kfi
R 2 = 40 kfi — R 3
= 40 kfi-1 kfi
= 39 kfi (standard resistor value)
/? 1 = /? 2 ||i? 3 =l kfi||39 kfi
«1 kfi
The input impedance of the noninverting amplifier is very high due to
the feedback effect of R 2 and R 3 . The input impedance can be shown to be
where Z i is the operational amplifier input impedance, M is the internal
gain or open-loop gain of the operational amplifier, and A o is the circuit
voltage gain {R 2 + R^)/ R 3 .
Z t = ] M£2 typically for the /utA741 , and M= 200,000 typically. For the
circuit designed in Example 9-5,
For obvious reasons, the noninverting amplifier is also known as a high input
impedance amplifier.
The circuit output impedance is also affected by resistors R 2 and R 3 :
(9-13)
= 5,000 MS2
Z ° l + M/A,
(9-14)
The /uA741 has Z o = 70 ft typically. Therefore, for Example 9-5,
z ,_ 7012
0 1 4- (200,000/40)
= 0.014 ft
209
Basic 1C
Operational
Amplifier
Circuits
The name inverting amplifier is applied to the circuit of Fig. 9-17 simply
because the output goes negative when the input goes positive, and vice
versa. Note that terminal 3 is grounded via resistor R v Because a very small
differential input (less than 1 mV) can cause the output to change by a large
amount, the voltage at terminal 2 should remain very close to that at
terminal 3. Therefore, terminal 2 voltage is always very close to ground.
Because it is not grounded, but remains close to ground potential, the
inverting input terminal in this application is sometimes termed a virtual
ground or virtual earth.
If V i in Fig. 9-17 is + 1 V, the input current can be calculated as
/.=
Vjn
9 - 6.3
Inverting
Amplifier
Since one end of is at V t = 1 V, and the other end is at ground level,
%
( 9 - 15 )
From the jiA741 data sheet in Fig. 9-13, the input bias current (i.e.,
the current flowing into terminals 2 and 3) is a maximum of 7^ = 500 nA. If
7, is very much greater than l B> then effectively all of 7, must flow through
Figure 9-17. Inverting amplifier.
210
Basic
Multistage
and
Integrated
Circuit
Amplifiers
Example 9-6
resistor R 2 (see Fig. 9-17). This means that the voltage drop across R 2 is
/, X R 2 . The left side of R 2 is connected to terminal 2, which, as already
discussed, is always at ground potential. Therefore, the right side of R 2 is at
(/, X R 2 ) volts below ground level; i.e.,
From Eq. (9-15),
K=-(i,xr 2 )
and voltage gain is
or
A =
A =
K -A*2
K
zjk
A
(9-16)
(9-17)
If ^= + 10 mV and fi 2 /«, = 100, then K.- - 100 X 10 mV= - 1 V.
When the input voltage is negative, the output is positive. A similar kind of
feedback effect to that which occurs with the voltage follower and the
noninverting amplifier keeps the output voltage exactly equal to — (R 2 / R x )
X V i-
The design of an inverting amplifier is quite simple. A current I x is
selected so that I X ^>I B . R { is calculated from Eq. (9-15), and R 2 is de-
termined using either Eq. (9-16) or (9-17). R 3 is made approximately equal
to the parallel equivalent resistance of R x and R 2 .
An inverting amplifier using a /tA741 IG operational amplifier is to
have a voltage gain of 144. The input signal voltage is typically 20 mV.
Determine suitable resistor values.
solution
For the /xA741,
/ fl( ma*) = 500nA
and max)
Let
/j ^ 1 00 X /g( m ax)
= 1 00 X 500 nA = 50 jx A
From Eq. (9-15),
_ K _ 20 mV
1 * /, 50 (iA
= 400 £2 (use 390-£2 standard value; see Appendix 1)
211
Transformer-
Coupled
Class A
Amplifiers
From Eq. (9-17),
R 2 = A v XR {
= 144X390 £2
= 56.2 left (use 56-k£2 standard value)
*3 = *ill *2 = 56 k£2||390£2
«7?,= 390 £2
The input impedance of the inverting amplifier is
( 9 - 18 )
For Example 9-6, the circuit input impedance is only 390 £2, which is very
much smaller than that obtained for the noninverting amplifier. It is seen
that the inverting amplifier has a relatively low input impedance.
The output impedance of the inverting amplifier is calculated from
Eq. (9-14). For the circuit in Example 9-6,
70 £2
0 1+ (200,000/ 144)
= 0.05 £2
Like capacitor coupling, a transformer may be used to ac couple
amplifier stages while providing dc isolation between stages. The dc resis-
tance of the transformer windings is very small, so that there is no effect on
the transistor bias conditions.
Figure 9- 18(a) shows a load resistance R L transformer coupled to the
collector of the transistor. The low (dc) resistance of the transformer primary
winding allows any desired level of collector current to flow, while the
transformer core couples all variations in I c to R L via the secondary winding.
The actual dc load connected in series with the collector and emitter of
transistor (), is (/? PK + R 3 ), where Rpy is the resistance of the primary
winding. The resistance (R py + R 3 ) is used to draw the dc load line on the
transistor characteristics. The ac load line is a little more complicated. (Note
that the dc load line and ac load line for a capacitive coupled circuit are
explained in Sections 5-2 and 5-8, respectively.)
9-7
Transformer-
Coupled
Class A
Amplifiers
212
Basic
Multistage
and
Integrated
Circuit
Amplifiers
R l R l + Rpy
i/, r:
(b) Transformer showing reflected load
Figure 9-18. Class A transformer-coupled amplifier and reflected load.
Consider the transformer illustrated in Fig. 9- 18(b). TV, is the number
of turns in the primary winding, and N 2 is the number of secondary turns.
V x and /j are the primary voltage and current, while V 2 and I 2 are the
voltage and current for the secondary.
The load resistance R L could be calculated as
The ac load resistance that could be measured at the terminals of the
primary is designated R[ y which is calculated from
From basic transformer theory,
* '»
",
n 2
and
A
A
N*
N,
This gives
v *“Tr v * and 7 >=
A' 2
AA'
Substituting for V J and /, in the equation for R [ ,
(jy,/Af 2 )r a
4 (AAM)A
or
(9-19)
is frequently termed the reflected load , meaning that is reflected into the
primary as R' L . R[ is also described as the load resistance referred to the primary.
The total ac load seen by transistor Q, in Fig. 9- 18(a) is the sum of R[
and the dc winding resistance of the transformer primary.
213
Transformer-
Coupled
Class A
Amplifiers
The circuit shown in Fig. 9- 18(a) has V cc = 11 V, ^ = 4.7 k£2, R 2 = 2.2 Example 9-7
k£2, and /? 3 = 560 £2. Transformer T x has R PY — 40 £2, N x = 74, and Af 2 =14.
The load resistance is R L = 56 £2. Draw the dc and ac load lines for the
circuit on the transistor common emitter characteristics in Fig. 9-19.
solution
dc load line
f'cc — /c( Rpy + ^3) ^CE
When 7 C = 0, V cc = V CE .
Plot point A on Fig. 9-19 at I c = 0, V C e~ ^cc~ 1 1 V.
Another point on the dc load line (and on the ac load line) is the Q point.
214
Basic
Multistage
and
Integrated
Circuit
Amplifiers
Figure 9-19. DC and ac load lines for a transformer-coupled amplifier.
This defines the dc bias conditions in the circuit.
^ b ~
*2
R x + R 2
= 11 VX
2.2 kfl
2.2 ld2 + 4.7 kfl
= 3.5 V
V E = V B — V BE — 3.5 V— 0.7 V
= 2.8 V
_ V E _ 2.8 V
Ie R 3 560 a
= 5 mA«/ c
K cc = / c (/? / >y + 7?3)+ V CE
When 7 C = 5 mA,
11 V = 5 mA(40 + 560 £2)4- V CE
V CE = ZV
Plot the point on Fig. 9-19 at 7 C = 5 mA and Vce = 8 V. Draw the dc load
line through points A and ().
ac load line
Use Eq. (9-19):
= (-^) 2 X56fi = 1564 a
Total ac load,
Rl=Rpy+R'l
= 4012+1564
= 1.6 kS2
When the collector current changes by A/ c = 5 mA,
A V CE = A/ c X R l
= 5 mA X 1 .6 k!2
= 8 V
On Fig. 9- 19(b) measure A I c and AF C£ from the () point to give point B at
V CE — 16 V. Draw the ac load line through points () and B.
215
Transformer-
Coupled
Class A
Amplifiers
The ac load line drawn in Example 9-7 is reproduced in Fig. 9-20,
where the effect of an input signal is also illustrated.
When the input signal causes the base current to be increased by
A/ b = 40 pA, the transistor current and voltage become those at point A' on
the ac load line; i.e., / c «s9 mA and ^c^^l-6 V. Similarly, when the base
current is decreased by A/ B = 40 pA, the current and voltage (at point B’)
are l c ^ 1 mA and V CE f&\AA V.
It is seen that a base current variation of A I B — ±40 pA causes the
collector current to change by A/ c =±4 mA and the collector-emitter
voltage to change by A V CE — ± 6.4 V.
This ±6.4-V variation in V CE appears across the primary winding of
transformer T,, Fig. 9-19(a). The collector current change A/ c =±4 mA
also flows through the transformer primary winding. The load current can
be calculated as
A4=^ ( A/ c)
= TT x ^ ±4mA ^
« ±21 mA
It is important to note that although the supply voltage to the circuit
in Fig. 9- 19(a) is only v cc= n V, the transistor collector-emitter voltage
can actually go to V* = 16 V. This is due to the inductive effect of the
transformer primary winding. When selecting a transistor for such a circuit,
the breakdown voltage of the device should be approximately twice the
circuit supply voltage.
The circuit in Fig. 9- 18(a) is referred to as a class A amplifier. A class A
circuit is defined as one in which the Q point is approximately at the center
of the ac load line.
Figure 9-20. Input signal and transformer primary voltage in a transformer-coupled
amplifier.
9-8
Transformer-
Coupled
Class B
and Class
AB Circuits
One of the most important considerations in power amplifier design is
efficiency. Power dissipated when no signal is present is, of course, wasted
power which reduces the efficiency of the circuit. Class A circuits dissipate
considerable power due to the transistor bias conditions, and consequently
they have low efficiency. In a class B amplifier, the transistors are biased at
cutoff so that there is no transistor power dissipation when the input signal
level is zero.
A basic class B circuit is illustrated in Fig. 9-2 1(a). Transformer T x
couples load resistor R L to the collector circuits of two transistors and Q, 2 -
Note that the primary of the transformer has a center tap to which the dc
supply voltage Vac is connected. and Q 2 have grounded emitters and
both are biased off via resistors R 1 and R 2 , which ground the bases.
The input signals applied to the transistor bases consist of two separate
sine waves which are identical, with the exception that they are in anti-
phase. When V x is going positive, V 2 is going negative, so that Q ^ is being
biased further off when Qj is being biased on. As the collector current in Q,i
increases from zero, it produces a half sine wave across the upper half of the
(b) Composite characteristics for class B amplifier
Figure 9-21. Class B amplifier circuit and composite charactemucs.
transformer primary, as illustrated. When the positive half-cycle of input
signal to (), base begins to go negative, the signal at () 2 base is commencing
to go positive. Thus, as (), becomes biased off again, Q 2 is biased on , and a
half-cycle of waveform is generated across the lower primary winding of the
transformer.
The effect of the two half-cycles in separate halfs of the transformer
primary is to produce a magnetic flux in the transformer core, which flows
first in one direction and then in the opposite direction. This flux links with
218
Basic
Multistage
and
Integrated
Circuit
Amplifiers
the transformer secondary winding and generates a complete sine wave
output, which is passed on to the load.
In the class B circuit, the two output transistors are said to be
operating in push-pull. The push-pull action is best illustrated by drawing
the load line on the composite characteristics , as shown in Fig. 9-2 1(b).
Suppose the supply voltage to the circuit in Fig. 9-2 1(a) is F cc = 16 V.
Then, when the input signal is zero, both transistors are biased off: I c = 0
and V CE = V cc =16 V. Therefore, the Q point is at I c = 0 and V CE = V cc .
Suppose the ac load offered by each half of the transformer primary to the
transistor collectors is 1 .6 kfi (as in Example 9-7).
Vqe = Vcc ~ Ic^l
and when Vqe ~
16V
“ 1.6 kti
= 10 mA
Plot point B on the ac load line at V C e — 0 and I c = 1 0 mA. Draw the
ac load line for Q, ! from the point to point B. The ac load line for is
exactly the same as that for Q,,- To best see what occurs when a signal is
applied, the characteristics for (? 2 are drawn as shown in Fig. 9-2 1(b), so
that the ac load line becomes one continuous line (from B to B') for both ()j
and 0,2 with the bias point 0 at its center.
Now consider the effect of the signal applied to the bases of Oi and 0,2-
When Oi base current is increased from zero to 90 /iA, O 2 remains off and
Vqei falls to 1 .6 V. At this point the voltage drop across the upper half of the
transformer primary in Fig. 9-2 1(a) is
Vrl = V cc — V CE
= 16 V — 1.6 V= 14.4 V
When the base current of O 2 ls increased from 0 to 90 /i,A, 0i is off and
14.4 V is developed across the lower half of the transformer primary
winding.
As explained, a full sine wave is developed at the output of the
transformer. When no signal is present, both transistors remain off and there
is almost zero power dissipation. Some power is dissipated in each transistor
only while it is conducting. The wasted power is considerably less with the
class B circuit than with a class A circuit.
Actually, the waveform delivered to the transformer primary and the
resultant output are not perfectly sinusoidal. Cross-over distortion exists, as
illustrated in Fig. 9-2 1(b), due to the fact that the transistors do not begin to
turn on properly until the input base-emitter voltage is about 0.5 V for a
silicon device, or 0.15 V for a germanium transistor. To eliminate this effect,
the transistors may be partially biased on instead of being biased completely
off. With this modification, the circuit becomes a class AB amplifier.
Figure 9-22 shows a class AB transformer-coupled output stage with a
class A transformer-coupled driver stage.
The output transformer T 2 has a center-tapped primary winding, each
half of which forms a load for one of the output transistors, ()j and Q_ 2 .
Resistors R 4 and R b bias (), and Q 2 partially on, and resistors R 6 and R 7 limit
the emitter (and collector) currents to the desired bias levels. T i and (£3 and
the associated components comprise a class A stage. The secondary of T x is
center tapped to provide the necessary antiphase signals to (), and Q 2 -
When the polarity of T x output is + at the top, (), base voltage is
positive and () 2 base voltage is negative, as illustrated. At this time (), is on
219
Transformer-
Coupled
Class B
and Class
AB Circuits
Figure 9-22. Class AB output stage with class A driver.
220
Basic
Multistage
and
Integrated
Circuit
Amplifiers
Example 9-8
for a class B circuit, with the exception that each transistor commences to
conduct just before the signal to its base becomes positive. This eliminates
the delay in transistor turn on, which creates cross-over distortion in a class
B amplifier.
The class A circuit in this case is referred to as a driver stage , simply
because it provides the input signals to drive the class AB output stage. The
input power handled by the driver stage is very much smaller than the
circuit output power; therefore, in this case the inefficiency of the class A
stage is unimportant.
The design of class B and class AB transformer-coupled circuits consists
largely of working out a specification for each of the components involved.
A class B amplifier is to supply 5 W to a 16-12 load. The available
supply voltage is Vcc = 30 V. Specify the output transformer and output
transistors.
solution
v o 2
P 0 = (where V 0 is rms voltage)
r l
peak output voltage Vp
and V 0 = =
V2 V2
(yvz) 2 v±
R l 2 R l
or transformer peak output voltage is
V P =V 2R[P„
= V2X 16 12X5 W
«12.6 V
Peak input voltage to each half of the transformer primary is
V^V CC = 30V
Transformer turns ratio from one half of the primary to the secondary is
30
N 2 12.6
From the whole primary to the secondary, the turns ratio is
2/V, 60
N 2 12.6
The ac load resistance appearing at each half of the primary is, using Eq.
(9-19),
x' L -
Xl
X 16 £2^91 £2
221
Transformer-
Coupled
Class B
and Class
AB Circuits
The total load appearing at the terminals of the whole primary is
The transformer is specified in terms of its output power, the load to be
supplied, and the total load reflected into the primary:
P 0 = 5 W, R l = 1 6 £2, R'l = 363 £2, primary center tapped
The transistors have to survive a maximum collector-emitter voltage of
V ce — 2 X V cc
= 2X30 V = 60 V
The transistor peak collector current is
30 V
91 £2
s=k 330 mA
Maximum power dissipation occurs in the output transistors when Vce
= 2 ^CC an< ^ 2 Ip'
» v cc..lp 30 V w 330 mA
«2.5W
The transistors are specified in terms of maximum and P:
/«„„>- 330 mA, Voh^-SOV, />_- 2.5 VV
9-9
Multistage
Emitter
Followers
In some situations where a fairly large output current is to be supplied
by an emitter follower, the input current to the emitter follower is so large
that it cannot be supplied from the output of most amplifiers. For example,
an emitter follower with an emitter current of 7 £ = 500 mA and a current
gain of h FE = 49 requires a base current of
_ Ir _ 500 mA
B 1 + h FE 1 +49
= 10 mA
To further reduce the level of input current, another (emitter follower)
transistor is connected as illustrated in Fig. 9-23. This circuit is known as a
Darlington pair , and it can be made up of npn transistors, Fig. 9-23(a), or of
pnp transistors as shown in Fig. 9-23(b).
Q_ 2 is the output transistor carrying the load current. is the input
transistor. The load current is I E2 , and the base current to £) 2 is
/ - bi
B 2 »+*«
~Ie\
The input current is I Bl :
7 —
81 1 + A*
0 +h FEl)0 +ll FE2 )
( 9 - 20 )
(a) npn darlington pair (b) pnp darlington pair
Figure 9-23. Darlington-pair emitter follower.
222
or
,XA,
(9-21)
Because the h FE (or beta) of the two- transistor combination is ( h FEl X
h FE2 ), t ^ ie Darlington pair is also termed a superbeta circuit.
A Darlington pair as in Fig. 9-23 (a) is made up of a 2N3055 for Q ^
and a 2N3904 for (),. The load resistance (R L = 10 £2) is to be supplied with
4 V. The circuit supply voltage is Vcc = 10 V. Calculate the maximum level
of input current, the input voltage level, and the power dissipated in each
transistor.
solution
input voltage
K + V B E2
= 4 V + 0.7 V + 0.7 V
= 5.4 V
output current
4 V
100
= 400 mA
I R2
[§2
1 + h FE2
From Fig. 8-2, the minimum h FE value listed for the 2N3055 is h FE = 20.
(Note that this is at l c — 4A. At 400 mA h FE is likely to be greater than 20.)
400 mA
l R 2(m*x) j + 2Q
19 mA
Ibi
(b2
i + Vf i
223
Multistage
Emitter
Followers
Example 9-9
From Fig. 8-1, the minimum h FE value (at 7 C = 1 mA) is around 70.
input current
224
Basic
Multistage
and
Integrated
Circuit
Amplifiers
19 mA _ ,
I B l(rnax) ~ J 4. 7Q ^270 flA
?2 = ^CE2 X ^C2
«(F CC - F o )X/ £2 = (10 V-4 V)X400mA
= 2.4 W
^1 = ^CEl X 1
«( ^cc - ^1) X / 52 = ( 10 V - 4.7 V) X 19 mA
= 0.1 W
The input impedance of a Darlington pair is
^ ~ hf e i X hj e2 X /? L
(9-22)
For A /(rl = 70, hj e2 = 20, and R L = 100,
2;«70X20X100fi
«140 kfi
This value is, of course, modified by any bias resistors that might be
employed at the input. The output impedance at the emitter of Q 2 I s
(9-23)
where R s is the impedance of the signal source. For hj eX = 70, hj e2 = 20, and
/?,= lkft,
„ lk g
70X20
«0.7fl
This is a very low output impedance, but it is very important to note
that in general it applies only for very low frequency operation and for
small-signal operation at higher frequencies (i.e., for signals much less than
Vbe)- If the circuit is operated at high frequency with a large input signal,
the transistor base-emitter voltage can be reversed when the large fast-
moving signal is going in a negative direction. The result is that the output
waveform is partially chopped off or at least seriously distorted.
The complementary emitter follower circuit shown in Fig. 9-24 eliminates
the problem discussed above. It is seen that the circuit consists of an npn
transistor () , connected in series with a pnp transistor Q 2 . The load resistor
R l is capacitor coupled, but it could be direct coupled if 4- and — supply
voltages are used. Transistor Qs and resistors /? 3 , R 4 , and R 5 show one
method of providing bias and input to Q, , and (? 2 - must have a voltage
drop across it of approximately 2X ^BE' Capacitor C, bypasses R 4 to ensure
that the ac input signal is developed equally at the bases of Q, and Q. 2 .
Emitter resistors R, and R 2 limit the bias current flowing through Q, and
0 . 2 -
When the input signal to the bases of (), and () 2 is large and going
positive, Q 2 base-emitter might become reverse biased. This is not im-
portant because under these conditions (), base-emitter will be very defi-
nitely forward biased. Similarly, when a large input is going in a negative
direction, the base-emitter of Q, might become reverse biased, but (? 2
base-emitter junction will be forward biased. Thus, the complementary
emitter follower provides a low output impedance under all conditions of
input signal.
225
Multistage
Emitter
Followers
Figure 9-24. Complementary emitter follower.
Glossary of
Important
Terms
Review
Questions
Capacitor coupling. Signal transference between amplifier stages by means
of interconnecting capacitors.
Direct coupling. Direct connection between amplifier stages.
DC feedback pair. Two-stage directly coupled amplifier in which each
stage is biased from the other.
Differential amplifier. Amplifier which uses two emitter-coupled transis-
tors.
Inverting input. Input terminal of a differential amplifier which produces
an antiphase output when a signal is applied.
Noninverting input. Input terminal of a differential amplifier which pro-
duces an in-phase output when a signal is applied.
Common mode gain. Ratio of output voltage to a common signal applied
to both inputs of a differential amplifier.
Constant current tail. Additional transistor connected to provide a con-
stant emitter current for a differential amplifier.
Operational amplifier. Amplifier with two input terminals, one output
terminal, very high gain, high input impedance, and low output
impedance.
Voltage follower. Operational amplifier connected to give a gain of 1, very
high input impedance, and very low output impedance.
Noninverting amplifier. Operational amplifier circuit in which the output
is in phase with the input.
Inverting amplifier. Operational amplifier circuit in which the output is in
antiphase with the input.
Virtual ground. One input terminal of an operational amplifier circuit
which although not grounded always remains at ground level.
Transformer coupling. Signal transference between amplifier stages by
means of interconnecting transformers.
Reflected load. Effective load at the primary terminals of a transformer
due to the load connected to the secondary.
Glass A amplifier. Amplifier in which the output transistor’s bias point is
approximately at the center of the ac load line.
Class B amplifier. Amplifier in which the output transistors are biased at
cutoff.
Glass AB amplifier. Amplifier in which the output transistors are partially
biased on.
Darlington pair. Two transistors connected as cascaded emitter followers.
Complementary emitter follower. Two transistors, one npn , the other pnp ,
connected to function as emitter followers with common input and
output terminals.
9-1. Sketch the complete circuit of two emitter current bias stages using
capacitor coupling. Briefly explain the function of every component.
226
9-2. Discuss the approach to designing a two-stage capacitor-coupled
transistor amplifier. Explain the method of calculating each compo-
nent and the reasoning behind the method.
9-3. Sketch the circuit of a DC feedback pair. Briefly explain the biasing
method for each transistor, and discuss the function of each compo-
nent in the circuit.
9-4. Sketch the circuit of a basic differential amplifier. Briefly explain
how the biasing technique affects the component currents and voltage
drops.
9-5. For a differential amplifier, show that the gain A v = (hj e R L )/2h u . Also
derive an expression for common mode gain and show how the
common mode gain can be reduced.
9-6. Sketch the circuit of a differential amplifier with an emitter follower
output. Identify the inverting and noninverting input terminals.
9-7. Sketch the circuit of a differential amplifier with a constant current
tail. Explain how the constant current tail functions and how it
affects the circuit.
9-8. Sketch the circuit of the CA3002 IC amplifier. Explain the function
of all components. Also explain why the differential amplifier is
extensively employed in integrated circuits.
9-9. Define operational amplifier. State typical values of open-loop gain,
input bias current, input impedance, and output impedance for an
IC operational amplifier.
9-10. Sketch the circuit of an operational amplifier employed as a voltage
follower. Identify all terminals of the amplifier. Also sketch the basic
operational amplifier circuit and explain how it functions as a
voltage follower.
9-11. Sketch the circuit of an operational amplifier connected to function
as a noninverting amplifier. Identify all terminals of the amplifier.
Derive the equation for voltage gain of the noninverting amplifier,
and write equations for input and output impedance.
9-12. Repeat Question 9-11 for an inverting amplifier.
9-13. Sketch the circuit of a class A transformer-coupled amplifier. Briefly
explain how it functions. Also derive an equation for the load
reflected from the secondary winding of transformer into the primary.
9-14. Sketch the basic circuit of a class B transformer-coupled output stage,
and briefly explain how it functions. Also explain the advantages of
class B operation over class A.
9-15. Sketch the complete circuit of a class AB transformer-coupled ampli-
fier with a class A driver stage. Explain how the circuit operates, and
explain the advantage of class AB operation over class B operation.
9-16. Sketch the circuits of npn and pnp Darlington pairs. Identify all
currents, and derive the equation for the current gain of the Darling-
ton pair.
227
Review
Questions
228
Problems
Problems
9-17. Sketch the circuit of a complementary emitter follower. Explain how
it functions and what its advantages are over an ordinary emitter
follower.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
Design a two-stage capacitor-coupled small-signal amplifier to meet
the following specification: supply voltage = 25 V, /, = 75 Hz, A v =
large as possible. Use 2N3904 transistors and make I c = 1.5 mA.
A two-stage capacitor-coupled amplifier uses 2N3904 transistors with
7 C = 2 mA and Vcc = 1 5 V. Design the circuit to have the largest
possible gain and to have /, = 150 Hz. Use emitter current bias for
each stage.
Repeat Problem 9-2 using collector-to-base bias for each stage.
A dc feedback pair is to operate from a supply of 15 V. Using
transistors with = 75 and h u — 1.5 k 0, design the circuit to
have I c = 0.9 mA. Make /, = 200 Hz.
Using 2N3904 transistors with Vcc — 20 V and I c = 1 mA, design a dc
feedback pair with f x = 250 Hz.
The differential amplifier in Fig. 9-5 has R LX = /? L2 = 4.7 kfl, R E = 2.2
k fl, V cc = 20 V, and V B = S V. Taking ^ = 0.7 V, calculate V cl and
Vc*
For the circuit described in Problem 9-6, calculate the single-sided
voltage gain, common mode gain, input impedance, and output
impedance. Take h u = 1 .5 kfl, h fe = 75, and h oe = 1 X 10“ 6 S.
The CA3002 IC amplifier shown in Fig. 9-1 1 has its supply and bias
voltages connected as follows: V cc (at terminal 9)= + 10 V, V EE (a,
terminal 2) = — 10 V, V (at terminal 1 ) = — 5 V, V (at terminal 7) = 0
V, and V (at terminals 5 and 1 0) = 0 V. Calculate the output voltage
at terminal 8.
An operational amplifier used as a voltage follower has a typical
open-loop gain of 200,000. If the maximum input signal voltage is
exactly 8 V, calculate the level of maximum output.
Design a noninverting amplifier using a fxA741 operational amplifier.
The output voltage from the circuit is to be ±5 V when the input
signal is ± 75 mV.
A noninverting amplifier uses an operational amplifier with an input
bias current of 750 nA. Design the circuit to have a voltage gain of
An inverting amplifier using a jnA741 operational amplifier is to have
a voltage gain of 200. The input signal voltage is 45 mV. Calculate
suitable resistor values, and determine the circuit input impedance.
An inverting amplifier is to have an input impedance of 1 kS2. When
the signal voltage is ±100 mV, the output is to be ±3.3 V.
Determine suitable resistor values.
9-14. A class A transformer-coupled amplifier, as in Fig. 9- 18(a), has
V cc = 20 V. The bias resistors are /?, = 3.9 k!2 and /? 2 = 1 k!2, and the
emitter resistor is R 3 = 68 12. The transformer has a primary winding
resistance of = 32 12, jV, = 80, and N 2 = 20. The load resistance is
R l = 23 12. Plot the dc load line and ac load line for this circuit on
blank characteristics with vertical ordinate as / c = (0 to 100 mA) and
horizontal ordinate V CE = (0 to 40 V).
9-15. A class B transformer-coupled amplifier, as in Fig. 9-2 1(a), uses a
transformer which has total primary turns of = 160 and jV 2 = 20.
The load resistance is R L = 23 12, and the total primary winding
resistance is R py = 64 12. Using blank characteristics with 7 C = (0 to 100
mA) and ^CE = (0 to 40 V), plot the complete ac load line for the
circuit.
9-16. A class B amplifier is to supply 8 W to a 12-12 load. The supply is
^cc = 25 V. Specify the output transformer and transistors.
9-17. A class B amplifier uses a transformer with / A^ 2 = 5 (where N t is
the total number of primary turns on a center-tapped primary). The
supply voltage is 45 V, and the load resistance is 8 12. Determine the
maximum output voltage and power from the circuit, and specify the
maximum transistor voltage, current, and power dissipation.
9-18. A Darlington pair has a load resistance of R L = 120 12, which is to be
supplied with 6 V. The output transistor has h FE = 25, and the input
transistor has ^^ = 50. The circuit supply is F , cc = 25 V. Calculate
the input current, input voltage level, and the power dissipated in
each transistor.
229
Problems
CHAPTER
10
Basic
Sinusoidal
Oscillators
10-1 A sinusoidal oscillator consists basically of an amplifier and a phase-
introduction shifting network. The amplifier receives the output of the phase-shifting
network, amplifies it, phase shifts it through 180° and applies it to the input
of the network. The network phase shifts the simplifier output through
another 180° and attenuates it before applying it back to the amplifier
input. When the amplifier gain and phase shift are equal to the network
attenuation and phase shift, the circuit is amplifying an input signal to
produce an output which is attenuated to become the input signal. The
circuit is generating its own input, and a state of oscillation exists.
For oscillation to be sustained certain conditions, known as the
Barkhausen criteria , must be fulfilled. These are the loop gain of the circuit must be
equal to (or greater than ) 1, and the phase shift around the circuit must be zero.
10-2
Phase-
Shift
Oscillator
In the phase-shift oscillator an external resistor-capacitor (RC)
network feeds a pordon of the ac output of an amplifier back to the
amplifier input. If the amplifier has an internal phase shift of 180° and the
230
network provides a further 180° phase shift, the signal fed back to the input
can be amplified to reproduce the output. The circuit is then generating its
own input signal, and a state of oscillation is sustained.
Figure 10-1 shows an IC operational amplifier connected as an invert-
ing amplifier (see Section 9-6) to give a 180° phase shift between amplifier
input and output. An RC network consisting of three equal-value capacitors
and three equal resistors is connected between the amplifier output and
input terminals. Each stage of the network provides some phase shift to give
a total of 180° from output to input.
The frequency of the oscillator output depends upon the capacitor and
resistor values employed. Using basic RC circuit analysis methods, it can be
shown that the network phase shift is 180° when the oscillating frequency’ is
2t tRCV6
( 10 - 1 )
231
Phase-
Shift
Oscillator
Fed back
voltage
Figure 10-1. Phase-shift oscillator using an IC operational amplifier
232
Basic
Sinusoidal
Oscillators
Figure 10-2. Transistor phase-shift oscillator.
As well as phase shifting, the RC network attenuates the amplifier
output. Network analysis shows that, when the necessary 180° phase shift is
achieved, this network always attenuates the output voltage by a factor of
29. This means that the amplifier must have a voltage gain of at least 29 for
the circuit to oscillate. For example, if the output amplitude is ± 2.9 V, the
feedback voltage is K = (± 2.9/29)= ±100 mV. To reproduce the ± 2.9-V
output, V t must be amplified by a factor of 29.
The amplifier gain of A 0 = 29 and network attenuation of /? = 29 give a
loop gain of fiA v = \. Also, the amplifier phase shift of 180° combined with
the network phase shift of 180° gives a loop phase shift of zero. Both these
conditions are necessary to satisfy the Barkhausen criteria.
Another phase-shift oscillator circuit is shown in Fig. 10-2. In this case
a single common emitter transistor amplifier stage is employed. The com-
mon emitter circuit has 180° phase shift between input and output, and the 233
RC network phase shifts the output to reproduce the necessary input. Once ^hift
again the amplifier must have a voltage gain of at least 29. Note that the Oscillator
amplifier input resistance (Z) forms the last resistor of the RC network.
The input impedance of the RC network loads the amplifier, and
(especially in the circuit of Fig. 10*2) this affects the amplifier gain. As
frequency increases, the capacitor impedances decrease, so that the loading
effect is greatest at high frequencies. When the loading effect reduces the
amplifier gain below 29, the circuit will not oscillate. It is found that the
phase-shift oscillator is most suitable for frequencies ranging up to a maxi-
mum of about 100 kHz.
An external load can also reduce the amplifier gain and cause the
circuit to cease oscillating. Because the operational amplifier circuit in Fig.
10-1 has a very low output impedance, it is less likely to be affected by
overloads than the circuit of Fig. 10-2.
If the amplifier gain is much greater than 29, the oscillator output
waveform is likely to be distorted. When the gain is slightly greater than 29,
the output is usually a reasonably pure sine wave.
The amplitude of the output waveform depends upon the supply
voltage and the amplifier bias conditions. The output voltage of the opera-
tional amplifier tends to go to approximately 1 V below the supply voltage
levels. For example, if the supply is ± 15 V, then the oscillator output (for
Fig. 10-1) is likely to be approximately ± 14 V. In the case of the circuit in
Fig. 10-2, the output is likely to be — ^CE or 3 . whichever is least.
Design of a phase-shift oscillator commences with design of the ampli-
fier to have a voltage gain slightly greater than 29. In the case of the
transistor circuit, final selection of the load resistor ( R 3 in Fig. 10-2) may
have to wait until the attenuator input impedance can be estimated to take
account of its loading effect. The network resistor value ( R ) is determined by
considering the amplifier input impedance. Then the capacitor value is
calculated using Eq. (10-1).
Using a /Li.A74 1 1C operational amplifier, with I ^cc = + 10 V, design a Example 10-1
phase-shift oscillator to have an output frequency of 1 kHz.
solution
amplifier
and
234
Basic
Sinusoidal
Oscillators
For the /*A741, /g (max ) = 500 nA.
Let
/j« 100 X / 5
= 100X50 nA = 50 juA
^o«±(^cc-l V)=±(10V-1)=±9V
and
9 V
1 /, 29 X 50 ju, A
«6.2 kfi (use 5.6-kfi standard resistor value; see Appendix 1)
R 2 = A D X 7?! = 29X5.6 kfi
» 162 kfi (use 180-k£2 standard value to give A v > 29)
*3 = *lll*2~ 5 -6 kfi
RC network
Amplifier Z t = R l = 5.6 k£2
To ensure that R y does not load R significantly, make R<R V
Let /? — .ft 1 /10 = 560 Q.
From Eq. (10-1),
2wR/V6
2irX560«Xl kHzV6
= 0.1 16 juF (use 0. 12-juF standard capacitor value; see Appendix 2)
10-3
Colpitts
Oscillator
The Colpitts oscillator circuit shown in Fig. 10-3 uses an LC network (C,,
C 2 , and L) to provide the necessary phase shift between amplifier output
voltage and feedback voltage. In this case the network acts as a filter to pass
the desired oscillating frequency and block all other frequencies. The filter
circuit resonates at the desired oscillating frequency. For resonance,
X L ~ %ct
where X CT is the reactance of the total capacitance in parallel with the
Fed back
voltage
Figure 10-3. Colpitts oscillator using an 1C operational amplifier.
235
Colpitts
Oscillator
inductance. This gives the resonance frequency (and oscillating frequency)
as
/ )= (> 0 - 2 )
2irVLC r
where
C T -
^ 1^2
C\ + c 2
00-3)
Consideration of the LC network shows that its attenuation (from the
amplifier output to input) is
x,-x r
236
Basic
Sinusoidal
Oscillators
Example 10-2
It can be shown that when the 180° phase shift is achieved (X L — X CI ) = X C2 .
This gives /3 = X ci j X C2 . For the loop gain to equal 1, f$A v = 1, and
> 1 (10-4)
A C2
As for other oscillator circuits, the loop gain should be greater than
unity to ensure that the circuit oscillates. Also, as before, the output
waveform is likely to be severely distorted when A v is much larger than
X C i/X C2 ' (In more complex circuits a method of stabilizing the output
amplitude may be employed.)
Design of a Colpitts oscillator might commence with the choice of
values for C, and C 2 much larger than any stray capacitance. should
also be much larger than the amplifier output impedance. Using the desired
oscillating frequency, the inductance L can be calculated using Eqs. (10-2)
and (10-3). The inductance should be as purely inductive as possible at the
specified oscillating frequency; i.e., the Q factor (coL ) / R should be as large
as possible. The minimum circuit gain is determined from Eq. (10-4). R i is
selected large enough to avoid overloading *c, (i.e., R , »Jf CI ). Then R 2 is
determined from A v and R v
Design a Colpitts oscillator to give /= 4 kHz. Use a juA741 IC
operational amplifier with V cc =±10 V.
solution
A" C 2» than any stray capacitance; take C 2 = 0.1 /iF and let = C 2 . Use Eq.
(10-3):
_ c,c 2 _ 0.1 juFXO.l ju,F
r_ C x + C 2 ~ 0.1 /xF + 0.1 JxF
= 0.05 /xF
At /= 4 kHz,
C2 2tt X 4 kHz X 0. 1 ixF
= 398 fi
and the /i A741 has Z 0 « 70
X C2 ^ > Zq
From Eq. (10-2), 237
Hartley
1 Oscillator
47T 2 f 2 C T
4tt 2 X(4 1cHz) 2 X0.05 pF
^32 mH
A, > ( X C JX C2 ) > 1. Make A,s*s 4.
>*c.
Let
For ^ = 4,
/?«100X* C ,= 100X398
»39 kfl (standard value)
*2 = 4 /?,
= 4X39 ktt
= 156 kfi (use 150-ktt standard value)
A Colpitts oscillator using a single-stage transistor amplifier is shown in
Fig. 10-4(a). This is the basic circuit, and its similarity to Fig. 10-3 is fairly
obvious. A more practical version of the circuit is shown in Fig. 10-4(b).
Here (),, /?,, /? 2 , /? 4 , and C 3 are unchanged from Fig. 10-4(a). However, in
(b) L has replaced the load resistor R v A radio frequency choke (RFC) is
included in series with ^cc and L. This allows direct current I c to pass, but
offers a very high impedance at the oscillating frequency. The upper end of
L is ac isolated (by RFC) from V cc and ground. The output of the
phase-shifting network is coupled via C ( from the junction of L and C, to the
amplifier input at (), base. The output voltage V 0 is derived from a
secondary winding L 2 coupled to the inductance L.
The Hartley oscillator circuit is similar to the Colpitts oscillator, except
that the phase-shift network consists of two inductors and a capacitor instead
of two capacitors and an inductor.
10-4
Hartley
Oscillator
238
Basic
Sinusoidal
Oscillators
(b) Practical circuit
Figure 1(M. Transistor Colpitts oscillator.
Figure 10-5(a) shows the circuit of the Hartley oscillator, and Fig.
10-5(b) illustrates the fact that L x and L 2 may be wound on a single core, so
that there is mutual inductance between them. In this case the total
inductance is given by
L T — L, + L 2 + 2M
( 10 - 5 )
where M is the mutual inductance.
As in the case of the Colpitts circuit, the frequency of oscillation is the
resonance frequency of the phase-shift network.
/ )=r (10-6)
27 tVCL t
The attenuation of the phase shift network is
/? =
Once again, for a 180° phase shift (X Ll — X c ) can be shown to equal ^2-
6^6
239
Hartley
Oscillator
C
1 1
— r ‘0‘Ott‘gOO(T
1 -
(b) Phase shift network with
Z., and Z. 2 wound on a
single core
Figure 10-5. Hartley oscillator using an 1C operational amplifier.
For the loop gain to be at least 1,
X,.
A.y 1 > ' (10-7)
The circuit design procedure for a Hartley oscillator is basically similar to
that for the Colpitts circuit.
The circuit of a transistor Hartley oscillator is shown in Fig. 10-6.
Figure 10-6(a) gives a basic circuit in which the phase-shift network and
amplifier are easily identified as distinct separate stages of the oscillator. In
Fig. 10-6(b) a practical circuit is shown. L,, Z. 2 * an< ^ C constitute the phase
shift network, and here the inductors are directly connected in place of the
(a) Basic circuit (b) Practical circuit
Figure 10-6. Transistor Hartley oscillator.
amplifier load resistance. The radio frequency choke (RFC) passes the direct
collector current, but at oscillating frequencies isolates the upper terminal of
L, from the supply voltage. Capacitor C x couples the output of the phase-
shift network back to the amplifier input, as in Fig. 10-6(a). Capacitor C 2 in
Fig. 10-6 (a) is no longer required in the circuit of Fig. 10-6 (b), because L 2
is directly connected to the amplifier. However, because of the direct
connection, the junction of L x and L 2 cannot now be directly grounded.
Instead, another coupling capacitor C 4 is used.
10-5
Wein
Bridge
Oscillator
The Wein bridge is an ac bridge in which balance is obtained only at a
particular supply frequency. In the Wein bridge oscillator , the Wein bridge is
used as the feedback network between input and output.
In Fig. 10-7 (a) the bridge components are R v R 2 , R 3 , R 4 , C,, and C 2 .
Analysis of the bridge circuit shows that balance is obtained when two
equations are fulfilled:
_ R^ + C'
2 tt/=
\/ c x r 2 c 2
( 10 - 8 )
(10-9)
240
+ v cc
(b) Showing that the circuit consists
of a feedback network and a
noninverting amplifier
Figure 10-7. Wein bridge oscillator.
241
242
Basic
Sinusoidal
Oscillators
Example 10-3
If — R 2 — R> and C, = C 2 = C, Eq. (10-9) yields
f= 2^CR
and from Eq. (10-8),
R 3 = 2R 4 (10-11)
The oscillator circuit is redrawn in Fig. 10-7 (b), showing that the
operational amplifier and resistors R 3 and R 4 constitute a noninverting
amplifier (see Section 9-6). C,, R lt C 2 , and R 2 are seen to be a feedback
network connected from the amplifier output back to the noninverting
input. At the resonant frequency of the Wein bridge, the fed back voltage is
in phase with the output. Since this (in phase) voltage is applied to the
noninverting input, it is amplified to reproduce the output. At all other
frequencies the bridge is off balance; i.e., the fed back and output voltages
do not have the correct phase relationship to sustain oscillations. The
Barkhausen criteria for zero loop phase shift is fulfilled in this circuit by the
amplifier and feedback network each having zero phase shift.
The design of a Wein bridge oscillator can be approached by first
selecting a current level for each bridge arm. This should be much larger
than the input bias current to the operational amplifier. R 3 + R 4 can then be
calculated using an estimated output voltage, and the other circuit compo-
nents can be determined using Eqs. (10-10) and (10-11).
Design a Wein bridge oscillator to have an output frequency of 10
kHz. Use a juA741 operational amplifier with V cc — ± 10 V.
solution
Amplifier maximum input current is I B = 500 nA. Let / 4(through r 4) = 500 juA
output voltage «±(K CC -1V)-±9V
Then
/?3 + 7? 4 =
9 V
500 /xA
= 18k ft
Use Eq. (10-11): R 3 = 2R 4
3R 4 = 18 k£2
and
18 k£2
R 4 = — - — =6 k£2 (use 5.6-kfi standard value)
The lower-than-calculated value for R 4 makes
/ 4 > 500 /xA
R 3 = 2R 4 = 2X5.6 kfl
= 11.2 k& (use 12-kfi standard value)
This will make R 3 >2R 4 (and A 0 >3).
Let R 2 = R 4 = 5.6 kfi. Then R t = R 2 = 5 . 6 ktt = R.
From Eq. (10-10),
C = 2-nfR
C ' = C 2 =C= 2 t x 10 kHzX5.6 k$2
= 2842 pF (use 2700-pF standard capacitor value)
Barkhausen criteria. States that for an oscillator the loop gain must be
greater than 1, and that the phase shift must be zero.
Phase-shift oscillator. Uses a CR network to phase shift the amplifier
output.
Loop gain. Circuit gain from the amplifier input to output, and through
the phase-shifting network back to the amplifier input.
Colpitts oscillator. Uses a phase-shifting network consisting of two capaci-
tors and one inductor.
Hartley oscillator. Uses a phase -shifting network consisting of two induc-
tors and one capacitor.
Wein bridge oscillator. Uses a Wein bridge as the feedback network.
10-1. State the Barkhausen criteria , and explain why they must be fulfilled for
a circuit to sustain oscillations.
10-2. Sketch the circuit of a phase-shift oscillator using an operational
amplifier. Briefly explain how the circuit operates and how it fulfills
the Barkhausen criteria.
10-3. Sketch the circuit of a phase-shift oscillator using a transistor ampli-
fier circuit. Briefly explain how the circuit operates, and state the
equation for oscillating frequency.
243
Review
Questions
Glossary of
Important
Terms
Review
Questions
244
Basic
Sinusoidal
Oscillators
Problems
10-4. Repeat Question 10-2 for a Col pitts oscillator.
10-5. Repeat Question 10-3 for a Colpitts oscillator.
10-6. Repeat Question 10-2 for a Hartley oscillator.
10-7. Repeat Question 10-3 for a Hartley oscillator.
10-8. Repeat Question 10-2 for a Wein bridge oscillator.
10-1. Design a phase-shift oscillator to have an output frequency of ap-
proximately 3 kHz. Use a /xA741 operational amplifier with F cc —
±12 V.
10-2. A phase-shift oscillator is to use three 0.05- juF capacitors and a
/x A741 operational amplifier with Vcc=± 9 V. Design the circuit to
have f—1 kHz.
10-3. Redesign the circuit of Problem 10-1 to use a single-stage transistor
amplifier. Use a 2N3904 transistor with V cc = 15 V.
10-4. Repeat Problem 10-1 for a Colpitts oscillator.
10-5. A Colpitts oscillator is to be designed to have /« 5.5 kHz. An
inductor with L = 20 mH and a juA741 operational amplifier are to
be employed. Using v cc = ± 18 V, complete the circuit design.
10-6. Design a Wein bridge oscillator using a juA741 operational amplifier
with v cc= ± 14 V. The output frequency is to be 15 kHz.
10-7. A Wein bridge oscillator is to have an output frequency of 9 kHz.
Two 5000-pF capacitors and a juA741 operational amplifier are to be
employed. Complete the circuit design using V cc = ± 12 V.
Zener Diodes
When an ordinary silicon junction diode is reverse biased, normally
only a very small reverse saturation current ( I s ) flows. If the reverse voltage
is increased sufficiently, the junction breaks down and a large reverse current
flows. This current could be large enough to destroy the junction. If the
reverse current is limited by means of a suitable series resistor, the power
dissipation at the junction will not be excessive, and the device may be
operated continuously in its breakdown condition. When the reverse bias is
reduced below the breakdown voltage, the current returns to its normal I s
level. It is found that for a suitably designed diode, the breakdown voltage is
a very stable quantity over a wide range of reverse currents. This quality
gives the breakdown diode many useful applications as a voltage reference
source.
There are two mechanisms by which breakdown can occur at a
reverse-biased /^-junction. These arc Zener breakdown and avalanche breakdown.
Either of the two may occur independently, or they may both occur at once.
Zener breakdown usually occurs in silicon /^-junctions at reverse
biases of less than 5 V. Under the influence of a high-intensity electric field,
CHAPTER
11
11-1
Introduction
11-2
Zener and
Avalanche
Breakdown
245
246
Zener
Diodes
Electrons pulled out
of atoms by high intensity
electric field
Depletion
region
Applied potential
{reverse bias)
Figure 11-1. Ionization by electric field; Zener breakdown.
large numbers of electrons within the depletion region break the covalent
bonds with their atoms (see Fig. 11-1). This is ionization by an electric field , and
when it occurs the presence of the free electrons converts the depletion
region from a material which is almost an insulator into one which is
effectively a conductor. Thus, a large (reverse) current can be made to flow
across the junction.
Since
Electric field strength =
reverse voltage
depletion region width
a small reverse voltage can produce a very high intensity electric field within
a narrow depletion region. Thus, the narrower the depletion region, the
smaller the Zener breakdown voltage. The actual intensity of the electric
field strength that produces Zener breakdown is estimated as 3 X 1 0 5 V/ cm.
With lightly doped semiconductor material, some depletion regions are
too wide for Zener breakdown to occur even with a 5-V reverse bias. With
sufficient increase in reverse bias, Zener breakdown occurs even for rela-
tively wide depletion regions. However, when the reverse bias exceeds
approximately 5 V, another form of reverse breakdown occurs before the
field intensity becomes great enough to cause electrons to break their bonds.
Recall that the reverse saturation current I s which flows across a
reverse-biased /m-junction is made up of minority charge carriers. The
velocity of the minority carriers is directly proportional to the applied bias
voltage. Hence, when the reverse-bias voltage is increased, the velocity of the
minority charge carriers is increased, and consequently their energy content
is also increased. When these high-energy charge carriers strike atoms within
Charge carrier
striking atom
knocks out other
charge carriers,
ionization by
collision
Incident minority
charge carriers
Charge carriers knocked out
/of atom causes further
ionization by collision
Figure 11-2. Ionization by collision; avalanche breakdown.
247
Zener Diode
Characteristic
and
Parameters
the depletion region, they cause other charge carriers to break away from
their atoms and join the flow of current across the junction (Fig. 1 1-2). This
effect is termed ionization by collision. The additional charge carriers generated
in this way are also accelerated to a high energy state and can cause further
ionization by collision. The number of charge carriers avalanches and the
result is avalanche breakdown. As in the case of Zener breakdown, the depletion
region material is converted from a near insulator into a conductor. Here
again a large (reverse) current can be made to flow across the junction.
A typical Zener diode characteristic is shown in Fig. 1 1-3. The forward
characteristic is simply that of an ordinary forward-biased junction diode.
The important points on the reverse characteristic are
V z = Zener breakdown voltage
IzT = test current at which V z is measured
IZK — Zener current near the knee of the characteristic; the minimum Zener current
necessary to sustain breakdown
11-3
Zener
Diode
Characteristic
and
Parameters
I zm = maximum Zener current; limited by the maximum power dissipation
Cathode
Anode
(a) Zener diode symbol
(b) Zener diode equivalent circuit
Figure 11-4. Zener diode symbol and equivalent circuit.
A very important parameter derived from the characteristic is the Zener
dynamic impedance (Z z ), which defines how V z varies with change in I z . Z z is
determined by measuring the reciprocal of the slope of the characteristic, as
shown in Fig. 1 1-3:
Figure 11-4 shows the Zener diode circuit symbol and the equivalent
circuit for the device. The equivalent circuit, which represents the diode
only in its breakdown condition, is simply a battery of voltage V z in series
with a resistance of Z z .
IN 746 thru IN 759
1 N4370 thru 1N4372
400 mW
2.4 —12 V
Hermetically sealed, all -glass case with alt external
surfaces corrosion resistant. Cathode end, indicated
by color band, will be positive with respect to anode end
when operated in the zener region.
MAXIMUM RATINGS
Junction and Storage Temperature: -65-°C to +175°C
D-C Power Dissipation: 400 Milliwatts at 50°C Ambient (Derate 3.2 mW/°C
Above 50° Ambient)
TOLERANCE DESIGNATION
The type numbers shown have tolerance designations as follows:
1N4370 series: * 10%, suffix A for ± 5% units.
1N746 series: ± 10%, suffix A for ± 5% units.
ELECTRICAL CHARACTERISTICS < T» = 25*C unteu other-. w noicJ)
249
Zener Diode
Characteristic
and
Parameters
Figure 11-5. Zener diode specifications. (Courtesy of Motorola, Inc.)
250
Zener
Diodes
1N3993 thru IN 4000
10 w
3.9 -7.5 V
Low-voltage, alloy -junction zener diodes in hermeti-
cally sealed package with cathode connected to case.
Supplied with mounting hardware.
MAXIMUM RATINGS
Junction and Storage Temperature: -65°C to +175° C.
D-C Power Dissipation: 10 Watts.(Derate 83.3 raW/°C above 55°C).
The type numbers shown in the table have a standard tolerance on the nominal
zener voltage of ±10%. A standard tolerance of ±5% on individual units is also
available and is indicated by suffixing M A" to the standard type number.
ELECTRICAL CHARACTERISTICS (T» = 30'C ± 3. W = 1.5 max @ U = 2 amp for all unils)
TypiNo.
Nominal
ZanarVottafa
V, @ L
Volts
Tost
Current
In
mA
Mu Zonor Impodanco
Mu OC Zoom
C arrent
UmA
KVM St
IEJUUCE CUttMT
V.
U*A}V#ftS
Zit @ In
Ohms
= 1.0 mA
Ohms
1N3993
3.9
640
2
400
2380
100
0.5
1N3994
4.3
580
1.5
400
2130
100
0.5
1N3995
4.7
530
1.2
500
1940
50
1
1N3998
5.1
490
1.1
550
1780
10
1
1N3997
5.8
445
1.0
800
1820
10
1
1N3998
6.2
405
1.1
750
1460
10
2
1N3999
6.8
370
1.2
500
1330
10
2
1N4000
7.5
335
1.3
250
1210
10
3
Figure 11-5. ( cont .)
Referring to the Zener diode data sheets (Fig. 11-5), it is seen that for
low-power devices (IN746 to IN 759) typical values of Z ^ range from 5 to
30 £2. For high-power devices(IN3993 to IN4000),the range of Z^j- is only 1 to
2 £2. Note that Z^is measured at the test current 1^ which is much greater
than the current near the knee. The Zener impedence near the knee of the
characteristic (Z^) is much larger than ZzT ‘
Referring again to the data sheets, note that a Zener voltage tolerance
of ±5% or ±10% is specified. This means, for example, that the actual
Zener voltage of a IN753 is 6.2 V ± 10%. The value of V z will remain stable
at whatever voltage it happens to be within this range.
The maximum power dissipation for each type of device is listed on the
data sheet for a specified maximum temperature. At higher temperatures the
maximum power dissipation must be derated exactly as for transistors (see
Section 8-3).
Silicon diode
(with negative
temperature
coefficient)
t t
- V F
Zener diode
(with positive
temperature
coefficient)
Figure 11-6. Construction of a compensated reference diode.
For Zener breakdown ()^<5 V), the temperature coefficient ( a z ) of the
breakdown voltage is negative. For a given value of I z> V z decreases slightly
when the temperature is increased. This is because, as the temperature
increases, the valence electrons of the atoms within the depletion region are
raised to a higher energy level, and are therefore more easily extracted from
their atoms.
In avalanche breakdown, relatively wide depletion regions are in-
volved. Consequently, charge carriers crossing the depletion region experi-
ence many collisions with atoms, and as temperature increases the atoms
vibrate and impede the progress of the charge carriers. Therefore, to
maintain a given current, V z must increase slightly when the temperature
increases. This effect gives avalanche breakdown a positive temperature
coefficient.
To produce reference voltages with very small temperature coefficients,
compensated reference diodes are constructed as shown in Fig. 11-6. A
forward-biased silicon diode is connected in series with a breakdown diode
which has a positive temperature coefficient. The negative temperature
coefficient of the silicon diode partially cancels the breakdown diode’s
positive temperature coefficient. With this arrangement, temperature coef-
ficients of better than 0.0005%/° C are possible.
A breakdown diode has F z = 6.2 V at 25° C, and a z = -f-0.02%/° C. A
silicon diode with F f = 0.7 V and a temperature coefficient of — 1.8 mV/ 0 C
is connected in series with the breakdown diode. Find the new value of
reference voltage and the temperature coefficient of the combination. Also
calculate the new value of at a temperature of 50° C.
solution
a z = +0.02% of V z for each°C temperature change
V z change = + 6,2 1 ^° ° 2 V/° C - + 1.24 mV/° C
251
Compensated
Reference
Diodes
11-4
Compensated
Reference
Diodes
Example 11-1
252
Zener
Diodes
Combined V z and V F change is
( + 1.24-1.8) mV/° C= -0.56 mV/° C
New value of K,, ^
V z + V f = 6.2 V + 0.7 V = 6.9 V
new temperature coefficient = —0.56 mV/ 0 C
= -0.00056X100
6.9
%/° C= -0.008%/° C
The value of F ref at 50° C
= 6.9 V — [0.56 mV X (50° C-25° C)]
= 6.9 V— 14 mV = 6.886 V.
11-5
Zener
Diode
Voltage
Regulator
11 - 5.1 Figure 11-7 shows the simplest possible form of voltage regulator
Regulator circuit, a Zener diode connected in series with a resistor R s . The resistor
Design limits the total current flowing to the diode and the load. The load is
connected across the diode, so that
Vr=Vs~Vz
Apart from small variations due to AF Z , I R will remain constant. Since
Ir = Iz +
vwv
+
-hh '-1
l
k V
f 4
O ^
o
Figure 11-7. Simple Zener diode voltage regulator.
When the load is not connected, I L = 0: 253
Zener
Ir~ ?Z{ m«) Diode
Voltage
Therefore, the Zener diode must be capable of passing all the current Regulator
I R . Also, for the diode to remain in breakdown, l z must not be permitted to
fall below a minimum level / Z(tnin ). The maximum value of load current is
/ z.(m*x) = 7 /? _/ Z(min)- 7 z ( m«) cf n be 7^, the maximum value of l z as limited
by maximum power dissipation. 7 Z(min) could be the value of I z near the knee
of the characteristic, I ZK . However, Z z becomes very large at 7 za> so it is best
to keep 7 Z(min) much larger than 7^.
Design a simple Zener regulator circuit to supply approximately 6 V Example 11-2
from a 15-V source. Calculate the minimum value of load resistor that may
be connected across the output terminals. The circuit is to operate at an
ambient temperature of 25° C.
solution
Consulting the Zener diode data sheets (Fig. 11-5), it is seen that a 1N753
has a nominal V z of 6.2 V. Therefore, using a IN 753, the voltage across R s
(Fig. 11-7) is
V R = V s - = 1 5 V — 6.2 V = 8.8 V
From the data sheet,
I z\i 60 mA
V R = 8.8 V
, Vr _ 8.8 V
5 I R 60 mA
147 £2
Power dissipation is R s = Vr'XI r = 8.8 VX60 mA = 0.53 W. R s should
be a 1W resistor.
I ZK is not specified for the 1N753, but a typical value of 1^ is 1 mA.
I Zimin) should be much greater than 1^.
Thus, make 7 Z(min) = 10 X I ZK = 10 mA.
4( max) = Ir — 7 Z(m in)
= 60 m A — 1 0 mA
= 50 mA
The minimum value of R L is R L ^ n y where
R - V * - 6 2 V
Wmi " ) /««.) 50 mA
124 »
11-5.2 Apart from output voltage and maximum load current, the perfor-
Regulator mance of a voltage regulator may be specified in terms of the stabilization ratio
Performance ( 5 ^) and the output impedance (Z G ).
S v is a measure of how the output voltage varies with changes in input
voltage.
The ideal value of is zero.
Z 0 defines how V Q varies with variations in load current I L .
z 0 —
A Vo
Ml
To calculate S y and Z 0 , consider the ac equivalent circuit for the
regulator (Fig. 11-8). The equivalent circuit is drawn simply by replacing
the diode with its Zener dynamic impedance (Z z ).
From Fig. 11-8, when V s changes by A Vs, K changes by A V Q .
and
A V 0
Zz
R s + Zz
XA V s
(1M)
^z
R s + Z z
(H-2)
The output impedance (also from Fig. 11-8) of the regulator is the
impedance “seen” when looking into the output terminals. Since the source
resistance of V s is likely to be much smaller than R$>
Z 0 ^Z z \\R s =^Y s («- 3 )
64.5 mA
Figure 11-6. AC equivalent circuit for Zener diode voltage regulator.
254
Calculate the values of stabilization ratio and output impedance for
the regulator designed in Example 11-2.
solution
For the 1N753 diode, Z z = 7 £2 (Fig. 11-5).
From Eq. (11-2),
Sv-
7fl
147 S2 + 7
=0.045
This means, for example, that if V s increases or decreases by 1 V, V Q
change would be
AV 0 = S y X AF 5 = 45 mV
From Eq. (11-3),
Example 11-3
z o =
7X147
7 + 147
S] = 6.7 S2
Therefore, when I L varies by ± 10 mA, for example, V 0 will change by
A K 0 = X AI l = ±67 mV
The regulator performance can also be defined in terms of the line
regulation and the load regulation. The line regulation is just another way of
expressing the voltage stabilization ratio, and the load regulation is another
method of stating the circuit output impedance.
For a given V s change (e.g., 10%), the resultant change in V Q is
expressed as a percentage of the normal V Q level:
line regulation =
(A V Q for a given A F 5 ) X 100%
% :
(H-4)
For a given change in load current (usually from no load to full load),
W 0 is expressed as a percentage of the normal V 0 level:
load regulation =
(A V Q for a given A I L ) X 100%
y 0
(11-5)
For the regulator referred to in Examples 1 1-2 and 1 1-3, determine the Example 11-4
line regulation for a 10% change in input voltage. Also determine the load
regulation for a load current change from no load to full load.
255
256
Zener
Diodes
solution
From Eq. (11-4),
Full load current
AFy=10%of V s =\0%oi 15 V
= 1.5 V
AF o = 5 r xAF 5 = 0.045X1.5 V
= 67.5 mV
AV 0
line regulation = — — X 100%
Fq
67.5 mV .
6.2 V
^ 1 . 1 %
- X 100%
I L = 50 mA
A I L = 50 mA — 0 = 50 mA
AV 0 = AI L X Z 0 = 50 mA X 6.7 12 =335 mV
From Eq. (11-5),
A V Q
load regulation = X 1 00%
Fq
335 mV
6.2 V
= 5.4%
X 100%
11-5.3 To improve the performance of the regulator, designed in Example
Two-Stage \ 1-2, an additional stage may be added giving the circuit shown in Fig. 1 1-9.
Regulator With two-stage regulation, the stabilization ratio becomes
4- Z 7
R~n + Z 7 <
R Uz,+i L + lz 2 ) r Uz, + A ) i L
-^ww
r .
°7'k V z.
l ‘Zy
t
Figure 11-9. Two-stage Zener diode voltage regulator.
(b) Usual circuit schematic for series regulator
(or emitter follower voltage regulator)
(a) Emitter follower voltage regulator
Figure 11-10. Emitter follower or series voltage regulator.
This affords a significant improvement over the stabilization ratio for a
single-stage regulator. The regulator output impedance, however, is not
improved. Z Q remains approximately equal to Z zx in parallel with R sl .
257
Other
Zener
Diode
Applications
When a low-power Zener diode is employed in the simple regulator
circuit described in Section 11-5, the load current is limited to low' values. A
high-power Zener used in such a circuit can supply the required load
current, but much power is wasted when the load is light. The emitter follower
regulator shown in Fig. 11-10 is an improvement on the simple regulator
circuit, because it draws a large current from the supply only when it is
required by the load. In Fig. 1 1- 10(a), the circuit is drawn in the form of the
common collector amplifier (emitter follower) discussed in Chapter 6. fn Fig.
1 1 -10(b), the circuit is shown in a form in which it is usually referred to as a
series regulator.
V 0 from the series regulator is ( — V BE ), and can be the
maximum l E that Q.i is capable of passing. For a 2N3055 transistor (specifi-
cation in Fig. 8-2), I L could approach 15 A. When I L is zero, the current
drawn from the supply is approximately [I z + /ctmin)]* The er niucr follower
voltage regulator is, therefore, much more efficient than a simple Zener
regulator.
11-6
Regulator
with
Reference
Diode
11-7
Other
Zener
Diode
Applications
The constant voltage characteristic of a Zener diode can be converted
into a constant current characteristic. The constant current circuit is shown
in Fig. 11-11. The voltage across &e~ K? Kb e-
'e =
11 - 7.1
Constant
Current
Circuit
( 11 - 6 )
258
Zener
Diodes
Example 11-5
Figure 11-11. Constant current circuit.
Since V z and V BE are normally constant quantities, I E also remains
constant, and I c zzI E . Therefore, I c remains substantially constant no matter
what the value of the collector voltage.
The only restriction on the circuit is that V C B must remain large
enough to keep operating in its active region; i.e., £)j must not become
saturated. The constant current circuit is widely applied.
The circuit in Fig. 11-11 uses a 1N755 Zener diode, and has F cc = 12
V, /?j = 220 £2, /? £ = 680 ft. If (), is a silicon transistor, calculate the
transistor collector current and the power dissipation in the Zener diode.
Also determine the new value of R E to give I c = 2.5 mA.
solution
From the Zener diode specifications in Fig. 11-5, the 1N755 has F z =7.5 V.
From Eq. (11-6),
/*-
7.5 V- 0.7 V
680 ft
10 mA
and
I c ~ I E = 10 mA
Neglecting 1 B
Vcc-Vz
12 V-7.5 V
220 ft
— 20.45 mA
Power dissipation in Z), is
259
Glossary of
P D = V z xl z = 7.5 V X 20.45 mA = 153 mVV ' mP ?ermI
For I c = 2.5 mA, I E ^ 2.5 mA.
From Eq. (11-6),
2.5 mA =
7.5 V-0.7 V
n 7.5 V-0.7 V
Re ~ 2.5 mA ~ 2 - 7kfi
Zener diodes are used extensively to protect other devices from exces-
sive voltages. In the circuit of Fig. 11-12, for example, the Zener diodes do
not operate while the peak input voltage remains below V z . When the input
peak exceeds V Zy one diode goes into breakdown while the other is forward
biased. Thus, the peak output is limited to (V z + V F ).
11 - 7.2
Over
Voltage
Protection
Zener breakdown. Reverse-biased /^-junction breakdown produced by Glossary of
high-intensity electric field. Important
Avalanche breakdown. Reverse-biased /^-junction breakdown produced
by collision of high-energy charge carriers with atoms.
Ionization by electric field. Removal of charge carriers from atoms by
effect of high-intensity electric field.
Ionization by collision. Removal of charge carriers from atoms by other
charge carriers colliding with the atoms.
V z , , Zener breakdown voltage.
7 Z . Test current at V z .
I ZK * Zener current near knee of characteristic.
Izm . Maximum Zener current.
*i
Figure 11-12. Zener diode overvoltage protection circuit.
260
Zener
Diodes
Review
Questions
Z z . Zener dynamic impedance.
Z ZT . Zener dynamic impedance at 1^.
%ZK' Zener dynamic impedance near knee of characteristic.
a z . Temperature coefficient of V z .
Compensated reference diode. Combination of Zener diode and forward-
biased diode to give improved temperature coefficient.
Sy. Voltage stabilization ratio of regulator.
Z Q . Output impedance of regulator.
Emitter follower regulator. Combination of transistor and Zener diode to
give improved efficiency regulator circuit.
Series regulator. Same as emitter follower regulator .
Constant current circuit. Combination of transistor and Zener diode to
give constant collector current.
Overvoltage protection circuit. Zener diode voltage limiter circuit.
11-1. Name and explain the two types of breakdown that can occur at a
reverse-biased /w-junction. Also state the important differences be-
tween the performance of breakdown diodes in which different
breakdown mechanisms are involved.
11-2. Sketch the characteristic of a Zener diode. Define and show how the
following quantities may be determined from the characteristic: V z ,
/ ZK » / ZM » anc ^
1 1-3. Sketch the schematic symbol for a Zener diode and show the polarity
of V z and I z . Also sketch and explain the equivalent circuit for a
Zener diode.
11-4. Draw a sketch to show how a compensated reference diode is con-
structed, and explain how the temperature coefficient is improved.
11-5. Sketch the circuit of a simple Zener diode voltage regulator. Briefly
explain how the circuit operates.
1 1 -6. Sketch the ac equivalent circuit for the simple Zener diode voltage
regulator. Derive the equations for Sy, Z 0 , line regulation, and load
regulation.
11-7. Sketch the circuit of a two-stage Zener diode voltage regulator
circuit. Explain the advantages of the circuit over the single-stage
regulator.
11-8. Sketch the circuit of an emitter follower voltage regulator. Explain
how the circuit operates and discuss its advantages over Zener diode
voltage regulators.
11-9. Sketch the circuit and explain the operation of the following:
(a) A Zener diode constant current circuit.
(b) A Zener diode overvoltage protection circuit.
Problems
11 - 1 . A Zener diode has V Z ~S.2 V at 25° C and a z = +0.05%/° C. A
silicon diode, which has V F = 0.6 V and a temperature coefficient of
— 2.2 mV/° C, is to be used with the Zener to construct a com-
pensated reference diode. Calculate the value of at 25° C and at
100° C. Also calculate the value of a z for the compensated reference
diode.
1 1-2. Design a simple Zener voltage regulator to supply approximately 5 V
from a 12-V source. Calculate the minimum value of load resistance
that may be connected across the output terminals if the circuit
operates at an ambient temperature of 55° C. Also calculate the
values of S y and Z 0 for the regulator.
11-3. Assuming a 10% input voltage change, determine the line regulation
of the circuit designed in Problem 11-2. Also calculate the load
regulation for a load current change from no load to full load.
11 - 4 . A Zener diode voltage regulator is to have an output of approxi-
mately 9 V. The available supply is 25 V, and the load current will
not exceed 1 mA. Design a suitable circuit, and calculate the output
voltage change when the input drops by 5 V and the load changes
from zero to 1 mA at the same time.
11 - 5 . A constant current circuit uses a 1N749 Zener diode in series with a
270-12 resistance. The supply to the Zener circuit is 10 V, and the
transistor is a silicon device. If /? £: = 330 12, calculate the value of the
constant collector current. Also determine the new value of R E to
make I c ^ 5.3 mA.
11 - 6 . The transistor in a constant current circuit is to have a collector
current of approximately 2 mA. Design a suitable circuit using a
20-V supply, and calculate the actual collector current level.
261
CHAPTER
12
12-1
Introduction
12-2
Principle
of the
n- Channel
JFET
Field
Effect
Transistors
Field effect transistors (FET) are voltage-operated devices. Unlike
bipolar transistors, FET’s require virtually no input current, and this gives
them an extremely high input resistance. There are two major categories of
field effect transistors, junction FET’s and insulated gate FET’s. These are
further subdivided into /^-channel and n -channel devices.
The operating principle of the n- channel junction field effect transistor
(JFET) is illustrated by the block representation in Fig. 12-1. A piece of
n-type material, referred to as the channel , has two smaller pieces of p - type
attached to its sides, forming /w-junctions. The channel’s ends are designated
the drain and the source , and the two pieces of p - type material are connected
together and their terminal is called the gate. With the gate terminal not
connected, and a potential applied (positive at the drain, negative at the
source), a drain current ( I D ) flows as shown in Fig. 12-l(a). When the gate is
biased negative with respect to the source [Fig. 12- 1(b)], the /w-junctions are
reverse biased and depletion regions are formed. The channel is more lightly
262
(a) No bias voltage
on gates
(b) Small negative
gate source
bias
(c) Large negative
gate source
bias
Figure 12-1. Principle of the n-channel JFET
doped than the p - type gate blocks, so the depletion regions penetrate deeply
into the channel. Since a depletion region is a region depleted of charge
carriers, it behaves as an insulator. The result is that the channel is
narrowed, its resistance is increased, and I D is reduced. When the negative
gate bias voltage is further increased, the depletion regions meet at the
center [Fig. 12-1 (c)], and I D is cut off completely.
When a signal is applied to the gate, the reverse voltage on the
junctions is increased as the signal voltage goes negative and decreased as it
goes positive. Consequently, as the signal goes negative the depiction regions
are widened, the channel resistance is increased, and the drain current
reduced. Also, as the signal goes positive the depletion regions recede, the
channel resistance is reduced, and the drain current is increased. As will be
seen in Chapter 20, the n-channel JFET is comparable to a triode vacuum
tube. The drain and source perform the same functions as the plate and
cathode, respectively; and, like the grid of a triode, the FET gate controls
drain current. As is also the case with a grid, gate current is to be avoided, so
the gate-channel junctions are normally never forward biased.
The name field effect device comes from the fact that the depiction
regions in the channel are the result of the electric field at the reverse- biased
gate-channel junctions. The term unipolar transistor is sometimes applied to
an FET, because unlike a bipolar transistor the drain current consists of only
one type of charge carrier, electrons in the n-channel FET and holes in the
p-channel device (Section 12-4).
The symbol for the n-channel JFET is show n in Fig. 12-2. As for other
types of transistors, the arrowhead always points from p to n. For an
n-channel device, the arrow-head points from the />-typc gate toward the
n-type channel. Some manufacturers use the symbol with the gate terminal
opposite the source [Fig. 12-2(a)J; others show the gate centralized between
263
Principle
of the
n-Channel
JFET
264
Field
Effect
Transistors
(a) (b) (c) Tetrode
connected
Figure 12-2. Circuit symbols for the n-channel JFET.
drain and source [Fig. 12-2(b)]. The symbol shown in Fig. 12-2(c) is used
where the terminals of the two gate regions are provided with separate
connecting leads. In this case the device is referred to as a tetrode- connected
FET.
12-3
Characteristics
of n-Channel
JFET
12 - 3.1
Depletion
Regions
An n-channel JFET is shown in Fig. 12-3 with the gate connected
directly to the source terminal. When a drain voltage ( V D ) is applied, a
drain current I D flows in the direction shown.
Source
Figure 12-3. n-Channel JFET showing internal voltage drops and resulting depletion
regions.
Since the /j-material is resistive, the drain current causes a voltage drop
along the channel. In the portion of the channel between gate and source, I D
causes a voltage drop which biases the gate with respect to that part of the
channel close to the gate. Thus, in Fig. 12-3, the gate regions are negative
with respect to point A by a voltage V A . This will cause the depiction regions
to penetrate into the channel at point A by an amount proportional to V A .
Between point B and the source terminal the voltage drop along the channel
is V B , which is less than V A . Therefore, at point B the gate is at — V B with
respect to the channel, and the depletion region penetration is less than at
point A. From point C to the source terminal, the voltage drop V c is less
than V B . Thus, the gate-channel junction reverse bias (at point C ) is V c
volts, and penetration by the depletion regions is less than at A or B. This
difference in voltage drops along the channel, and the consequent variation
in bias, account for the shape of the depletion regions penetrating the
n-channel.
265
Characteristics
of n-Channel
JFET
When the gate is connected directly to the source (i.c., no external
bias), ^cs = 0. The characteristic for ^ = 0 is plotted in Fig. 12-4. When
^ds = Id = 0, and the voltage between the gate and all points in the
channel is also equal to zero. When ^DS is increased by a small amount, a
small drain current flows, causing some voltage drop along the channel. This
reverse biases the gate-channel junctions by a small amount, causing little
depletion region penetration, and having negligible effect on the channel
resistance. With further small increases in ^DS the drain current increase is
nearly linear, and the channel behaves as a resistance of almost constant
value.
The channel continues to behave as an almost constant resistance,
until the voltage drop along it becomes large enough to cause considerable
12 - 3.2
Drain
Characteristics
when l / GS = 0
Breakdown
region
Figure 12-4. Characteristics of n-channel JFET for V cs -0.
266
Field
Effect
Transistors
penetration by the depletion regions. At this stage the channel resistance is
significantly affected by the depletion regions. Further increases in ^DS
produce smaller increases in I D , which, in turn, cause increased penetration
by the depletion regions and further increase the channel resistance. Because
of the rapid increase in channel resistance at this stage (produced by
increasing I D ), a saturation level of I D is reached, where further increases in
Vds produce only very slight increases in I D . The drain current at this point,
with Vqs at zero, is referred to as the drain-source saturation current I DSS (see
Fig. 12-4). When the drain current saturation level is reached, the shape of
the depletion regions is such that they appear to pinch off the channel. For
this reason, the drain-source voltage at which I D levels off is designated the
pinch-off voltage ( V p ), as indicated in Fig. 12-4. The region of the characteris-
tic where I D is fairly constant is referred to as the pinch-off region. The region
of the characteristic between ^ds = 0 and Vds~ V P is termed the channel ohmic
region , because the channel is behaving as a resistance. With continued
increase in Vds a voltage will be reached at which the gate-channel junction
breaks down. This is the result of the charge carriers which make up the
reverse saturation current at the gate channel junction being accelerated to
a high velocity and producing an avalanche effect (see Chapter 11). At this
point the drain current increases very rapidly, and the device may be
destroyed. The normal operating region of the characteristics is the pinch-off
region.
12 - 3.3
Drain
Characteristics
with
External
Bias
When an external bias of, say, — 1 V is applied between the gate and
source, the gate-channel junctions are reverse biased even when I D = zero.
Therefore, when Vds - 0 the depletion regions are already penetrating the
channel to some extent. Because of this, a smaller voltage drop along the
channel (i.e., smaller than when Vos = 0) will increase the depletion regions
to the point at which they pinch off the current. Consequently, the pinch-off
voltage is reached at a lower I D than when V«-0- The characteristic for
Vqs = — 1 V is shown in Fig. 1 2-5.
By employing several values of negative external bias voltage, a family
of Id! V ds characteristics is obtained as shown in Fig. 12-5. Note that the
value of Vds for breakdown is reduced as the negative gate bias voltage is
increased. This is because — Vgs is adding to the reverse bias at the junction.
If a positive gate bias voltage is employed, a larger I D can be the result, as
shown by the characteristic for Vcs~ + 0.5V in Fig. 12-5. In general,
however, V GS is maintained negative to avoid the possibility of forward
biasing the gate-channel junctions.
The broken line on Fig. 12-5 is a line through the points at which I D
saturates for each level of gate bias voltage. When ^=0, Id saturates at
I DSS , and the characteristic shows V p = 4.5V. When an external bias of — 1 V
is applied, the gate-channel junctions still require — 4.5 V to achieve pinch
off. This means that a 3.5-V drop is now required along the channel instead
Gale channel
junction
v ds *"
Figure 12-5. n-Channel JFET drain characteristics.
of the previous 4.5 V, and the 3.5 V is achieved with a lower value of I D .
Similarly, when is —2 V and —3 V, pinch off is achieved with 2.5 V
and 1.5 V, respectively, along the channel. The 2.5- and 1.5-V drops arc, of
course, achieved with further reduced values of I D .
The FET transfer characteristics are experimentally determined by
maintaining ^DS at a constant level and varying K» in convenient steps. At
each step of Vcs the I D and Vos levels are recorded, and a table of values is
obtained from which a graph of I D is plotted versus This will give
transfer characteristics similar to the transconductancc characteristics of a
vacuum tube or bipolar transistor (Fig. 12-6). As in the case of other devices,
the transfer characteristics may also be derived from the output characteris-
tics by reading off corresponding and I D levels for a fixed level of Vds-
Derive the transfer characteristics from the FET drain characteristics
in Fig. 12-6.
solution
Refer to the drain characteristics in Fig. 12-6; when ^ = 0, / D = s 9mA.
Mark point 1 on the transfer characteristics at I D — 9 mA and ^“0.
267
Characteristics
of n-Channel
JFET
12 - 3.4
Transfer
Characteristics
Example 12-1
268
Field
Effect
Transistors
Figure 12-6. n-Channel transfer characteristics.
Point 2 is at I D = 5.4 mA
and
s 5
II
1
<
Point 3 is at I D = 2.8 mA
and
Vcs=~ 2 V
Point 4 is at I D = 0.9 mA
and
I'cs = — 3 V
Point 5 is at I D = 0 mA
and
1
11
Draw the transfer characteristic through points 1 to 5.
12-4
The
p-Channel
JFET
In this device, the channel is p - type material, and the gate regions are
n-type (Fig. 12-7). The drain-source potential is applied, positive to the
source, negative to the drain. Thus, a current flows (in the conventional
direction) from the source to the drain. To reverse bias the junctions
between the gate and the channel, the / 2 -type gate must be made positive
with respect to the //-type channel. Therefore, bias voltage is applied,
positive on the gate, negative on the source. The voltage drop along the
channel is negative at the depletion regions and positive at the source. As in
the case of the / 2 -channel device, this voltage drop tends to reverse bias the
gate-channel junctions.
Symbols for the //-channel JFET are shown in Fig. 12-7. The
arrowhead again points from the p - type material to the / 2 -type material: in
this case it points from the p - type channel to the / 2 -type gate. The drain and
transconductance characteristics for the //-channel JFET are similar to those
of an n-channel device, with the exception that all voltage and current
polarities are inverted (Fig. 12-8).
269
JFET
Data Sheet
and
Parameters
Figure 12-7. Principle of operation and circuit symbols for p-channel JFET.
Transfer Drain characteristics
Figure 12-8. p-Channel drain and transfer characteristics.
12-5
JFET Data
Sheet and
Parameters
A typical FET data sheet is shown in Fig. 12-9. Like the bipolar
transistor data sheet, it begins with a device type number and a brief
description of the device to indicate the most important applications. These
data are followed by the maximum ratings for the FET, and then the
12 - 5.1
Data
Sheet
2n5457 (SILICON)
Silicon N-channel junction field-effect transistors de-
pletion mode (Type A) designed for general-purpose
audio and switching applications.
CASE 29 (5)
(TO-92)
Drain and source may ba
interchanged.
ELECTRICAL CHARACTERISTICS <r. = »-c
Characttristic | Symbol [Min | Typ [ Mai [ Urit~
OFF CHARACTERISTICS
Gate-Source Breakdown Voltage
0c "-lOjiAdc. Vug - 0)
B V &SS
25
-
-
Vde
Cate Reveree Current
(Vog = -15 Vde, Vpg - 0)
«GSS
_
_
i.a
nAde
(Vqs - -IS Vde. Vpg - 0, T a - 100°C)
-
-
200
Giti- Source Cutoff Voltage
(Vpg x is Vde. Ij, « 10 nAde)
2N5457
v cs(om
0.5
_
s.o
Vde
2N5456
i.o
—
7.0
2N5459
2.0
-
6.0
Gate-Source Voltage
(Vqs . IS Vde, Ip - lOOuAdc)
2N5457
V GS
_
2.S
_
Vde
(V x . 1$ Vde, I D x 200 iiAdc)
2N545B
—
3.5
—
|V K - IS Vde, Ip - 400 uAdc)
2N54S9
-
4.S
-
ON CHARACTERISTICS
Zero-Gate-Voltage Drain Current HI
l DSS
mAde
(Vpg - 15 Vde, VQg - 0) 2N54S7
1.0
3.0
5.0
2NS4S6
2.0
8.0
9.0
2NS4S9
4.0
9.0
16
DYNAMIC CHARACTERISTICS
Forward Transfer Admittance HI
(Vpg - IS Vde, Vpg - 0. f - 1 kHa) 2NS4S7
2N54S8
2N5459
Kl
1000
1500
2000
3000
4000
4500
sooo
5500
0000
limboa
Output Admittance
(Vpe - IS Vde, Vpg - 0, 1 - 1 kHa)
M
10
50
Mmho.
Input Capacitance
(Vpg • 15 Vde, Vpg - 0, f - 1 MB*)
Cue
4.5
7.0
pF
Reveree Tranefer Capacitance
(Vpg - 15 Vde. Vpg - 0, 1 - 1 MBl)
CrM
_
l.S
3.0
PF
IHpulae Teat: Pulae Width SUOu; Duty Cycle S 10 %
<*> Continuous imp.Ovon.onu hov* onhoncod lhaaa guotoniood Mo.imum noting. ti tol'ov .1 - IOWITj. 25°C.
Oaraia «o« 2S°C - « O m*v/°C. 1S0°C. * JC • m° C/W
Figure 12-9. FET data sheet. (Courtesy of Motorola, Inc.)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Drain-Source Voltage
V DS
25
Vde
Drain-Gate Voltage
V DG
25
Vde
Reveree Gate -Source Voltage
V GS(r)
25
Vde
Gate Current
>G
10
mAdc
Total Device Dtaetpatlon i T A » 2S*C
PpU'
310
mW
Derate atiove 25°C
2.82
mW/°C
Operating Junction Temperature
Tj m
135
°C
Storage Temperature Range
W”
-65 to » ISO
»c
2n5458
2n5459
0
270
electrical characteristics are noted for specified bias conditions. Some of the
important FET parameters listed on the data sheet are considered below.
The drain-source saturation current {I DSS ) and the pmch-off voltage ( V p )
have already been discussed in Section 12-3. I DSS is sometimes termed the
pinch-off current , and referred to as I DP at 1^ = 0 V. I DP may also be specified
at Vqs values other than zero, and in this case V ^ will also be specified.
Another name for the pinch-off voltage is gate cutoff voltage
The FET transfer characteristic approximately follow's the equation
Id
2
( 12 - 1 )
When I DSS and V p are known, a table of values of I D and V ^ may be
determined from the equation. From this table, the transfer characteristic
can be constructed. One of the problems in using FET’s is that each device
type does not have a single transfer characteristic. This is because I DSS and
V p cannot be specified accurately. Instead, the manufacturer specifies maxi-
mum and minimum values for each parameter. Referring to Fig. 12-9, it is
seen that, for the 2N5457 FET, I DS s( m i n ) = 1 mA, and Ioss^ mMJi ) — 5 mA. Also
V p , which is listed as F^^, has a minimum level of 0.5 V and a maximum
of 6 V.
Using the information provided on the data sheet (Fig. 12-9), construct
the maximum and minimum transfer characteristic for a 2N5459 FET.
solution
From Fig. 12-9,
v p= v cs( o«)~2 V (min), 8 V (max)
loss = 4 mA (min), 16 mA (max)
To construct the minimum transfer characteristic, the minimum levels
of V P and I DSS are substituted into Eq. (12-1) along with convenient values
of V cs .
When F a? = 0 V, 1 D = 4 mA [1 -0/2] 2 = 4 mA.
Plot point 1 of the minimum transfer characteristic at 1^ = 0 V and I D = 4
mA (Fig. 12-10).
When Fes * 0.5 V,
When V cs =\ V,
When Vcs =1.5 v >
When V cs = 2 V,
f D = 4 mA ( 1 - 0.5/2J 2 = 2.25 mA
I D = 4 mA [ 1 - l/2] 2 = 1 mA
I D = 4 mA [1 - 1.5/2] 2 = 0.25 mA
/ /) = 4mA [1 -2/2] 2 = 0 mA
(point 2)
(point 3)
(point 4)
(point 5)
12-5.2
Saturation
Current and
Pinch-off
Voltage
Example 12-2
271
272
Field
Effect
Transistors
mA
DSSImax)
Figure 12-10. Construction of maximum and minimum transfer characteristics for
2N5459.
The minimum transfer characteristic is now drawn through points 1 to 5.
For the maximum transfer characteristic the above process is repeated using
I DSS = 16 mA and V p = 8 V.
When Vcs = 0 V, I D = 16 mA [1 -0/8] 2 = 16 mA (point 6)
When K ra = 2V, / fl = 9mA (point 7)
When F gs = 4V, 7 D = 4mA (point 8)
When = 6 V, 7^ = 1 mA (point 9)
When Vo; = 8 V, I D = 0 mA (point 10)
The maximum transfer characteristic is now drawn through the points as
plotted.
12 - 5.3
Trans-
conductance
It has been shown that I DSS and V P can readily be determined from the
drain and transfer characteristics. Two other quantities that can be de-
termined from the characteristics are the transconductance (g m ) and the drain
resistance {r d ). The transconductance is simply the slope of the transfer
characteristic, and since the slope varies, the value of ^GS at which g m is
measured must also be specified. Forward transfer admittance or transadmittance
( Yj t ) are other names given to the transconductance (Fig. 12-9). g m (or Yjf) is
usually expressed in micro Siemens ( /iS) [some device manufacturers still use
mhos on their data sheets] and is defined as
gm
variation in drain current
variation in gate-source voltage
(when drain-source voltage is maintained constant)
Wes
v as
( 12 - 2 )
From the FET maximum transfer characteristics given in Fig. 12-11,
determine g m at = — 1 V and V GS = —4 V.
273
JFET Data
Sheet and
Parameters
Example 12-3
Figure 12-11. Derivation of g m from transfer characteristics.
solution
From Fig. 12-11 and Eq. (12-2),
274
Field
Effect
Transistors
at Vgs = "1 V> ^ = = 3 ’ 4 "iA/V = 3400/^
at Vqs = — 4 V, g m = = 1.9 mA/V= 1900 /tS 1
12 - 5.4
Drain
Resistance
The drain resistance ( r d ) is the ac resistance between drain and source
terminals when the FET is operating in the pinch-off region. It is also the
slope of the drain characteristics in the pinch-off region. Since the character-
istics are almost flat, r d is not easily determined from the characteristics. r d
may also be designated as r DSS , and in each case the units are ohms, kilohms,
or megohms. Since r d is usually the output resistance of the FET, it may also
be expressed as an output admittance : | Y 0J \ =\fr d .
The drain resistance is defined as
_ variation in drain-source voltage
d variation in drain current
(when the gate-source voltage is maintained constant)
_ W*
(12-3)
From Fig. 12-9, | Y os \ is 10 /xS typical, and 50 /xS at maximum. This
corresponds to r d — 100 kfl typical and 20 kfi minimum.
12 - 5.5
Drain-Source
on
Resistance
The drain resistance ( r d ) is not to be confused with the drain-source on
resistance R DS , also designated R D(dm y While r d is a dynamic (or ac) quantity,
&ds is the dc resistance of the channel when the depletion regions are
removed; i.e., when the device is biased on in the channel ohmic region of
the characteristics. I D XR DS gives a drain-source on voltage V DS(fin ^ which is
similar to the V CE (sat) of bipolar transistors. R DS may be typically 100 or
less, and it is an important quantity for FET’s used in switching circuits
known as sampling gates. I D X R DS can be much smaller than F C£(sat) , making
the FET sampling gate superior to the bipolar transistor sampling gates.
12 - 5.6
Cate Cutoff
Current
and Input
Resistance
The gate-channel junction in a JFET is an ordinary /^-junction, and
since it is normally reverse biased, a minority charge carrier current flows.
This is the gate- source cutoff current 7^, also called the gate reverse current. For
the 2N5457, 7^=1 nA at 25°C and 200 nA at 100°C (Fig. 12-9). The
device input resistance (R cs ) is the resistance of the reverse-biased gate-chan-
nel junctions, and is inversely proportional to 7^. Typical values of R ^ for
a JFET are 10 9 at 25°C and 10 7 £2 at 100°C.
There are several ways in which the FET breakdown voltage may be
specified. BV DC0 is the drain- gate breakdown voltage with the source open
circuited. BV^ is the gate-source breakdown voltage with the drain shorted to
the source. Typical values for each are in the region of 25 V; they are listed
on the 2N5457 data sheet of Fig. 12-9. Both are a measure of the voltage at
which the reverse-biased gate-channel junctions break down.
All devices have a temperature-dependent limit to the power that they
can dissipate. P D is normally specified at 25°C, with a derating factor
included for operation at higher temperatures. As in the case of bipolar
transistors, a maximum power dissipation curve may be drawn upon the
FET characteristics.
On the drain characteristics of Fig. 12-12 draw the maximum power
dissipation curve for a FET with P D = 200 mW operating at a maximum
ambient temperature of 100°C. The derating factor is 2 mW/°C.
solution
P D at 25°C = 200 mW
Derating factor = 2 mW/°C.
Maximum ambient rise above 25°C = 100°C — 25°C=75°C.
P D at \00°C = P D -{2 mW X 75°C)
= 200 mW— 150 mW = 50 mW
Figure 12-12. Maximum power dissipation curve at 100'C.
12-5.7
Breakdown
Voltage
12-5.8
Maximum
Power
Dissipation
Example 12-4
275
276
Field
Effect
Transistors
When ^ - 10 V, I D -P D / V DS - 50 mW/ 10 V = 5 mA.
Plot point 1 on Fig. 12-12 at 1^=10 V, I D = 5 mA.
At *z>s = 15V, 7 D = 50mW/15V = 3.3mA (point 2)
At V DS = 20 V, I D = 50 mW/20 V = 2.5 mA (point 3)
At V DS = 25 V, I D = 50 mW/25 V = 2 mA (point 4)
Join all the points together as shown to draw the maximum power
dissipation curve for T=100°C.
12-5.9
Noise
Figure
One advantage of a FET over a bipolar transistor is that the FET
usually has much lower noise. This is because, unlike the bipolar transistor,
there are very few charge carriers crossing junction in the FET. As in the
case of the bipolar device, the FET noise figure ( NF ) is specified as a spot noise
figure at a particular frequency and bias conditions and for a given value of
bias resistance. The figure will vary if any of these conditions are altered.
Noise calculations for a FET circuit are performed in the same way as for a
bipolar transistor circuit.
12-5.10
Capacitances
Capacitances for FET’s may be specified as gate-drain capacitance ( C gd ),
gate-source capacitance (C gs ), and drain-source capacitance (C^). Instead of these
quantities, the capacitance is sometimes specified as the common source input
capacitance ( C Us ) or ( C gss ). This is the gate-source capacitance measured with
the drain shorted to the source. In this case a reverse transfer capacitance (C rM ) is
also specified, C rss being another term for C gd . These quantities are very
important for FET high-frequency and switching circuits. For the 2N5457,
C Us is 7 pF maximum and C TSS is 3 pF maximum (Fig. 12-9).
12-6
JFET
Construction
Junction field effect transistors are normally constructed by the diffu-
sion process (Chapter 7). Figure 12-13 illustrates one type of construction.
Starting with a p- type substrate, an n -channel is diffused. Then />-type
impurities are diffused into the ^-channel to form one side of the gate, the
substrate forming the other side of the gate. Finally, metal is deposited in
place to make terminals. With this symmetrical type of construction, the
drain and source are interchangeable. Other fabrication techniques produce
devices in which the geometry is not symmetrical. In such cases interchang-
ing the drain and source terminals would radically affect the device char-
acteristics.
Gate
.terminals
Drain
—
1
l " 1
P
. Silicon dioxide
“Gates
Cross section
Figure 12-13. n-Channel diffused JFET construction.
Gate o
i "ill"
Input C gs ;
: | R cs Q) 1 r d ^ C ds
] 9„ v 9 J T
Source o <
> — l — J — i — U
(a) Complete equivalent circuit
Output
(b) Low frequency ac equivalent circuit
Figure 12-14. Equivalent circuits for junction field effect transistor.
277
12-7
FET
Equivalent
Circuit
The complete common source ac equivalent circuit for a field effect
transistor is shown in Fig. 12-14 (a). The source is common to both input
and output terminals. The output circuit is defined in terms of a current
source ( gmX V gs ) supplying current to drain resistance ( r d ). Note that V gs is
the ac (signal) voltage applied between gate and source. In parallel with the
output terminals is the drain-source capacitance C^. Input signals will “see”
the gate-source leakage resistance R ^ in parallel with the gate-source
capacitance C gs . The drain-gate capacitance C gd is shown connected be-
tween the drain and gate terminals. R ^ is normally very much larger than
the bias resistances, so it can be eliminated from the equivalent circuit. For
low-frequency operation the capacitors can also be eliminated. The sim-
plified low-frequency equivalent circuit is as shown in Fig. 12- 14(b).
12-8
The
MOSFET
12 - 8.1
Enhancement
Mode
MOSFET
Figure 12-1 5(a) shows the construction of an insulated gate FET or metal
oxide semiconductor FET (MOSFET). Starting with a high-resistive p - type
substrate, two blocks of heavily doped n-type material are diffused into the
substrate, and then the surface is coated with a layer of silicon dioxide. Holes
are cut through the silicon dioxide to make contact with the n-type blocks.
Metal is deposited through the holes to form drain and source terminals, and
on the surface area between drain and source, a metal plate is deposited.
This plate, as will be seen, can function as a gate.
Consider the situation when the drain is made positive with respect to
the source and no potential is applied to the gate. The two n -blocks and the
p - type substrate form back-to-back jfrn-junctions connected by the resistance
of the p - type material [Fig. 12- 15(b)]. Both junctions cannot be forward
biased, so only an extremely small drain current flows (i.e., a reverse leakage
current). If the />-type substrate is now connected to the source terminal,
there is zero voltage across the source-substrate junction, and the drain-
substrate junction remains reverse biased. When the gate is made positive
with respect to the source and the substrate, negative charge carriers are
induced in the substrate as shown in Fig. 12- 15(c). As the gate potential is
increased, more and more negative charge carriers are induced in the
substrate. The induced charge carriers are actually minority charge carriers
(electrons) within the p - type substrate which are attracted to the positive
voltage on the metal plate. They cannot flow across the silicon dioxide to the
plate, so they accumulate at the substrate surface just below the plate. The
minority charge carriers constitute an n-type channel stretching from drain
to source. Thus, a drain current flows and its magnitude depends upon the
channel resistance, which in turn depends upon the number of charge
carriers induced by the positive gate. The gate potential, therefore, controls
the drain current. Since the conductivity of the channel is enhanced by the
278
Source Gate Metal Drain
(a) Construction of n-channel enhancement mode MOSFET
(b) Equivalent circuit when drain-source voltage
is applied without any gate bias
(c) Effect of positive gate bias
Figure 12-15. n-Channel enhancement mode MOSFET.
279
280
Field
Effect
Transistors
Transfer
characteristic Drain characteristics
Figure 12-16. Drain and transfer characteristics for n-channel enhancement mode
MOSFET.
positive bias on the gate, the device is known as an enhancement mode
MOSFET.
The drain and transfer characteristics of the enhancement mode
MOSFET are shown in Fig. 12-16. Note that the drain current increases
with positively increasing gate-source bias voltage. Because the gate of the
MOSFET is insulated from the channel, there is no leakage current in-
volved. This gives the device a very high input resistance, in some cases
10 15 12 or greater. Transconductance values for MOSFETs typically range
from 1000 /LtS to 2000 fxS, i.e., from 1 to 2 mA/V.
Two symbols for the enhancement mode n-channel MOSFET are
shown in Fig. 12-17. In each case, the fact that the device has an insulated
gate is indicated by the gate not making direct contact with the channel. In
each case the arrowhead is shown pointing from the p - type substrate toward
the (induced) n-type channel. One symbol shows the source and substrate
internally connected, while the other symbol shows the substrate connection
brought out separately from the source. The line representing the channel is
broken into three sections to show that the channel does not exist until a
gate voltage is applied, i.e., to show that the device is operated in the
enhancement mode.
A /^-channel enhancement mode MOSFET is constructed by starting
with an n-type substrate and diffusing />- type drain and source blocks. All
voltage and current polarities are then the reverse of those for the n-channel
device, and the direction of the arrowhead is reversed in the circuit symbol.
G o |
T
Go
J
1
o Substrate
Figure 12-17. Circuit symbols for n-channel enhancement mode MOSFET.
Consider the device illustrated in Fig. 12-18 (a). The construction is
the same as for the enhancement mode MOSFET, with the exception that a
lightly doped n-type channel has been introduced between the two heavily
doped source and drain blocks. When the drain is made positive with respect
to the source, a drain current will flow, even with zero gate potential. If the
gate is made negative with respect to the substrate, positive charge carriers
are induced in the n-type channel. These positive charge carriers absorb free
negative charge carriers and cause the channel resistance to increase. Drain
current is decreased, and the effect is similar to that in the n-channel JFET.
Since the action of the negative voltage on the gate is to deplete the channel
of free n-type charge carriers, the device is referred to as a depletion mode
MOSFET.
If the drain characteristics are plotted for various levels of negative
gate-source voltage, the curves obtained are very similar to those of an
n-channel JFET. Now consider what happens if the gate is made positive
with respect to the substrate. In the n-type channel, additional n-type charge
carriers are induced, so the channel resistance decreases. Therefore, the
12 - 8.2
Depletion
Enhancement
Mode
MOSFET
Source Gate Drain
(a) n-channel depletion-enhancement
mode MOSFET with no bias
(b) Depletion mode operation
Figure 12-18. n-Channel depletion-enhancement mode MOSFET.
281
282
Field
Effect
Transistors
Transfer Drain characteristics
Figure 12-19. Drain and transfer characteristics for n-channel depletion-enhancement
mode MOSFET.
D
S
Figure 12-20. Circuit symbols for n-channel depletion-enhancement mode MOSFET.
depletion mode MOSFET is capable of being operated in the enhancement
mode also. The resultant characteristics are shown in Fig. 12-19.
The symbols for the depletion -enhancement mode MOSFET (Fig.
12-20) are similar to those for the enhancement mode device, with the
exception that the line representing the channel is now solid.
12-9
The
V-MOSFET
The construction of the V-MOSFET (or V-FET) is quite different
from that of the MOSFET discussed in Section 12-8. The cross section of an
n-channel V-FET is illustrated in Fig. 12-21. A V-shaped cut penetrates
from the surface of the device through n + , p, and n ~ layers almost to the n +
Source Gate
Source
Silicon dioxide
283
The
V-MOSFET
V
n~ Epitaxial layer
.
■> n* Substrate
X
Drain
Figure 12-21. Cross section of n-channel enhancement mode V-MOSFET.
substrate. The layers are heavily doped, low resistive material, while the
n~ layers are lightly doped, high resistive regions. The silicon dioxide layer
covers both the horizontal surface and the surface of the V-cut. The
(insulated) gate is a metal film deposited on the silicon dioxide in the V-cut.
Source terminals make contact (through the silicon dioxide) to the upper n +
and p layers. The n + substrate is the drain terminal of the device.
This is an enhancement mode FET; no channel exists between the drain
and source regions until the gate is made positive with respect to the source.
As in the case of the enhancement mode MOSFET described in Section
12-8.1, an n-type channel forms close to the gate when the gate is made
positive with respect to the source. In the case of the V-FET, this n-type
channel provides a vertical path for charge carrier flow between the n +
substrate, i.e., the drain, and the n + source termination. When the
gate-source voltage is zero or negative, no channel exists and no current
flow occurs.
The drain characteristics and transfer characteristics for the enhance-
ment mode n-channel V-FET are similar to those for the enchancement
mode MOSFET (Fig. 12-16). As the gate is made more and more positive
with respect to the source, the channel resistance is reduced and more drain
current flows. The gate voltage controls the drain current so that, for a given
level of Vcs> Id remains fairly constant over a wide range of ^DS levels.
/^-Channel VMOS field effect transistors are also available. As for
/^-channel JFETS and /^-channel MOSFETS, the characteristics are similar
to those of the n-channel devices, except that the current directions and
voltage polarities are reversed. Because the drain terminal of the V-FET is
at the bottom of the device, instead of at the top surface, the drain can have
a considerably larger area for any given device size. This allows much
greater power dissipations than are possible in a MOSFET with both drain
and source at the surface.
In the V-FET the channel length is determined by the diffusion
process, while in the MOSFET, with a channel parallel to the surface of
the semiconductor, the channel length depends upon the dimensions of the
photographic masks employed in the diffusion process. By controlling the
VN88AF
ELECTRICAL CHARACTERISTICS (25'C unless otherwise noted)
VN88AF
Test Cond t ons
Charact.nttic
Mm
Typ
Max
1
BV DSS
Drain-Source
80
V GS = °- *D = 10 nA
2
Breakdown
80
V
Vqs 0. Iq 2 5 mA
3
v GSIth)
Gate Threshold
Voltage
08
20
V DS V GS- 'D ‘ 1 mA
4
'GSS
0 05
100
nA
v G s isv. v DS 0
s
500
V GS IS V. V DS 0. T A 125 C (Note 21
6
s
10
Vqs Max Rating. Vqs - 0
7
A
T
'DSS
Zero Gate Voltage Drain
Current
500
mA
Vqs 0 8 Max Rating. V GS 0. T A 125 C
(Note 21
8
C
100
nA
V DS = 25 V. V GS 0
9
•Dion)
ON State Dram Current
(Note 11
1 0
2
A
Vqs 25 V. V G s - 10 V
10
04
V G s 1 6 V. Iq 0 1 A
*TT
v DS(on)
Drain-Source Saturation
1 4
1 7
V
V GS - 5V. Iq 0 3 A
12
Voltage (Note 1 )
1 3
V GS - 10 V. Iq = 0 6 A
~
30
4 0
Vcs'IOV.Iq = ioa
14
9m
Forward Transconductance
(Note 1 1
170
250
mhos
Vqs = 24 V. Iq = 05 A
IS
C.ss
Input Capacitance
(Note 2)
50
16
D
C rS $
Reverse Transfer Capacitance
(Note 21
10
pF
V G s 0. Vqs = 25 V. 1 = 1 0 MHz
17
N
A
Cass
Common-Source Output
Capacitance (Note 2)
50
18
1
C
'd(on)
Turn-ON Delay Time
(Note 2)
2
5
19
l r Rise Time (Note 2)
2
5
See Switching Time Test Circuit
20
«d<o»ll
Turn-OFF Delay Time
(Note 21
2
5
IT
1|
Fall Time (Note 21
2
5
NOTES 1 Pulse test - 80 ms pulse. 1% duty cyiie 2 Sample test
Output Characteristics
Transfer Characteristic
V 0 s OR AIN TO SOURCE VOLT AGE I VOL TSI
0 2 4 6 8 10 12
V GS gate TO SOURCE VOLTAGE (VOLTS!
Figure 12-22. Portion of data sheet for V-MOS field effect transistor. (Courtesy of
Siliconix, Inc.)
284
doping density and the diffusion time, much shorter channels can be created 285
than are possible with mask control of channel length. These shorter Glossary of
channels allow greater current densities, which again contribute to larger lmP Terms
power dissipations. The shorter channel length also allows a higher transcon-
ductance to be achieved in the V-FET, and very considerably improves the
frequency response and switching time of the device.
Another very important factor in V-FET geometry is the presence of
the lightly doped n ~ epitaxial layer close to the n + substrate. When the gate
voltage is zero or negative and the drain is positive with respect to the
source, the junction between the p-layer and the n-Iayer is reverse biased.
The depletion region at this junction penetrates deep into the n ~ layer, and
thus avoids punch through from drain to source. Because of this, relatively high
drain-source voltages can be applied without any danger of device break-
down.
The V-MOSFET can now be described as a high-voltage power
transistor capable of high-frequency and fast-switching operation, and
having a large transconductance value.
A portion of the manufacturer’s data sheet for the SILICONIX
VN88AF n-channel enhancement mode V-MOS power FET is shown in
Fig. 12-22.The device has a rated maximum power dissipation of 12.5 W,
can survive a ^DS of 80 V, and can pass a drain current of 2 A. The output
characteristics show- that, when ^ = 7 V, I D is constant at just over 1.2 A
for V DS levels in excess of approximately 8 V.
The transfer characteristic for the VN88AF is almost linear over most
of its length. The g m of the device is typically 250 mS, or 250 mA/V. This
compares very favorably with the 6 mA/V (maximum) specified for the
2N5459 JFET (see Fig. 12-9) and with the 20 mA/V maximum usually
found in MOSFETs. Since the gain of a FET amplifier is approximately
g m XR L (see Section 14-3), V-FET stages obviously have much larger gains
than other FET amplifiers.
n-channel JFET. Field effect transistor consisting of n-type channel and Glossary of
p-ty pe gate regions, with gates and channel forming /^-junctions. Important
p-channel JFET. Field effect transistor consisting of />-type channel and
n-type gate regions, with gates and channel forming /m-junctions.
Drain. FET terminal at one end of channel — most positive terminal for
n-channel JFET.
Source. FET terminal at opposite end of channel from drain — negative
channel terminal for n-channel JFET.
Gate. FET input terminal — controls channel current.
Unipolar transistor, n-channel or p-channel FET.
Drain current, l D . Current flowing into or out of the drain terminal.
Source current, I s . Current flowing into or out of the source terminal.
Tetrode connected FET. FET with two gate regions, each having separate
terminals.
Depletion regions. Regions depleted of charge carriers penetrating into the
channel when the gate-channel junctions are reverse biased.
Drain characteristics. Plot of drain current versus drain-source voltage for
various levels of gate-source voltage.
Channel ohmic region. Region of drain characteristics in which the FET is
behaving like a resistor.
Pinch-off region. Region of drain characteristics in which drain current
remains almost constant for a given level of gate-source voltage.
Breakdown region. Region of drain characteristics in which the drain-
gate junction breaks down.
Drain saturation current, I DSS . Level of I D at commencement of saturation
region with gate-source voltage at zero.
Pinch-off voltage, V p . Drain-source voltage at I DSS , the level of at
which I D becomes zero.
Transfer characteristic. Plot of I D versus Vor
Transconductance, g m . Ratio of I D change to gate-source voltage change
for a given level of Vds-
Forward transfer admittance. Same as transconductance.
Transadmittance, Yj t . Same as transconductance.
Drain resistance, r d . The drain-source ac resistance when the FET is
operating in the pinch-off region. The reciprocal of the slope of the
drain characteristics in the pinch-off region.
Output admittance, F M . The inverse of r d .
Drain-source on resistance, Rds* The dc drain to source resistance when
the FET is biased on in the channel ohmic region of the characteristics.
Drain-source on voltage, V Ds ^ m y I D X R DS .
Gate-source cutoff current, I GSS > Small current which flows across the
reverse-biased gate-channel junctions of a JFET.
Gate reverse current. Same as Iq^.
Input resistance, R^. Resistance of reverse-biased gate-channel junctions.
Drain-gate breakdown voltage, BV^q. Drain- gate voltage at which
gate-channel junctions break down.
Gate-source breakdown voltage, BV GSS . Gate-source voltage at which
gate-channel junctions break down.
Common source input capacitance, C Ut or C gst . The gate-source capaci-
tance measured with the drain shorted to the source.
Reverse transfer capacitance, C ru or C gd . The drain-gate capacitance.
MOSFET. Metal oxide semiconductor field effect transistor.
Enhancement mode MOSFET. MOSFET which is off when 1^ = 0.
Channel conductivity must be enhanced by increasing bias from zero.
Depletion-enhancement MOSFET. MOSFET which conducts when
= 0. Channel conductivity can be depleted or enhanced by increasing
or decreasing bias.
V-MOSFET. MOSFET in which the gate is V-shaped; high-frequency,
high-power device.
12-1. Using illustrations, explain the principle of the n-channel JFET.
Show the internal depletion regions, and explain their shape.
12-2. Sketch typical drain characteristics for an n-channel JFET, and
explain. Indicate and name the regions of the characteristics. Define
and mark I DSS and V p on the characteristics.
12-3. Sketch a typical transconductance characteristic for an n-channel
JFET, and show how g m may be derived from it.
12-4. Repeat Questions 12-1 and 12-2 for a /^-channel JFET.
12-5. Draw the complete equivalent circuit for a JFET. Explain the origin
of each component, suggest typical values, and show- how the circuit
can be simplified for low-frequency operation. Show how some of the
parameters involved may be derived from the drain characteristics.
12-6. Draw sketches to show one type of JFET construction. Label all parts
and explain.
12-7. Using illustrations, explain the principle of the n-channel enhance-
ment MOSFET. Also sketch the device drain characteristics and
explain.
12-8. Repeat Question 12-7 for an n-channel depletion-enhancement
MOSFET.
12-9. Sketch the symbols and characteristics for n-channel JFET, /^-channel
JFET, n-channel enhancement MOSFET, n-channel depletion-
enhancement MOSFET, and /^-channel depletion-enhancement
MOSFET.
12-10. Sketch the cross section of a V-MOSFET and explain how it oper-
ates.
12-11. Sketch typical output and transconductancc characteristics for a
V-FET. Briefly discuss the performance of this device and compare it
to other FET’s.
12-1. From the drain characteristics in Fig. 12-12, derive the transfer
characteristic.
12-2. Using the information provided in the data sheet (Fig. 12-9), con-
struct the maximum and minimum transfer characteristics for a
2N5458 FET.
12-3. From the FET maximum transfer characteristic constructed for Prob-
lem 12-2, determine the value of g m at 1 / GS — ~ 1 V and 1 ^ =*= — 6 V.
287
Problems
Review
Questions
Problems
288
Field
Effect
Transistors
12-4. On the drain characteristics shown in Fig. 12-5, draw the maximum
power dissipation curve for a 2N5458 FET operating at a maximum
ambient temperature of 125°C.
12-5. From the transfer characteristics for a VN88AF in Fig. 12-22, de-
termine the value of g m . Using the output characteristics given in Fig.
12-22, draw the transfer characteristic for Vds = 10 V. Determine g m
from this characteristic.
FET Biasing
Thermal runaway does not occur with field effect transistors; however,
the wide differences in maximum and minimum transfer characteristics
make I D levels unpredictable with simple bias techniques. To obtain reason-
able limits on the quiescent values of drain current, bias techniques similar
to those used with vacuum-tube circuits must be employed. For both analysis
and design of FET bias circuits, a graphical approach is most convenient.
With few exceptions, MOSFET bias circuits are almost identical to those
used for JFET’s.
The dc load line for a FET circuit is drawn upon the device character-
istics in exactly the same way as was done with the bipolar transistor circuit
(see Section 5-2). Consider the common source circuit and device character-
289
CHAPTER
13
13-1
Introduction
13-2
DC Load
Line and
Bias Point
13-2.1
DC Load
Line
290
FET
Biasing
R
(b) Plotting dc load line
Figure 13-1. DC load line for common source circuit.
istics shown in Fig. 13-1. The drain-source voltage = (supply voltage) —
(voltage drop across R L ):
V ds =V dd -I d R l ( 13 - 1 )
By substituting any convenient values of I D into Eq. (13-1), the correspond-
ing levels of V DS can be calculated. These points are then plotted on the
characteristics and the load line is drawn through them.
Construct the dc load line for the FET common source circuit and
characteristics shown in Fig. 13-1.
Example 13-1
solution
^ DS ^DD 1 D^L
When I D = 0,
291
Spread of
Characteristics
and Fixed
Bias Circuit
^DS~ ^DD
= 24 V
Plot point A on the characteristics at I D = 0 and V DS = 24 V.
When V DS = 0,
0 =v dd -i d r l
1 V ° D - 24 v
° R l 2.2 k£2
= 10.9 mA
Plot point B on the characteristics at / D = 10.9 mA and V DS = 0 V. The dc
load line is now drawn through points A and B.
The dc load line for a FET circuit is a graph of corresponding l D and
^DS levels for given values of load resistance and supply voltage. The load
line defines all dc values of I D and Vds that can exist in the circuit. If either
R l or Vds is changed, a new dc load line must be drawn.
A dc bias point or quiescent point (Q point) similar to that for bipolar 13-2.2
transistor circuits is selected on the load line. This point defines the dc The Bias
conditions that exist in the circuit when no input signal is applied. As Point
explained in Section 5-2, the bias point may be selected to give maximum
possible equal positive and negative changes in the output voltage from the
circuit. Where maximum possible output voltage variations are not required,
the bias point may be selected at any convenient position on the load line.
For a FET amplifier circuit, however, Vos must not be allowed to fall below
the pinch-off voltage [V p on Fig. 13- 1(b)]. Also, since the gain of a field
effect device is nonlinear, FET amplifiers are usually arranged to give only
small output voltage variations. The Q_ point for a FET circuit is usually
selected for a convenient value of gate bias voltage. In Fig. 13- 1(b) the ()
point is at F ay = — 1 V, giving I D = 5.5 mA and ^=11.9 V.
For a given FET type, typical values of I DSS and V p arc specified on
the device data sheet. These quantities cannot be specified to close toler-
ances, so as explained in Section 12-5, the maximum and minimum values
are also specified. The maximum and minimum values may easily range to
±50% or more of the typical values. Because of this spread on / ^ and V p ,
there are significant effects on the drain and transfer characteristics. These
are shown in Fig. 12-10 where the maximum and minimum transfer
characteristics are plotted for a 2N5459 FET.
13-3
Spread of
Characteristics
and Fixed
Bias Circuit
292
FET
Biasing
Example 13-2
The circuit of Fig. 13- 1(a) is an example of fixed bias. The gate is
biased via resistance R c to a negative voltage V G . The maximum and
minimum levels of I D for a given bias voltage can be best determined by a
graphical technique. A bias line is drawn vertically on the transfer character-
istics at the fixed level of V GS . I D(max) and I D(min) are then indicated at the
intersections of the bias line and the transfer characteristics.
The maximum and minimum transfer characteristics for the FET in
the circuit of Fig. 13-1 (a) are shown in Fig. 13-2. Draw the bias line for
V G = — 1 V and determine the maximum and minimum levels of I D and the
corresponding Vds levels.
Figure 13-2. /o( max) ancl in) determination for fixed bias circuit.
solution
V G s=Vc=- IV, being a fixed quantity unaffected by I D and Vds-
Draw a bias line vertically from v cs~ 1 V as shown in Fig. 13-2.
From the points at which the bias line intersects the characteristic, it is
seen that / D(max) = 5.5 mA and I D{ndn) = 1.25 mA.
Eq. (13-1)
For ^(nu,).
V DS = 24 V- (5.5 mA X 2.2 kft ) = 1 1 .9 V
293
Self-Bias
For ),
V DS = 24 V — (1.25 mA X 2.2 kft) = 21.25 V
Example 13-2 shows that because of the spread in FET characteristics,
the fixed bias technique is by no means reliable. It is possible to make such a
circuit function satisfactorily by adjusting V G to give the desired level of
However, this is acceptable only in an experimental situation. For more
predictable bias conditions, slightly more complicated circuit techniques
must be resorted to.
The process of biasing ^-channel FET’s is exactly the same as for
^-channel devices, with the exception that all voltage polarities are reversed.
13-4
Self-Bias
In the self-biased circuit a resistance in series with the source terminal 13-4.1
provides the gate bias voltage. Consider the self-biased circuit shown in Fig. ^ ,ne
1 3-3. The voltage drop across R s is V Rg = I D XR S . If 1 D = 1 mA and R s = 1 k ft,
then V Rs = IV- In this case the source terminal is IV positive with respect to
ground or, in other words, ground is IV negative with respect to the source
terminal. Since the gate is grounded via R c , the gate terminal is also IV
negative with respect to the source terminal; i.e., the gate-source bias is
1^= — IV. It is seen that for the self-biased circuit the gate-source bias
voltage is
— IqXRs (1 3 - 2 )
To determine the maximum and minimum values of I D> it is best to
again apply a graphical analysis technique. By selecting convenient values of
I D and calculating the corresponding levels of Fes i a bias line may be drawn
upon the transfer characteristics. The points where this bias line intersects
the transfer characteristics give / D(mu) and I D ( min y Summing the voltage
drops across R L , the transistor, and R s gives
Vdd “ “F + Id^s (13-3)
From Eq. (13-3), the maximum and minimum levels of may be
calculated once and I D ( mtn) are determined.
294
FET
Biasing
Example 13-3
Figure 13-3. Self-biased circuit.
v oo
The circuit of Fig. 13-3 uses a FET with the maximum and minimum
transfer characteristics shown in Fig. 13-4. Determine the values of I D ^ mAx ^
and and the corresponding values of V DS .
solution
From Eq. (13-2),
^GS —
When I D = 0, = 0. Plot point A on the bias line at I D = 0 and = 0.
When I D = 5 mA, V as = — 5 mA X 1 kS2 = — 5 V. Plot point B at I D = 5 mA,
^=-5V.
The bias line for R s = 1 kfi is now drawn through points A and B.
Where the bias line cuts the maximum and minimum transfer characteris-
tics, read
7 Z)(max) = 2.5 mA
and
•^D(min) ^*2 mA
From Eq. (13-3),
^ds — Vdd ~~ Id^l
~~ ^DD ■*" Rs)
For V«)>
= 24 V - 2.5 mA(3 kfi + 1 kfi) = 1 4 V
F o r to^iny
V DS = 24 V — 1 .2 niA(3 k£2 + 1 kft) = 19.2 V
It is seen from Example 13-3 that the self-bias technique gives closer
limits on I D , and consequently on >v than the fixed-bias circuit. The
limits can be even closer if a larger value of R s is used. The bias lines drawn
as broken lines on Fig. 13-4 are for R s — 2 kfi and 3 k 12, as shown. Although
the limits of I D are closer with large values of R Sy I D is reduced to quite low
levels, and this can be a distinct disadvantage.
As already explained, source resistance R s is included to stabilize the 13-4.2
drain current. R s will also tend to stabilize I D against signals applied to the Bypass
gate; i.e., R s will reduce the ac voltage gain of the circuit. C s in Fig. 13-3 is a Capacitor
large capacitor which acts as an ac short circuit across R s , so that maximum
ac gain is achieved. As in the case of bipolar transistor circuits, the total dc
load is ( R l + R s ), and the ac load (with R s bypassed) is R L . Therefore, an ac
load line must be drawn to describe the ac performance of the circuit.
13-5
Self-Bias
with
External
Voltage
Two methods of employing an external voltage and source resistance
for FET bias are shown in Fig. 13-5. In the circuit of Fig. 13-5(a) the source
resistance is connected to a negative supply voltage, while in Fig. 13-5(b) a
potential divider (R x and R 2 ) is used to derive a positive bias voltage from
Vdd- The procedure for drawing the bias line for each of these circuits is
similar to that for the self-bias circuit.
For the circuit of Fig. 13-5(a),
Vss = V cs
Vcs~ Kss
For the circuit of Fig. 13-5(b).
(13-4)
f'c “ ^GS
Figure 13-5. Two forms of self-bias with external voltage.
2%
and
r/ _ ^ DD X ^2
c R { + R 2
,, _ V, DD X ^2
Vcs ~ R t + R 2
(13.5)
In each case convenient values of I D can be substituted into the above
equations to determine the corresponding ^gs levels. These values may then
be used to plot the bias lines on the transfer characteristics.
The circuits of Fig. 13-5(a) and (b) use FET’s with the maximum and
minimum transfer characteristics shown in Fig. 13-6. Draw the bias line for
each circuit, and determine and in each case.
solution (a)
From Eq. (13-4), when I D = 0, = F^ = 3 V.Plot point A on the character-
istics (Fig. 13-6) at I D = 0 and V GS = +3 V.
When I D — 1 mA, ^ = 3V-(1 mAx3kfi) = 0.
Plot point B at I D = \ mA and F^ = 0 V.
Figure 13-6. and determination for self-bias circuit with external voltage.
297
Self-Bias
With
External
Voltage
Example 13-4
298
FET
Biasing
Draw the bias line through points A and B. Where the bias line intersects
the transfer characteristics, read I D(m3ut) = 1 .9 mA and / £>(min) = 1 .3 mA.
solution (b)
From Eq. (13-5), when 7^ = 0
_ 24 VX1 M£2
^ 3MS2+1M&
= 6 V
Plot point C on the transfer characteristics at I D = 0 and = 6 V.
When I d = 2 mA,
T7 24VX1MS2 /n o, ^
(3MJ2 + 1MB) ( 2mAx3kQ )-°
Plot point D at I D = 2 mA and = 0 V.
Draw the bias line through points C and D. Where the bias line intersects
the transfer characteristics, read 7 £ )( ma *)=2.8 mA and 7 D(min) = 2.2 mA.
13-6
Design
of FET Bias
Circuits
It is instructive to compare the results of Example 13-4 to those of
Example 13-3. The difference between and I D(jt ^ n ) in Example 13-3 is
1 .3 mA, while for Example 1 3-4 the difference is 0.6 mA in each of the two
cases. It is seen that the circuits which have an external bias voltage as well
as a source resistance maintain I D within closer limits than the circuit which
has only a source resistance. The reason for the improvement is that R s is
larger in the latter example. R s could also be made larger in the circuit
without external bias, but I D would then be reduced to a very low level.
The design process for FET bias circuits is simply the reverse of the
analysis process. The maximum and minimum acceptable levels of I D are
first specified. These are then marked on the transfer characteristics, and the
bias line is drawn through them. The reciprocal of the slope of the bias line
determines the value of the source resistance, and the point at which the bias
line intersects the horizontal axis of the characteristics indicates the required
external voltage.
Example 13-5
A JFET with the transfer characteristics shown in Fig. 13-7 is to be
connected in a circuit with a drain load resistor of 4.7 k£2 and a supply
voltage of V dd = 30 V. V D is to be approximately 20 V, and is to remain
constant to within ± 1 V. Design a suitable self-bias circuit with external
bias voltage.
299
Design
of FETBias
Circuits
Figure 13-7. Graphical process in bias circuit design.
solution
The circuit is as shown in Fig. 13-5 (b) with different resistance and voltage
values.
Vo=V DD -l D R L
V D 30 V — 20 V
4.7 kfl s
*2.1 mA
For V D to be constant to within ± 1 V,
±1 V _ ±1 v
D ~ R l ” 4.7 kS2
±0.2 mA
= (2.1 ±0.2) mA
7 D(min) = (2.1-0.2)rnA=1.9 mA
W)" (2. 1+0.2) mA = 2.3 mA
Now mark / /)(max) = 2.3 mA (point on the maximum transfer
characteristic (Fig. 13-7), and 7 /)(min) * 1 *9 mA (point Y) on the minimum
transfer characteristic. Draw the bias line through these two points, and
extend it until it intersects the horizontal axis of the transfer characteristics.
300
FET
Biasing
The reciprocal of the slope of the bias line is determined over any
convenient range. From points A and B on the bias line,
A V
M
10 V
2.5 mA
= 4kfi
The bias line intersects the horizontal axis at F c = 7 V; therefore, an
external bias of 7 V is required.
V *-*tt XVD > [ seeFi S 13 - 5 ( b )]
R 2 _ v c _ 7 V
R x + R 2 V dd 30 V
^2 = J_
R x 23
R 2 and R x should be as large as possible to avoid overloading input
signals. If R 2 is 700 kfl, for example, then R x = 2.3 Mfi.
13-7
Biasing
MOSFET'S
MOSFET biasing is as simple as JFET biasing. In the case of
depletion-enhancement devices, the gate-source voltage may be either posi-
tive or negative. For enhancement MOSFET’S, the gate-source voltage must
have the same polarity as the drain supply; i.e., must be positive for an
n-channel device and negative for a /^-channel FET.
13 - 7.1
Fixed Bias
for
MOSFET's
Consider the two circuits and graphical analysis shown in Fig. 13-8.
Both circuits employ a depletion-enhancement device, so may be
positive, negative, or zero. The circuit in Fig. 13-8(a) has the device gate
grounded via resistor R c and the source terminal grounded directly. is
zero, and the bias line is drawn vertically at Vos = 0 on the transfer
characteristics in Fig. 13-8(c). I D ^ miuC) and can be read where the
maximum and minimum transfer characteristics cut the bias line.
In the circuit of Fig. 13-8(b), V GS is a positive voltage ( V c ) determined
by v DD and potential divider R x and R 2 . To analyze the circuit, a vertical
line is drawn on the transfer characteristics at Vcs- V c- Again, the maxi-
mum and minimum values of I D are indicated by the intersections of the
transfer characteristics and the bias line.
The circuit in Fig. 13-9(a) employs an n-channel enhancement
MOSFET. This device must have its gate voltage positive with respect to the
source for drain current to flow. Potential divider R x and R 2 connected
across Vdd provides the required V c . The bias line is drawn vertically on the
transfer characteristics [Fig. 13-9(b)] at Vcs= Vo and the maximum and
minimum levels of I D are determined as shown.
Figure 13-8. Two fixed bias circuits and graphical analysis for depletion-enhancement
MOSFET.
The self-bias circuit of Fig. 13-10 is analyzed exactly as was done for
the similar JFET circuit.
The depletion-enhancement MOSFET in the circuit of Fig. 13-10 has
the transfer characteristics shown in Fig. 13-11. Determine the maximum
and minimum values of I D for the circuit.
solution
_ V D q X R 2
c R x + R 2
_ 20 VX200 kfl
“ 300 left + 200 kfi
Vcs-Vc-Ws
301
Biasing
MOSFETS
13-7.2
MOSFET
Self-Bias
Example 13-6
Figure 13-9. Fixed bias circuit and graphical analysis for enhancement MOSFET.
Figure 13-10. Depletion-enhancement MOSFET with self-bias and external bias voltage.
When I D — 0,
F a =8V-0=8V
Plot point A on the transfer characteristics at I D = 0 and v -
When V GS = 0
0 = 8 V-(I D X \ kfi)
8 V
1 kQ
= 8 mA
Plot point B on the characteristics at Vos = 0 and I D = 8 mA.
302
303
Problems
Figure 13-11. Graphical analysis for self-biased depletion-enhancement MOSFET
Draw the bias line through points A and B. Where the bias line
intersects the maximum and minimum transfer characteristics, read
Id( max) = 8.5 mA
^>( min) “7.2m/\
Fixed bias. Circuit in which the source is grounded and a constant bias Glossary of
voltage is applied to the gate. Important
Self-bias. Circuit in which the gate is grounded via a high resistance, and a
resistance is included in series with the source.
Self-bias with external voltage. Circuit with source resistance and a fixed
level of gate-source voltage greater than zero.
Bias line. Line drawn upon transfer characteristics to define all possible
bias conditions.
13-1. A common source amplifier has 1^ = 20 V and R L — 3.9 k 12. If the Problems
FET used has the drain characteristics shown in Fig. 12-12, draw the
dc load line and determine a suitable value of gate bias voltage.
13-2. The FET used in the circuit of Fig. 13-12 has the maximum and
minimum transfer characteristics shown in Fig. 13-11. Draw bias
lines for (a) V G = V, and (b) V G = + 1 V. In each case determine
the levels of ^D(min)> ^O(max)* an< ^ Ko(min)'
304
FET
Biasing
R l | 2.2 kQ
-o v dd
+ 30 V
In
t 1 MO
^G
\
Figure 13-12.
13-3. Draw circuits to show a JFET circuit using (a) fixed bias, (b)
self-bias, (c) self-bias with external voltage. In each case include the
necessary bypassing capacitors and briefly explain.
13-4. The FET used in the circuit of Fig. 13-13 has the transfer characteris-
tics shown in Fig. 13-14. Draw the bias line and determine the
maximum and minimum levels of I D . Also calculate the maximum
and minimum levels of V D and Vds-
13-5. The circuit in Problem 13-4 is to be redesigned to give I D within the
limits of 1 to 1.3 mA. Draw the new bias line and determine the new
value for R s and the new ratio for R 2 / R v
13-6. Determine the maximum and minimum values of V D for the circuit
of Fig. 13-15. The FET transfer characteristics are shown in Fig.
13-16.
Figure 13-13.
305
Problems
Figure 13-14.
13-7. The FET used in the circuit of Fig. 13-17 has the transfer characteris-
tics shown in Fig. 13-14. Determine maximum and minimum levels
of I D and V D .
13-8. The self-bias circuit of Fig. 13-3 is to be redesigned to give I D within
the limits of 0.5 to 1.5 mA. If the FET used has the transfer
characteristics shown in Fig. 13-14, draw the bias line and determine
the new value for R s .
Figure 13-15.
306
FET
Biasing
13-9. The FET’s employed in the circuits of Figs. 13-13 and 13-17 have
typical drain characteristics as shown in Fig. 13-18. Construct the dc
load line for each circuit. Note that the total dc load is R L + R s .
13-10. Determine the maximum and minimum levels of V DS when the gate
bias voltage in Example 13-2 is changed to — 1.5 V.
13-11. A self-bias circuit uses a JFET with the transfer characteristics shown
in Fig. 13-14. If #5 = 3.9 kfl, R L = 5.6 kfl, and 1^ = 20 V, determine
the maximum and minimum levels of V D .
Figure 13-17.
Figure 13-18. Drain characteristics for the circuits in Figs. 13-13 and 13-17.
307
8iasing
MOSFETS
13-12. If R s in Problem 13-11 is changed to 2.7 k£2, determine the new
maximum and minimum levels of V D .
13-13. A FET circuit using self-bias with external voltage (circuit as in Fig.
13-13) has R l = 3.3 kfl, R s = 3.3 kft, /?, = 1 MS2, /? 2 = 130 kft, and
V DD = 25 V. The FET transfer characteristics are as shown in Fig.
13-14. Determine the maximum and minimum levels of V D .
13-14. Determine the new maximum and minimum levels of V D when the
JFET is replaced by a MOSFET with the characteristics in Fig.
13-11, (a) in the circuit of Problem 13-4; (b) in the circuit of Problem
13-7.
13-15. The circuit of Fig. 13-10 is to be redesigned to have V D between 15
and 18 V. R L is to be changed to 6 kfl. Using the transfer characteris-
tics in Fig. 13-14, determine suitable new values for R j, R 2 > and R s .
13-16. The MOSFET circuit in Fig. 13-8 (b) uses a device with the
characteristics in Fig. 13-11. R L = 1 kfl and ^DD = 24 V. Determine
the ratio of R 2 to /?, which will give V D between 10 and 15 V.
13-17. A self-biased MOSFET circuit with external bias (as in Fig. 13-10) is
to have R L =3.3 k£2 and ^DD = 30 V. The circuit is to be designed to
give a V D level between 20 and 23 V. Using the transfer characteris-
tics in Fig. 13-11, determine suitable values for /?,, R 2> and R s .
CHAPTER
14
14-1
Introduction
14-2
The Common
Source
Circuit
Basic
FET
Circuits
There are three basic FET configurations: Common source , common drain ,
and common gate. These are similar to the three bipolar transistor circuits. Of
the three, the common source circuit is the most frequently used because of
its good voltage amplification and high input impedance. The common
drain and common gate circuits are applied as buffer amplifiers and
high-frequency voltage amplifiers, respectively.
The common source circuit is the FET equivalent of the bipolar transistor
common emitter circuit and the vacuum-tube common cathode circuit. Like
its transistor and tube equivalents, the common source circuit is used very
frequently because of its good voltage amplification. Figure 14-1 shows an
n -channel JFET connected as a common source amplifier. The gate is biased
negative with respect to the source by voltage — V c which is connected via
the gate resistance R c . The load resistance R L is connected in series with the
drain and the supply voltage V DD . Input signals are capacitively coupled to
308
309
The Common
Source
Circuit
the gate via C,, and the output is taken from the drain via C 2 . The source
terminal is common to both input and output.
To study the operation of the circuit, assume that the gate bias voltage
V G is such that I D = 1 mA. Also let the transconductance of the FET be
Sn, ~ 5000 /iS
The voltage drop across R L — I D R L = 1 mA X 10 kfi = 10 V, and the drain to
source voltage is f / DS = V DD — {I D R L ) — 2 0 V- 10 V= 10 V.
If a +0.1 V signal is now applied to the gate, the gate negative bias is
decreased by 0.1 V, the depletion region penetration is reduced, and I D is
increased. The new value of I D is
I D = l mA+(^xAy
= 1 mA + (5000X 10 -6 X0.1)
= 1 mA + 0.5 mA = 1 .5 mA
The new value of drain voltage is
V D =V DD -I D R L
= 20- (1.5 mAX 10kfl) = 5 V
Thus, an input signal of +0.1 V at the gate causes V D to decrease from
10 V to 5 V; an output change of —5 V.
Similarly, if an input signal of —0.1 V is applied to the gate, the gate
negative bias is increased by 0.1 V, the depletion regions penetrate deeper
into the channel, and I D is decreased.
I D then becomes
/„ = ■ mA + (j.XiK c )
= 1 mA + (5000X I0~ 6 X —0.1)
= 1 mA — 0.5 m A = 0.5 mA
310
Basic
FET
Circuits
and V D — V DD IqRl
= 20 — (0.5 mA X 10 kU)
= 15 V
Now, an input signal of —0.1 V on the gate caused V D to increase
from 10 to 15 V, an output change of +5 V.
The above analysis shows that the common source circuit provides an
amplified output voltage at the drain terminal when an input signal is
applied to the gate. It also shows, as illustrated in Fig. 14-1, that a
positive-going signal produces a negative-going output, and vice versa; i.e.,
there is a 180° phase shift between input and output.
14-3
AC Analysis
of Common
Source
Circuit
14-3.1
Equivalent
Circuit
To draw the ac equivalent circuit for the common source amplifier of
Fig. 14-1, the supply voltages and capacitors are replaced with short circuits,
and the device is replaced with its own ac equivalent circuit. Using the FET
low-frequency equivalent circuit from Fig. 12-14, the common source ampli-
fier equivalent circuit is shown in Fig. 14-2.
14-3.2
Voltage
Gain
From Fig. 14-2,
Output voltage = I d X ( r d \\R L )
r d XR L
and h—uYi
r, X R.
V = -g m V t X - —
' • r d +R L
Voltage gam = A v = ^ ^ + (14-1)
If, as frequently is the case, r d ^>R Lt then r d + R L ^r d , and Eq. (14-1) becomes
A Sm ^d R L
T d
or
Av^~g m R i
(H-2)
0 311
AC Analysis
of Common
Source
Circuit
S
Figure 14-2. AC equivalent circuit for common source amplifier.
This is an approximate expression for common source voltage gain which
may be useful occasionally.
The common source amplifier shown in Fig. 14-1 uses a 2N5457 FET. Example 14-1
Calculate the typical value of circuit voltage gain.
solution
From Fig. 12-9,
1 1
I yj 10X10' 6
fc-liy-3000 ps
100 kQ
From Eq. (14-1),
, -gm T d R L
A, = — —
‘ r d +R L
— 3000X 10~ 6 X lOOX 10 3 X IPX 10 3
(100Xl0 3 )-f(10X10 3 )
-27.3
Using Eq. (14-2),
A»^-gm R L
= — 3000 X 10 _6 X 10X 10 3 = -30
At low frequencies, the output imp>edance is simply 14-3.3
Output
Z 0 = R L \\r 4 asR L (14-3) Impedance
At high frequencies, R L and r d are shunted by the drain-source capacitance
Example 14-2
14-3.4
Input
Impedance
For the circuit of Fig. 14-1, r d = 100 kS2 and C DS = 3 pF. Calculate the
low-frequency output impedance, and determine the output impedance at a
signal frequency of 1 MHz.
solution
Low-frequency output impedance:
4 =
X =
lOOkGxlOkfi
100 kfi+lOkfi
1
2 irfCos
= 9.09 kft
At /= 1 MHz,
X = :
f 27rX 1 X 10 6 X3X 10“ 12
4 = 4114
R n XX r
=53 k£2
141 =
y]i R 0 2 + X ( 2
9.09 kftX53 k g
[(9.09 kfi) 2 + (53 kG) 2 ] 1/2
( R 0 is resistive and X c is reactive)
= 8.96 k ft
At low frequencies, the input impedance Z t is the bias resistance R G .
To be strictly correct, Z t = RqWR^ but since Rgs is usually very much
greater than the bias resistance,
Z^R C ( 14 - 4 )
At higher frequencies, the input capacitance shundng R c becomes
effective. It is important to note that the actual capacitance presented to an
input signal is amplified by the Miller effect (see Section 8-5), just as in the
case of bipolar transistor and vacuum-tube circuits.
c i„=C es + (l+A')C g<l
where A 0 is the circuit voltage gain &,(/?/. ||r rf ).
C m =C g ,+ [l+gJR L h)]C g<t ( 14 - 5 )
The input resistance is usually much larger than the signal source
resistance. Consequently, when the input frequency is increased until X c is
312
several times the signal source resistance, the signal is potentially divided
across X c and the signal source resistance, and the overall amplifier gain
begins to be reduced.
313
The
Common
Drain
Circuit
The common source amplifier in Fig. 14-1 uses a 2N5457 FET.
Calculate the typical value of input capacitance for the amplifier.
solution
Using typical parameters from Fig. 12-9 for the 2N5457 FET,
C ut = 4.5 pF and C ru — C gd = 1 .5 pF
c gs = c ut - C ru = 4.5 pF - 1 .5 P F = 3 pF
T d =
_L
y m
= 100 kfi
10X10' 6
gm = \Y /s \ = 3000 pS
From Eq. (14-5),
C^C t , + [\+g m {R L \\rA]C ti
= 3 pF + [l + (3X 10“ 3 )(10 kfi||100 kfi)] 1.5 pF
= 45.4 pF
Example 14-3
In the common drain amplifier , also called the source follower , the load
resistance ( R L ) is in series with the source terminal as shown in Fig. 14-3.
This circuit is the FET equivalent of the common collector bipolar transistor
circuit and the vacuum-tube common plate circuit. In the circuit of Fig.
14-3, the gate bias voltage V G is not equal to the gate-source voltage
Instead
14-4
The
Common
Drain
Circuit
Assume that I D = 1 m/\, Vqs = “2 V, and = 5000 pS:
I d R l = 1 mAX10kfl=*10 V
and V g =-2 V+10V*8 V
Note that the gate is 8 V above ground level, and the source terminal is
314
Basic
FET
Circuits
Figure 14-3. Common drain amplifier.
10 V above ground. Consequently, the source is 2 V more positive than the
gate; i.e., the gate-source bias is —2 V.
The dc conditions are now established as
I D = 1mA, V S =10V, F c = 8 V
Now calculate the input voltage necessary to produce a + 1 V change
in the output voltage: The new value of voltage at the FET gate is V G + V iy
where V i is the signal voltage. The new value of V Rl is {I D + A/ Z) )X 10 k£2
and V Rl — 10 V+1V=11V. Thus, 11 V=(I D + AI D )X 10 M2.
and
and
A In
11 V
D 10 M2
A = Sm X AF C5
A/n
— = 0.1 mA
AF gs = — mA =0.02 V
5000 X10" 6
V G + K = (^ + AF gs ) + (4 + A/ d )^
8 V+ ^. = ( — 2 V + 0.02 V) + (l mA + 0.1 mA) 10 M2
K = — 1 .98 V + 1 1 V-8 V= + 1.02 V
Therefore, to produce an output change of -I- 1 V required an input
change of + 1.02 V. Thus, the common drain amplifier has a voltage gain of
approximately 1 and no phase shift between input and output (Fig. 14-3). It
can also be said that output voltage changes approximately follow the input
voltage changes, hence the name source follower.
14-5
AC Analysis
of Common
Drain
Circuit
As in the case of the common source circuit, the ac equivalent circuit 14-5.1
for the common drain amplifier is drawn by replacing supply voltages and Equivalent
capacitors with short circuits, and replacing the device with its own ac
equivalent circuit. The common drain equivalent circuit is shown in Fig.
14-4. Note that the current generator is g m V gs , where V gs ** V t — V 0 . Also note
that R c is R x in parallel with R 2 (see Fig. 14-3).
From Fig. 14-4,
P.-4fX(rJ| Rl)
14-5.2
Voltage
Cain
and
Therefore,
Solving for V 0 ,
-4*
r d + R L
h~SmV,.~gm( V i- K)
v.-uW-
V.)
'd^ R L
r d +R L
K( r d+ R l) = g. K r d R L~gm K r d R L
K( r d + R L+ gn, r d R t) = g* K ' d R L
r d R.
V = e V —
o U ' r d + R L + g m T jR l
(14-6)
S
D
Figure 14-4. AC equivalent circuit for common drain amplifier.
315
The voltage gain is
316
Basic
FET
Circuits
= gm
T d R L
r d + R L + Sm r d R L
(14-7)
Example 14-4 The common drain amplifier in Fig. 14-3 uses a 2N5457 FET. Calcu-
late the typical value of circuit voltage gain.
solution
From Fig. 12-9,
r,= j^|=100kJ2
& -|y A |-3000 ( is
From Eq. (14-7),
A = 3000 X 10~ 6 X 100 X 10 3 X 10 X 10 3
" ( 100 X 10 3 ) + (10 X 10 3 ) + (3000 X 10 - 6 X 100 X 10 3 X 10 X 10 3 )
= 0.965
14-5.3 Consider Eq. (14-6):
Output
Impedance Tj R t
V 0 = g m V- —
o 'r d + R L + g m r d R L
g m V i is an output current directly proportional to V-, and (r d jR L )/(r d + jR l +
&* r A) = a resistance, Z 0 .
This can be rewritten
^ r d R L
r d + R L( 1+ gm r d)
[rd/( l+ Sm r d)] R L
[ r d/( l +gm r d)] +R L
-R I f ±
L U+t-r,
1
R >
(14-8)
317
AC Analysis
of ihe
Common
Drain Circuit
Figure 14-5. Modified equivalent circuit for common drain amplifier.
Using this knowledge, a modified equivalent circuit (Fig. 14-5) can be
drawn for the common drain amplifier.
The common drain amplifier of Fig. 14-3 has a FET with r d = 100 kfi
g„, = 3000 /iS. Calculate the circuit output impedance.
solution
r d
I00X10 3
1 +(3000 X10 _6 X 100 X 10 3 )
= 332 0
From Eq. (14-8)
Example 14-5
Z Q = 10kfl||332fl
10 kflx332 £2
10 kfl + 332 ft
Just as was the case in the common source circuit, the bias resistances
constitute the input resistance for a common drain amplifier. For the circuit
in Fig. 14-3 the input resistance is
14-5.4
Input
Impedance
Z-R,\\R 2 (14-9)
The drain-gate capacitance C gd is in parallel with Z t . The gate-source
capacitance C gt still exists between gate and source terminals, but since the
source voltage follows the gate voltage, only a fraction of the input signal
appears across the gate-source terminals. All the signal voltage appears
across C gd , however, so C gf has a negligible effect by comparison with C^.
The input capacitance begins to affect the circuit gain when X c * d is reduced
to several times the signal source impedance.
14-6
The
Common
Gate
Circuit
In the common gate circuit , the input signal is applied to the source
terminal, and the output is taken from the drain. The circuit in Fig. 14-6
also shows that the gate is grounded, that the load resistance R L is in series
with the drain, and a source resistance R s is included. A signal voltage V t is
developed across R s , and since the gate is grounded, V i is also developed
across the gate source terminals.
Assume an I D of 1 mA and a g m of 5000 /iS for the circuit of Fig. 14-6.
The drain voltage is
r D =y DD -(W
= 20 V — ( 1 mAxl0kS)-10V
The voltage drop across R s is
1^ = X
= 1 mAX 1 kfl=l V
This means that the source terminal is IV positive with respect to
ground, or to put it another way, ground is — IV with respect to the source
terminal. Since the gate is grounded, it is also —IV with respect to the
source terminal; i.e., the gate-source voltage Vqs = —IV.
If an input signal of +0.1 V is now applied to the source, the voltage
drop across R s becomes 1.1 V. Vcs also becomes — 1.1 V; i.e., is changed
by —0.1 V. This causes I D to be reduced. The new value of I D is
I D = 1 mA “(^ xA,/ J
-1 mA-(5000Xl0‘ 6 X0.1)
= 1 mA — 0.5 mA
= 0.5 mA
318
The new value of drain voltage is
V»=V D d-1 D Rl
= 20 -(0.5 mAXlOkfi)
= 15 V
Thus, an input signal of +0.1 V at the source caused V D to increase
from 10 to 15 V, i.e., a change of +5 V. Similarly, it can be shown that an
input of —0.1 V will cause the drain voltage to be reduced from 10 to 5 V.
From the above analysis it is seen that the common gate circuit
provides voltage amplification, and that the output voltage at the drain is in
phase with the input voltage at the source. Another very important point is
that since 1 D flows through the source as well as the drain, the signal voltage
source has to supply the I D changes. As will be seen, this gives the common
gate circuit a very low input impedance.
Replacing supply voltages and capacitors with short circuits gives the
ac equivalent circuit in Fig. 14-7(a). Substituting the device equivalent
circuit gives the complete ac equivalent circuit shown in Fig. 14-7(b). Note
that the current source (g m V is ) is connected between the drain and the
source terminals, as always. However, since the source and the drain are the
input and output terminals, respectively, for the common gate circuit,
( g m V v ) appears between the input and the output.
The output voltage is
and
V-l d X{f 4 \\R L )
-4x
*d+ R L
4
g m V V =im
V,
V = gm (/ X
T d R L
r d +R L
The voltage gain is
gm r 4 R L
319
AC Analysis
of the
Common
Gate Circuit
14-7
AC Analysis
of the
Common
Gate Circuit
14 - 7.1
Equivalent
Circuit
14 - 7.2
Voltage
Gain
A,
r, + Rt
( 14 - 10 )
320
Basic
FET
Circuits
Example 14-6
14-7.3
Output
Impedance
Figure 14-7. AC equivalent circuits for common gate circuit.
This is the same as the voltage gain equation for the common source
amplifier, except that the gain is a positive quantity. The absence of a minus
sign from the gain formula indicates that V 0 is in phase with V-, as shown in
Fig. 14-6.
The common gate amplifier in Fig. 14-6 uses a 2N5457 FET. Calcu-
late the typical value of circuit voltage gain.
solution
The calculation is exactly the same as for Example 14-1, except for the sign
change.
0 T R
A 0 = m - ~ = 27.3 (see Example 14-1)
r d+ R L
Referring to the ac equivalent circuit in Fig. 14-7(b), note that the
common gate output impedance is R L in parallel with r d .
Z=R L \\r d ^R L
( 14 - 11 )
Z 0 is, of course, the low-frequency output impedance. At high frequencies,
this will be modified by the parallel capacitance C gd .
The ac equivalent circuit of Fig. 14-7(b) shows that, ignoring the
current through R s> the input current is I d .
'« = g m V g s = g m V t
Thus, the input impedance to the device source terminal is VII. =
The circuit input impedance is
14-7.4
Input
Impedance
z t = —
g m
Rs
(14-12)
Actually, R L and r d can be shown to be involved in R t> but the
difference is quite negligible.
Calculate the input resistance for the common gate amplifier in Fig. Example 14-7
14-6. Assume that the device is a 2N5457.
solution
From the data sheet for the 2N5457 (Fig. 12-9),
*,-1^1-3000 ,1 S
or — = ! =333 0
g„ 3000 X 10~ 6
From Eq. (14-12),
333X 1 kS 2
333+1 kfi
= 250 n
The common gate amplifier has a very low input impedance which
requires that the signal have an even lower source impedance. With the
common source circuit, the Miller effect amplifies the input capacitance and
limits the high-frequency response. Miller effect occurs only where the
output voltage is antiphase to the input. Where the output is in phase with
the input, as in the common gate circuit, the capacitance between input and
321
322
Basic
FET
Circuits
output terminals tends to be reduced instead of amplified. The only input
capacitance of any importance is the gate source capacitance C gs . This low
input capacitance gives the common gate circuit a much better high-
frequency response than the common source circuit.
14-8
BI-FET
and BI-MOS
Circuits
The major advantage of FET’s over bipolar transistors is the very high
input resistance of the FET. In the case of JFET’s and ordinary MOSFET’s,
i.e., not V-FETs, the gain of a single stage is considerably less than that of a
bipolar single-stage amplifier. For a bipolar stage, ^ = 200 to 500, typically.
For a FET, A v = g m R L . With a typical g m of 4 mS and = 10 kfi, ^ = 40.
(For a V-FET, g m could easily be 100 mS, giving A v = 1000.)
Field effect transistors are frequently combined with bipolar stages to
give multistage circuits which have a very high input resistance. Where
JFET’s are combined with bipolars, the circuits are known as BI-FET
circuits. When MOSFET’s and bipolars are combined, the name BI-MOS is
applied. Several BI-FET and BI-MOS amplifier circuits are illustrated in
Figs. 14-8 through 14-10.
Figure 14-8 shows a self-biased JFET stage capacitor coupled to a
common emitter stage with emitter current bias. The circuit has a very high
input resistance and an overall voltage gain less than that of a two-stage
bipolar circuit.
Figure 14-8. Two-stage BI-FET ampfifier.
Figure 14-9. BI-MOS DC feedback pair.
(a) Using p-channel FETs (b) Using n-channel FETs
Figure 14-10. Differential FET input stages used in BI-FET operational amplifiers.
323
Example 14-8
Analyze the BI-FET circuit in Fig. 14-8 to determine overall voltage
gain, input impedance, and output impedance. The FET has g m = 5 mS, and
the bipolar transistor has k u — 2 k£2 and fy, = 100.
solution
Input impedance Z'czR l = 1 Mfi.
Output impedance Z 0 c^.R 6 = 5.6 kfi.
4> = 4»1 X ^d2
=^Ax
fy^Z.2
where R L1 = /? 2 ||/? 4 ||/y
i4„ = 5 mA/V[3 kS2|| 100 kfi||47 kfi||2 kS2] X —g —
=il600
The circuit in Fig. 14-9 is a BI-MOS version of the DC feedback pair
explained in Section 9-3. is self-biased with an external gate voltage
derived from the emitter resistances {R b and R 6 ) of (? 2 - The base of Q, 2 is
directly connected to the drain terminal of If I Dl becomes greater than
the intended design level, there will be a larger voltage drop across R x and
R 2 . Consequently, V B 2 is lower than the design level. This means that Kn is
also lower than intended, and Vos is less than the design level. The result is
that I D is reduced toward the intended design level. The same line of
reasoning can be applied to show that, when I D is lower than intended, the
feedback effect tends to increase I D toward the design level.
Like the bipolar DC feedback pair, this BI-MOS circuit is a two-stage
amplifier using a minimum number of components. Unlike the bipolar
circuit, the BI-MOS DC feedback pair has a very high input resistance.
The differential FET amplifiers illustrated in Fig. 14-10 are typical of
input stages employed in BI-FET and BI-MOS IC operational amplifiers.
The double-ring symbol in the common source circuit of the FET’s repre-
sents a constant current circuit (see Figs. 9-10 and 11-11). This arrangement
internally stabilizes the FET drain current no matter what the gate bias
voltage (within limits).
Basically, one of these FET differential circuits is connected as an
additional stage preceding a bipolar operational amplifier like that shown in
Fig. 9-8. Again, the FET’s are employed essentially for the very high input
resistance; however, improved slew rates and better frequency responses also
result.
324
Common source circuit. FET circuit in which the input is applied between
gate and source, and the output is derived from drain and source.
Common drain circuit. FET circuit in which the input is applied between
gate and drain, and the output is derived from source and drain.
Common gate circuit. FET circuit in which the input is applied between
source and gate, and the output is derived from drain and gate.
Source follower. Another name for the common drain amplifier.
BI-FET. Multistage circuit combining bipolar transistors with JFET’s.
BI-MOS. Multistage circuit combining bipolar transistors with
MOSFET’s.
14-1. Sketch the circuit of a common source JFET amplifier. Identify all
components, indicate voltage polarities, and show the input and
output waveforms. Briefly explain the operation of the circuit.
14-2. Draw the ac equivalent circuit for a common source amplifier, and
derive expressions for common source voltage gain and output imped-
ance.
14-3. Repeat Question 14-1 for a common drain amplifier.
14-4. Draw the ac equivalent circuit for a common drain amplifier, and
derive expressions for voltage gain and output impedance.
14-5. Repeat Question 14-1 for a common gate amplifier.
14-6. Draw the ac equivalent circuit for a common gate amplifier, and
derive expressions for voltage gain, output impedance, and input
impedance.
14-7. Sketch typical BI-FET and BI-MOS circuits, explain the operation
of each circuit, and briefly discuss the advantages of such circuits.
14-1. A common source amplifier using a 2N5458 FET (specification in
Fig. 12-9) has /? A = 6.8 kft and R c — 2.2 Mf2. Calculate the voltage
gain and low-frequency output and input impedances of the circuit.
14-2. (a) Calculate the input capacitance for the amplifier in Problem
14-1.
(b) Assuming that Cds “ ^ pF for the device used in the circuit of
Problem 14-1, calculate the output impedance at a signal frequency
of 1 MHz.
14-3. A common source amplifier is to be designed to have a voltage gain
of at least 40. If a 2N5459 FET is employed, determine the value of
R l for the circuit. Also calculate the typical and maximum values of
circuit voltage gain.
14-4. Calculate the typical and maximum value of input capacitance for
the circuit in Problem 14-3.
14-5. A common drain amplifier has R L = 6.8 k!2, /?, = 2.2 MS2, and /? 2 = 1
Glossary of
Important
Terms
Review
Questions
Problems
325
326
Basic
FET
Circuits
Mft. The FET employed has r d = 120 kft and g m = 5000 juS. Calculate
the input impedance, output impedance, and voltage gain.
14-6. A common drain amplifier is to have an output impedance of
approximately 200 ft. Select a suitable FET from the data sheet in
Fig. 14-9. If R l is 1 kft, calculate the typical, maximum, and
minimum values of Z 0 . Also calculate the typical voltage gain for the
circuit.
14-7. A common gate amplifier has R L = 6.8 kft and R s = 870 ft. If the FET
used in the circuit is a 2N5458, calculate the voltage gain, input
resistance, and output resistance.
14-8. A common gate circuit using a 2N5457 FET has a voltage gain of 36.
If the FET g m is the typical value for the device, calculate the value
of R l . Also calculate the maximum and minimum values of A v .
14-9. The circuit in Fig. 14- 10(b) has a 2-mA constant current generator
and uses JFET’s with the characteristics shown in Fig. 13-6. R x = R 2
= 2.2 kft, V Gl = V G2 = ~3 V, V cc = + 12 V, and V EE =-\2 V. De-
termine the maximum and minimum values of drain and source
voltages.
14-10. For the circuit described in Problem 14-9, calculate the ac voltage
gain from the gate of one FET to its drain terminal. Refer to the
bipolar differential amplifier circuit in Chapter 9 for guidance.
The
Tunnel
Diode
A tunnel diode (sometimes called an Esaki diode after its inventor, Leo
Esaki) is a two-terminal negative resistance device which can be employed as
an amplifier, an oscillator, or a switch. Because of its very fast response to
inputs, it is almost exclusively a high-frequency component. Tunnel diodes
require smaller bias voltages and lower load resistances than most other
electronic devices.
Recall from Chapter 2 that the width of the depletion region at a
/^-junction depends upon the doping density of the semiconductor material.
Lightly doped material has a wide depiction region, while heavily doped
material has a narrow region. In the case of the tunnel diode, the junction is
formed of very heavily doped material, and consequently the depletion
region is very narrow.
CHAPTER
15
15-1
Introduction
15-2
Theory of
Operation
15-2.1
Depletion
Region
327
328
The
Tunnel
Diode
The depletion region is an insulator since it lacks charge carriers, and
usually charge carriers can cross it only when the external bias is large
enough to overcome the barrier potential. Barrier potentials are approxi-
mately 0.7 V for silicon and 0.3 V for germanium. However, because the
depletion region in a tunnel diode is extremely narrow, it does not constitute
much of a barrier to electron flow. Consequently, a small forward or reverse
bias (not large enough to overcome the barrier potential) can give charge
carriers sufficient energy to cross the depletion region. When this occurs, the
charge carriers are said to be tunneling through the barrier.
15 - 2.2
Energy Band
Diagrams
Consider the silicon energy band diagrams shown in Fig. 15-1. If the
material is normally doped (either n-type or p- type), electrons fill all the
holes in the valence band of energy levels and the conduction band is empty
[Fig. 15-l(a)].
(a) Normally doped
p and n type
(b) Very heavily
doped p- type
(c) Very heavily
doped /7-type
Figure 15-1. Energy band diagrams for normally doped and very heavily doped semicon-
ductor material.
When semiconductor material is very heavily doped with holes (i.c., 329
/>-type), there is a shortage of electrons and the valence band cannot be Theory of
regarded as filled. The result is that at the top of the valence band there is a Operation
layer of empty energy levels. This is illustrated in Fig. 15- 1(b). With very
heavily doped «-type material, there is an abundance of electrons. Conse-
quently, electrons fill the valence band and create a layer of filled energy
levels at the bottom of the conduction band [Fig. 15-l(c)].
The energy band diagram for a heavily doped unbiased /w-junction is
shown in Fig. 15-2(a). Note that the depletion region is very narrow' and
that the filled levels on the n-side are exactly opposite those on the p- side. In
this condition, no tunneling occurs because there are no empty lower energy
levels to which electrons from either side might cross the depletion region.
Note also that the conduction and valence bands on the />-side are higher
(negatively) than those on the n-side. This is a result of the depletion region
and barrier potential being created by electrons crossing from the n-side to
the />-side. The n-side lost negative charges and the />-side gained them.
When the junction is reverse biased (negative on the />-side, positive on
the n-side), filed energy levels on the />-side are opposite empty energy levels
on the n-side. The result is that electrons tunnel through the barrier from the
higher-energy levels on the />-side to the lower levels on the n-side [Fig.
15-2(b)]. Despite the fact that the junction is reverse biased, substantial
current flows. Figure 15-2(c) shows that with increasing reverse bias more
electrons tunnel from the />-side to the n-side and a greater current flows.
Therefore, the reverse characteristic of a tunnel diode is linear, just like that
of a resistor.
15 - 2.3
Reverse-
Biased
Tunnel
Diode
When the tunnel diode is forward biased, its initial behavior is similar
to when it is reverse biased [Fig. 15-3(a)]. In this case, some of the filled
levels on the n-side are raised to a higher energy level than empty levels on
the p- side. Electron tunneling now occurs from the n-side to the />-sidc.
When the forward bias is increased, more and more of the electrons on the
n-side are raised to a higher level than the empty levels on the />-sidc. This
results in more tunneling of electrons from the n-side to the />-side. Eventu-
ally, however, a maximum level of tunneling is reached when the band of
filled energy levels at the bottom of the conduction band on the n-side is
directly opposite the band of empty energy levels at the top of the valence
band on the />-side [Fig. 15-3(b)]. With further increase in forward bias, part
of the band of filled levels on the n-side is raised to an energy level
corresponding to the forbidden gap on the p- side. Electrons cannot tunnel to
a forbidden energy level; thus, as illustrated in Fig. 15-3(c), the current flow
due to tunneling is reduced. With continued increase in forward bias, the
tunneling continues to be reduced. When all the band of filled levels at the
bottom of the conduction band on the n-side is raised to a level correspond-
ing to the forbidden gap on the />-sidc, Fig. 15-3(d), the current flow due to
15 - 2.4
Forward-
Biased
Tunnel
Diode
(a) Unbiased tunnel
diode junction
(b) Small reverse
bias
(c) Increasing reverse
bias
Figure 15-2. Energy band diagrams and characteristic for reverse-biased tunnel diode.
330
Conduction
band
Valence
band
More
tunneling
(a) Small
forward
(d ) Forward
Figure 15-3. Energy band diagrams and characteristic for forward -biased tunnel diode
331
332
The
Tunnel
Diode
tunneling is reduced to a minimum. Now, however, the normal process of
current flow across a forward-biased junction begins to take over, as the bias
becomes large enough to overcome the barrier potential. Current now
increases as the voltage increases, and the final portion of the tunnel diode
forward characteristics is similar to that for an ordinary /^-junction.
15-3
Tunnel
Diode
Symbol,
Characteristics,
and
Parameters
A typical tunnel diode characteristic is shown in Fig. 15-4, along with
frequently employed symbols for the device. The peak current ( I p ) and valley
current (/J are easily identified on the characteristic as the maximum and
minimum levels, respectively, of I F prior to the device being completely
forward biased. The peak voltage ( V p ) is the E D level corresponding to I pi and
the valley voltage ( V D ) is the E D level at I v . V F is the forward voltage drop when
the device is completely forward biased. The broken line on Fig. 15-4(a)
r
•) Anode <->
Anode ^
JT X
r
^ /
() Cathode (
Cathode °
(b) Symbols
Figure 15-4. Tunnel diode characteristics and symbols.
shows the characteristic for an ordinary forward-biased diode. It is seen that
this joins the tunnel diode characteristic as V F is approached.
When a voltage is applied to a resistance, the current normally
increases as the applied voltage is increased. Between I p and I c on the tunnel
diode characteristic, I D actually decreases as E D is increased. This region of
the characteristic is named the negative resistance region , and the negative
resistance R D of the tunnel diode is its most important property.
The value of the negative resistance may be determined by calculating
the reciprocal of the slope of the characteristic in the negative resistance
region. From Fig. 15-4(a), the negative resistance R D = (&E D /1I D ), and the
negative conductance G D = (hI D /&E D ).
If R d is measured at different points on the negative resistance portion
of the characteristic, slightly different values will be obtained because the
slope is not constant. Therefore, R D is usually specified at the center of the
negative resistance region.
Typical tunnel diode parameters are as follows:
Peak current I p = 1 to 100 mA
Peak voltage V p — 50 to 200 mV
Valley current I v = 0.1 to 5 mA
Valley voltage V v = 350 to 500 mV
Forward voltage V F = 0.5 to 1 V
Negative resistance R D = — 10 to - 200 £2
In Chapter 3 it was shown that a straight-line approximation of diode
characteristics can sometimes be conveniently employed. This is true also of
the tunnel diode, for which the piecewise linear characteristics can be con-
structed from the data provided by the device manufacturer.
Construct the piecewise linear characteristics and determine R D for the
1N3712 from the following data: I p = 1mA, 7, = 0. 12mA, F /> = 65mV, F c = 350
mV, and ^ = 500 mV (at I F = I P ).
solution
Refer to Fig. 15-5. Point 1 is first plotted at I p = 1 mA and ^, = 65 mV. Point
2 is plotted at / p = 0.12 mA and F„ = 350 mV. The origin and point 1 arc
joined by a straight line to give the initial portion of the forward characteris-
tic. A straight line is now drawn between points 1 and 2 to give the negative
resistance region. Point 3 is plotted at 1^ = 500 mV and J F = I P , and the
forward voltage portion of the characteristic is drawn at the same slope as
the line between 0 and point 1. Sometimes a second value of V F at \l P is
given so that the forward region can be plotted more accurately. A horizon-
tal line is then drawn from point 2 to this line to represent the valley region
of the characteristic.
333
Piecewise
Linear
Characteristics
15-4
Piecewise
Linear
Characteristics
Example 15-1
334
The
Tunnel
Diode
Figure 15-5. Tunnel diode piecewise linear characteristic.
R d is determined by calculating the reciprocal of the slope of the
negative resistance region of the characteristic.
_ 350 mV -65 mV
-M d -(1 mA — 0.12 mA)
285 mV
- 0.88 mA
= —324 ft
15-5
Tunnel
Diode
Equivalent
Circuit
The equivalent circuit shown in Fig. 15-6 is for a tunnel diode biased
in the negative resistance region. Therefore, it consists of the negative
resistance R D shunted by the junction capacitance C D . Values of C D range
from 5 to 100 pF. R s represents the resistance of the connecting leads and
the semiconductor material, and is of the order of 1 fl. L s , which is typically
0.5 nH, is the inductance of the connecting leads to the tunnel diode.
Figure 15-6. Tunnel diode equivalent circuit.
Because of the presence of L s and C D in the equivalent circuit, the 335
tunnel diode has a self- resonance frequency (/,„), which may range from 700 Tunnel
MHz to 4 GHz. The negative resistance determined from the characteristic ParaMd
does not allow for the effects of C D shunting R D at high frequencies. Thus, Amplifier
the effective negative resistance becomes progressively smaller as operating
frequency increases, and there is a frequency at which the effective R D
becomes zero. This is known as the resistive cutoff frequency (f n ). Values of f n
range from 1 .6 to about 3.3 GHz.
For operation as an amplifier, a tunnel diode must be biased to the
center of its negative resistance region. Figure 15-7(a) shows the basic circuit
of a parallel amplifier. The load resistor ( R L ) is connected in parallel with
the diode (/),) and supplied with current from battery voltage ( E B ) and
signal ( e s ). Figure 15-7(b) shows the dc conditions of the diode when the
signal voltage e s = 0 and when * s =±100 mV. Operation of the circuit is
explained by the following example.
15-6
Tunnel
Diode
Parallel
Amplifier
(a) Basic parallel amplifier
(b) Device current and voltage
conditions for e s = 0 and
e s » ± 100 mV
Figure 15-7. 8asic circuit of tunnel diode parallel amplifier with device current and
voltage conditions.
Example 15-2
Assuming that E B and e s have zero source resistance, calculate the
current gain, voltage gain, and power gain for the tunnel diode parallel
amplifier circuit in Fig. 15-7(a).
solution
When e s = 0.
E b + e s = E b = 200 mV
E n = (E„ + e s ) = 200 mV
From point Q on the characteristic, 7 D = 2mA and E R = (E B + e s ) =
200 mV.
4 =
200 mV
80 0
= 2.5 mA
— / D + I L — 4.5 mA
When e s — + 1 00 m V ,
E B + e s = 300 mV = E D = E R
From point A on the characteristic, 7 D = lmA and 7 L = 300 mV/
80 £2 = 3.75 mA.
I B = 1 mA 4- 3.75 mA = 4.75 mA
Change in I L = A I L = 3.75 mA — 2.5 mA = 4- 1 .25 mA
Change in 7 5 = A7 5 = 4.75 mA — 4.5 mA= 4-0.25 mA
When e s = — 1 00 m V,
E b 4- e s = 100 mV ~E D = E R
From point B on the characteristic, 7^ = 3 mA and 7^ = 100 mV/
800= 1.25 mA.
I B = 3 mA 4- 1.25 mA = 4.25 mA
A I L = 1 .25 mA — 2.5 mA = — 1.25 mA
A/^ = 4.25 mA — 4.5 mA= —0.25 mA
It is seen that, when e s = ± 100 mV, A I L = ±1.25 mA and A I B = ±0.25 mA.
Also, A I B is an input current ( i s ) produced by signal voltage e s , and A I L is an
output current (t 0 ) through the load resistor R L .
336
The current gain is
337
Gain
, «. 1.25 mA . t< ’ ua ' ion
I, = — = — — = 5 fora
i, 0.25 mA Parallel
Amplifier
The output voltage is
e 0 = A E r = e t
The voltage gain is
e m
A = — = l
‘s
The power gain is
A p = A i XA 0 = 5
It is seen that a tunnel diode parallel amplifier has current gain and
power gain but no voltage gain.
From Fig. 15-7(b), the value of R D can be determined as
From Example 15-1, when the signal voltage (e t ) changed by +100
mV, the diode current (I D ) changed from 2 to 1 mA. Thus,
for e. = + 100 mV
A I D can also be calculated as
e s 100 mV
/o= «: = ^Toofi = - lmA
15-7
Gain
Equation
for a
Parallel
Amplifier
and i 0 = M L = e s /R L .
i, = U B = U L -U D
_ e s e s
R L Rd
. i. >J_Rl
•“ ■, “ (*./*l)-(‘./Rd) ~ (1 /R l )-(\/R d )
338
The
Tunnel
Diode
15-8
Practical
Parallel
Amplifier
Circuit
Example 15-3
For the parallel amplifier
A,=
( 15 - 1 )
Note that R D is already taken as negative for this formula, so that only
the absolute value of R D (i.e., no negative sign) should be employed in
calculating A t .
For /?£ = 100 S2 and R L — 80 12, as in Example 15-2,
. 100 _ e
' 100-80
From the equation for A- it is seen that
When R l <^R d , A t « 1
and When ^,<1
When R l — R d , A t = oo, which means that the circuit is likely to
oscillate. Therefore, for best gain R L should be slightly less than R D .
Figure 15-8 shows the circuit of a practical tunnel diode parallel
amplifier. The signal voltage e s and load resistor R L are capacitor coupled to
the diode, while dc bias is provided by voltage E B and potential divider R x
and R 2 . Inductor L x and capacitor C, isolate the bias supply from ac signals.
Operation of the amplifier is best understood by drawing the dc and ac
equivalent circuits.
Draw the dc and ac equivalent circuits for the tunnel diode parallel
amplifier circuit of Fig. 15-8. Also draw the dc load line on the device
characteristic. Determine the circuit bias conditions and calculate the
amplifier current gain.
Figure 15-8. Practical tunnel diode parallel amplifier circuit.
solution
dc equivalent circuit
The capacitors are a dc open circuit, and the inductor has a winding
resistance R w . Therefore, the dc equivalent circuit consists of E B , R v R 2 , R Wy
and Z), as shown in Fig. 15-9(a).
ac equivalent circuit
For ac signal frequencies, the impedance of L, is much higher than that of
the diode or R L . Therefore, L { together with E B , R {y R 2 , and C, are all left
out of the ac equivalent circuit. C 2 and C 3 are ac short circuits, so the ac
equivalent circuit consists of e s , R Sy D ly and R L [Fig. 15-9(b)].
dc load line and bias conditions
E By /?,, and R 2 can be replaced by the open-circuit voltage across R 2 and the
dc source resistance ( R B ) seen when looking toward E B at R 2 [Fig. 15-9(a)].
This is simply the Thevenin equivalent circuit of E By R ly and R 2 .
The open-circuit voltage
and
£o =
E b X R 2
z?, + z? 2
12 VX 47
2.2 kfl + 47 fl
= 250 mV
,XZ? 2 2.2 kfl X 47
R x + R 2 2.2 kfl + 47 £2
To this must be added R Wi which is typically about 35 S2.
The simplified dc equivalent circuit is now the diode in series with a
bias of 250 mV and a total resistance of approximately 80 £2. This is shown
in Fig. 15- 10(a). The dc load line can now be drawn in the usual way.
Ed = ^0~Ud^ ^L(dc))
where R L(dc ) ~^b + r w- When I D = 0, E n = E 0 - 0 = 250 mV. Plot point A on
the characteristic [Fig. 15- 10(b)] at I D = 0 and E D — 250 mV.
R, R w
— m
i W\A
n+ ,
. r
\ S
r r
$R 7
0,ui
[ ) R L i
o - «
V
J <
J 1
(a) dc equivalent circuit ac equivalent circuit
339
Practical
Parallel
Amplifier
Circuit
Figure 15-9. DC and AC equivalent circuits for tunnel diode parallel amplifier in Fig.
15-8.
80 ft
-m-
340
The
Tunnel
Diode
250 mV
(a) Simplified dc equivalent current
Ed
(b) dc load line
Figure 15-10. Simplified DC equivalent circuit and dc load line plotting for tunnel diode
parallel amplifier.
When I D = 1 mA, £^ = 250 mV — (1 mAX80 12) = 170 mV. Plot point
B at I D = 1 mA and E D = 1 70 mV.
Now join points A and B together to give the dc load line. It is seen
that the dc load line for R L = 80 12 intersects the device characteristic at
point Q in the middle of the negative resistance region. This is the quiescent
point for the circuit, and it defines the dc voltage and current conditions.
From point Q, the dc bias conditions are /^c^O.57 mA, £^^204 mV.
ac load = R L = 300 12
current gain
For the IN3712, R D = 324 S2 (see Example 15-1).
From Eq. (15-1),
A =
324
324-300
13.5
341
Glossary of
Important
Terms
A tunnel diode series amplifier may also be constructed. In this case the
device is connected in series with the load, and voltage amplification is
obtained instead of current amplification. Oscillators and switching circuits
may also be constructed using tunnel diodes.
Heavily doped material. Semiconductor material from which tunnel di- Glossary of
odes are manufactured — heavily doped to provide large quantities of Important
p- type or n-type impurities. Terms
Filled energy levels. Semiconductor energy levels which are completely
occupied by electrons.
Empty energy levels. Semiconductor energy levels from which electrons
are absent — filled with holes.
Forbidden energy levels. Semiconductor energy levels which cannot be
occupied by electrons — energy levels in the forbidden gap.
Depletion region. Region at /m-junction depleted of charge carriers — very
narrow region in a tunnel diode.
Tunneling. Electrons crossing the depletion region at a /w-junction without
being given sufficient energy to overcome the barrier potential are said
to be tunneling through the barrier.
Negative resistance region. Region of tunnel diode forward characteristic
in which the current decreases as the voltage is increased.
Negative resistance. Reciprocal of the slope of the negative resistance
region calculated as (voltage change)/ (current change).
Peak current ( 1 ft ). Forward current that flows just prior to the negative
resistance region.
Peak voltage ( F ' p ). Forward-bias voltage required to produce peak current.
Valley current (7^). Forward current that flows just after negative resis-
tance region.
Valley voltage ( V v ). Forward-bias voltage necessary to produce valley
current.
Forward voltage ( V F ). Forward-bias voltage necessary to bias the tunnel
diode beyond the negative resistance and valley regions.
Piecewise linear characteristic. Straight-line approximation of device
characteristic.
Self-resonance frequency. Frequency at which the inductance and capaci-
tance of a tunnel diode will resonate.
342
The
Tunnel
Diode
Review
Questions
Problems
Effective negative resistance. Value of tunnel diode negative resistance at
a given high frequency — less than the dc negative resistance value.
Resistive cutoff frequency. Frequency at which negative resistance goes to
zero.
Parallel amplifier. Current amplifier circuit in which the tunnel diode and
load resistor are in parallel.
Series amplifier. Voltage amplifier in which the tunnel diode and load
resistor are in series.
15-1. Sketch energy band diagrams for (a) normally doped p - type and
«-type semiconductor material; (b) very heavily doped />-type; (c)
very heavily doped n-type. Briefly explain.
15-2. Draw typical reverse characteristics for a tunnel diode. Also sketch
the energy band diagrams for the tunnel diode, and show the effect of
reverse bias. Briefly explain.
15-3. Make a sketch showing the approximate shape of the forward char-
acteristics for a tunnel diode. Sketch the tunnel diode energy band
diagrams, showing the effect of increasing forward bias. Explain the
shape of the characteristics in terms of the energy band diagrams.
15-4. Sketch typical forward characteristics for a tunnel diode, showing
realistic voltage and current levels. Label all important points and
regions on the characteristics, and show how the most important
parameter of the tunnel diode can be derived from the characteris-
tics.
15-5. Sketch the equivalent circuit for a tunnel diode and explain the
origin of every component. State typical values for each component,
and define self-resonance frequency, resistive cutoff frequency, and
effective negative resistance.
15-6. Sketch the basic circuit of a tunnel diode parallel amplifier. Briefly
explain how it operates.
15-7. Draw a practical parallel amplifier circuit for a tunnel diode. Ex-
plain the function of each component. Also draw the dc and ac
equivalent circuits of the parallel amplifier.
15-1. A tunnel diode is specified as having I p = 6 mA, 1^ = 50 mV, 4 = 0.5
mA, V v = 400 mV, and 1^ = 550 mV at l F = I p - Construct the piece-
wise linear characteristics, and determine the value of negative
resistance for the device.
15-2. Construct the piecewise linear characteristics and determine R D for a
IN3715 from the following data: l p — 2.2 mA, 4 = 0*21 mA, V p = bb
m V, V v = 355 mV, and F f = 510 mV at I F = I p -
15-3. A parallel amplifier uses the tunnel diode specified in Problem 15-1
and a load resistance of 47 ft. Bias voltage is 225 mV from a dc
source having zero resistance. Draw the dc load line for the circuit,
and calculate the current gain, voltage gain, and power gain.
15-4. A IN3715 is to be connected as a parallel amplifier. Using the
piecewise linear characteristics drawn for Problem 15-2, draw an
appropriate dc load line and determine suitable values of R L , R B , E B ,
and e t . Calculate the circuit current gain.
15-5. A practical tunnel diode parallel amplifier circuit (Fig. 15-8) has the
following components: E B — 5 V, /?, = 220 ft, R 2 = 12 ft, C,=0.5 /xF,
R w = 0.5 ft, L, = 20 mH, C 2 = 0.2 #xF, C 3 = 0.5 /xF, and R L = 15 ft. The
tunnel diode used has I p = 5 mA, E p = 50 mV, I 0 = 1 mA, and V v = 400
mV. Draw the ac and dc equivalent circuits for the amplifier.
Construct the piecewise linear characteristics and draw the dc load
line. Calculate the circuit current gain.
343
Problems
CHAPTER
16
16-1
Introduction
16-2
SCR
Operation
The
Silicon
Controlled
Rectifier
The silicon controlled rectifier (SCR) can be thought of as an ordinary
rectifier with a control element. The current to the control element, which is
termed the gate, determines the anode- to-cathode voltage at which the
device commences to conduct. The gate bias may keep the device off, or it
may permit conduction to commence at any desired point in the forward
half-cycle of a sinusoidal input. The SCR is widely applied as an ac power
control device. Many other devices, such as the DIAC, TRIAC, etc., are
based on the SCR principle. Collectively, SCR-type devices are known as
thyristors. This term is derived from thyratron and transistor , the thyratron being
a gas-filled tube which behaves like an SCR.
Figure 16- 1(a) shows why an SCR is sometimes referred to as a
four-layer device or pnpn device. The SCR consists of four layers of semiconduc-
tor material, alternately />-type and n-type. The layers are designated p v n v
p 2 , and n 2 in Fig. 16-1 (a). Three junctions are produced: y i>v / 2 , and / 3 , and
there are three terminals, anode ( A ), cathode (C), and gate ( G ).
344
(a) (b) ( C ) (d)
Figure 16-1. (a) and (b) SCR basic construction; (c) two-transistor equivalent circuit; (d)
symbol.
To understand the operation of the device, it is necessary to imagine
layers rt, and p 2 split into n v n\, p 2> and p 2 , as shown in Fig. 16-1 (b). Since
is connected to n[, and p 2 is connected to p 2 , this has not really changed
anything. However, it is now possible to think of p l *n l ,p 2 as a pnp transistor,
and n\,p 2 ,n 2 as an npn transistor. Replacing the transistor block representa-
tions in Fig. 16-1 (b) with the pnp and npn circuit symbols gives the tu>o- transis-
tor equivalent circuit [Fig. 16- 1(c)]. It is seen that Q 2 collector is connected to
(£, base, and the (), collector is commoned with () 2 base. The (), emitter is
the SCR anode terminal, the () 2 emitter is the cathode, and the gate is the
juction of the (), collector and the base. The circuit symbol for the SCR
is shown in Fig. 16- 1(d).
To forward bias the SCR, a voltage is applied as shown in Fig. 16-2(a),
positive on the anode, negative on the cathode. If the gate is left uncon-
nected, only small leakage currents flow and both transistors remain cut off.
[Reference to Fig. 16- 1(a) shows that the leakage currents are the result of
junction J 2 being reverse biased when A is positive and C is negative.]
When a negative gate-cathode voltage is applied, the () 2 base-emitter
junction is reverse biased, and only small leakage currents flow, so both
transistors remain off. A positive gate-cathode voltage [Fig. 16-2(b)] forward
biases the base-emitter junction and causes a base current I B2 to flow',
consequently producing collector current I C2 . Since I C2 is the same as / fl) , Q,
also switches on and I cx flows, providing base current I B2 . Each collector
current provides much more base current than is needed by the transistors,
and even when the gate current ( I G ) is cut off the transistors remain on,
conducting heavily with only a small SCR anodc-to-cathode voltage drop.
346
The
Silicon
Controlled
Rectifier
16-3
SCR
Characteristics
and
Parameters
The ability of the SCR to remain on when the triggering current is removed
is referred to as latching.
To switch the SCR on, only a brief pulse of gate current is required.
Once switched on , the gate has no further control, and the device remains on
until the anode-cathode voltage is reduced to near zero. The SCR can also
be triggered on with the gate open circuited, if the anode-to-cathode voltage
is made large enough. Consider Fig. 16- 1(a) again. With a forward bias
(positive on A , negative on C), junctions J x and J 3 are forward biased while
junction J 2 is reverse biased. When V F is made large enough, J 2 will break
down due to avalanche effect (Chapter 11). The resultant current flow
across the junction constitutes collector current in each transistor. Each
collector current again feeds base current into the other transistor, and both
transistors switch on.
Typical forward and reverse characteristics for an SCR are shown in
Fig. 16-3. First consider the reverse characteristics, and refer again to Fig.
16-1 (a). When a reverse bias is applied (negative on A , positive on C\J 2 is
forward biased while J x and J 3 are reverse biased. When the reverse voltage
~Vak is small, a reverse leakage current (7^) flows (see Fig. 16-3). This is
typically around 100 /xA and is sometimes referred to as the reverse blocking
current. As the level of reverse voltage is increased, Jrx remains approxi-
mately constant until Vak becomes large enough to cause J ] and J 3 to
break down. As shown in Fig. 16-3, the reverse current increases very rapidly
when the reverse breakdown voltage is reached, and if I R is not limited the
device would be destroyed. The region of the reverse characteristics before
reverse breakdown is termed the reverse blocking region.
When the SCR is forward biased with 7 C = 0, two junctions (/, and J 3 )
are forward biased and J 2 is reverse biased. With small anode-to-cathode
voltages (+ Vak)> a small leakage current flows (Fig. 16-3). This forward
347
SCR
Characteristics
and
Parameters
leakage current (I FX ) is approximately equal to and has a typical value of
100 /iA. With I G at zero, I F remains at I FX until + V AK is made large enough
to cause the reverse-biased J 2 junction to break down. The fonvard voltage
at this point is termed the forward breakover voltage V^soy When V ^ fl0) is
reached, the two component transistors () , and 0% are immediately switched
on into saturation as already explained, and the anode-cathode voltage falls
to the forward conduction voltage ( V F ).
So far the forward characteristics have been discussed only for the case
of I c — 0. Now consider the effect of I c greater than zero. As already shown,
when 4- V AK is less than and I c is zero, a small leakage current flows.
This is too small to have any effect on the level of + Vak at which switch-on
occurs. When I G is made just slightly larger than the junction leakage
currents, it will have a negligible effect on the level of + Kuc for switch-on;
see I Gl in Fig. 16-3. Now consider the opposite extreme. When I c is made
larger than the minimum base current required to switch () 2 on, the SCR
remains off until + Kuc is large enough to forward bias the base-emitter
junctions of (), and Q This is illustrated in Fig. 16-3 where it is seen that
when I c = switch on occurs when + Vak reaches the relatively low
voltage of V 4 .
Between i and 4 there are gate current levels which permit device
switch on at levels of + V AK greater than V 4 but less than
348
The
Silicon
Controlled
Rectifier
16-4
SCR
Specifications
The forward conduction voltage ( V F ) is made up of (V BEl + P C£2 ) or
^be 2 + ^cei) [Fig- 16-2(b)]. The value of V CE for a transistor biased on in
saturation is typically about 0.2 V, and since forward for a silicon
transistor is about 0.7 V, the total volue of V F is around 0.9 V. The region of
the forward characteristics before switch on occurs is known as the forward
blocking region , and the region after switch on is termed the forward conduction
region. In the forward conduction region, the SCR is behaving as a forward-
biased rectifier.
To switch an SCR off, the forward current (If) must be reduced below
a level known as the holding current ( 1 H ) (Fig. 16-3). The holding current is
the minimum level of I F that will maintain the SCR conducting. If a gate
current (I G ) greater than zero is maintained while the SCR is on, lower
values of holding current {I H2 , 7// 3 , or I H4 ) are possible. Manufacturers
usually specify I H as I H0 , the holding current with the gate open circuited, or
I HX , the holding current with a specified bias resistance connected between
gate and cathode.
Two very important quantities that must be considered in selecting an
SCR for a particular application are the voltage and currents that the device
can survive without breaking down. The forward breakover voltage and
reverse breakdown voltage have already been discussed. The maximum
forward voltage that may be applied without causing the SCR to conduct is
termed the forward blocking voltage. This is designated V FOM or VfXM for an
open-circuited gate or a resistance biased gate, respectively. Similarly, the
reverse blocking voltage is called V R0M or F AVAf . The maximum allowable
forward current is variously specified as the average forward current [7/^ av )], the
rms forward current (If), or the peak one-cycle surge current [/ FA/(surge) ]. The first
two of these need no explanation; the third is a relatively large nonrepetitive
surge current that can be permitted to flow for one cycle.
Part of the available range of SCR’s is illustrated by the partial
specifications shown in Figs. 16-4 and 16-5. With an rms forward current of
1.6 A and a forward blocking voltage up to 200 V, the C6 range (Fig. 16-4)
is relatively low current, low voltage devices. The C6 package is the
standard TO-5 transistor-type can. Note that, although the anode-to-
cathode voltage can be as high as 300 V (nonrepetitive), the peak reverse
gate voltage is only 6 V.
The C35 range (Fig. 16-5) is capable of handling much higher powers
than the C6 SCR’s. RMS forward current for the C35 devices is 35 A, and
peak forward blocking voltages are as high as 800 V repetitive, or 960 V
nonrepetitive. The device is bolt mounted for heat dissipation. Even higher
voltage and higher current handling are possible with the C500X1, for
example. RMS continuous current is 1200 A and forward blocking voltage is
1800 V. To remove the heat dissipated, the device has a water jacket
requiring a flow of 1 gal/min («4 liters/min) for maximum dissipation.
1.6A RMS SCR UP TO 200V
349
SCR Control
Circuits
C6
Types
Peak Forward Blocking
Voltage, VrxM
T; = — 40°C to A- 1 25°C
Rue = 1000 Ohms
Working and Repetitive
Peak Reverse Voltage,
Vbom (wkg) and Vbom (rep)
Tj = — 40*C to -4-1 25*C
Non-Repetltive Peak
Revert* Voltage,
Vbom (non-rep)
<5 Millltec
T; = — 40°C to +125*C
C6U
25 volts
25 volts
40 volts
C6F
50 volts
50 volts
75 volts
C6A
100 volts
100 volts
150 volts
C6G
150 volts
150 volts
225 volts
C6B
200 volts
200 volts
300 volts
MAXIMUM ALLOWABLE RATINGS ANO CHARACTERISTICS
RMS Forward Current, On-state lr 1.6 Amperes
Average Forward Current, On-slate lruv> Depends on conduction angle (see chart)
Peak One Cycle Surge Forward Current (Non-repetitive), Iru (surge) . . . 10 Amperes
Peak Reverse Gate Voltage, Vorm 6 Volts
Operating Temperature T i , — 40 e C to -fl25*C
Forward and Reverse Blocking Current* Irx Ikt Typ. 40/Max. 100 /iAdc
Holding Current! . Ihx Typ. 1.0/Max. S.O mAdc
Turn off Timet ton Typ. 40 nsec
“
4
l
i •»
l
\
4-
\
1
!:
i M
n
V
\
r— .1 .■■■it
-H
l l l l
TYPICAL VARIATION OF GATE TRIGGER VOLTAGE
ANO CURRENT WITH GATE PULSE WIDTH
Figure 16-4. Condensed specification for C6 SCR. (Courtesy of General Electric Semi-
conductor Products Dept., Syracuse, N.Y.)
The simplest of SCR control circuits is shown in Fig. 16-6(a). If SCR,
were an ordinary rectifier, the ac supply voltage would be half-wave rectified
and only the positive half-cycles would appear across the load (R L ). The
same would be true if the SCR gate had a continuous bias voltage to keep it
16-5
SCR
Control
Circuits
16 - 5.1
Pulse
Control
35A RMS SCR UP TO 800V
350
The
Silicon
Controlled
Rectifier
Example 16-1
C35
Type
Peak Forward Slacking
Voltage, Vkom
T c = — 6S°C to + 125 # C
Repetitive Peak Reverse
Voltage, Vki>M(rep)*
Tc = — 65°C to -f-125°C
Non-Repetitive Peak
Reverse Voltage,
<5.0 Millisec
VRovi(non-rep)*
Tc = -6S°C to + 125*C
C35U
25 volts
25 volts
35 volts
C35F
50 volts
50 volts
75 volts
C35A
100 volts
100 volts
150 volts
C35G
150 volts
150 volts
225 volts
C35B
200 volts
200 volts
300 volts
C35H
250 volts
250 volts
350 volts
C35C
300 volts
300 volts
400 volts
C350
400 volts
400 volts
500 volts
C35E
500 volts
500 volts
600 volts
C35M
600 volts
600 volts
720 volts
C35S
700 volts
700 volts
840 volts
C35N
800 volts
BOO volts
960 volts
•Values apply for zero or negative gate voltage only. Maximum case to ambient thermal resistance
for which maximum Vvom and Vboh ratings apply equals ll°C/watt.
MAXIMUM ALLOWABLE RATINGS ANO CHARACTERISTICS
RMS Forward Current, On-state lr 35 Amperes
Average Forward Current, On-state Ire*?) Oepends on conduction angle (see chart)
Peak One Cycle Surge Forward Current (Non-repetitive), Iru (surge) 150 Amperes
Ht (for fusing) 75 Ampere* seconds (for times ^ 1.5 milliseconds)
Operating Temperature Tj — 65°C to + 125°C
Turn-off Timet toff Max. 75 *tsec
Figure 16-5. Condensed specification for C35 SCR. (Courtesy of General Electric Semi-
conductor Products Dept., Syracuse, N.Y.)
on when the anode-cathode voltage is positive. A trigger pulse applied to
the gate can switch the device on at any time during the positive half-cycle
of the input voltage. The resultant load waveform is a portion of the positive
half-cycle commencing at any instant at which the SCR is triggered [Fig.
1 6-6(b)]. Resistor R c holds the gate-cathode voltage at zero when no trigger
input is present.
The circuit of Fig. 16-6(a) has an ac input of 30 V peak, R L = 15
and R c = 1 kfi. (a) Select a suitable SCR from the specifications in Fig. 16-4.
(b) Specify the required trigger current and voltage, (c) Determine the
supply voltage at which the SCR will switch off.
solution (a)
For the SCR to remain off until triggered, the forward blocking voltage
( ^fxm) must be greater than the peak input voltage.
Vfxm> 30 V
351
SCR
Specifications
Trigger
pulse
Load
waveform
(b) Circuit waveforms
Figure 16-6. Simple SCR control circuit and waveforms.
For the C6U, V FXM = 25 V (see Fig. 16-4). Therefore, the C6U is not
suitable.
For the C6F, V FXM = bO V. The C6F looks like it might be a suitable
device. Now consider the peak load current (I P ).
At peak input, voltage across R L is
Vl = ‘ p -Vak
/p=-
V A
AK
When the SCR is on, a typical Kue is 1 V.
(16-1)
30 V-l V
15
= 1.93 A
For half-wave rectification, the rmi value of I L is
/r nu = 0.5X/ / ,
= 0.5X1.93 A
«0.97 A
The maximum allowable rms forward current for the C6 range is 1 .6
A; therefore, the C6F is a suitable device.
352
The
Silicon
Controlled
Rectifier
16-5.2
90° Phase
Control
solution (b)
From the gate trigger voltage and current chart in Fig. 16-4, for 20-jiis pulse,
V c = 0.5 V and 7 C «=:0.01 mA
Trigger input current,
V 0 5V
/ 7 .= / c + ~ =0.01 mA+ j^-=0.51 mA
Trigger voltage = F c = 0.5 V
Trigger current = / r = 0.51 mA
solution (c)
The SCR will switch off when I L falls below 1 H . For the C6F, a typical I H =
1 mA (see Fig. 16-4).
From Fig.l6-6(a),
e x ~
At/*-/*,
e, = \ V + (l mAX 15 fl) = 1.015 V
The SCR will switch off when e t falls below 1.015 V.
In the phase-control circuit shown in Fig. 16-7 the gate triggering
current is derived from the ac supply via resistance R { . If R l is adjusted to a
low resistance value the SCR will trigger almost immediately at the com-
mencement of the positive half-cycle of the input. If R { is set to a high
resistance, the SCR may not switch on until the peak of the positive
half-cycle. For resistances between these two values, the SCR will switch on
somewhere between the commencement and the peak of the positive half-
cycle, i.e., between 0° and 90°. If I c is not large enough to trigger the SCR
at 90°, then the device will not trigger on at all, because I c is greatest at the
peak of input and falls off as the voltage falls. The purpose of diode D x is to
protect the SCR gate from the negative voltage that would otherwise be
applied to it during the negative half-cycle of the input. R 2 keeps the SCR
biased off until triggered. Also, because I G is not precisely predictable, the
presence of R 2 makes the R } calculation more reliable.
From Fig. 16-7, it can be seen that at the instant of SCR switch on the
current I G + I 2 flows through R t , Z) p and R L . Therefore, at the instant of
Load waveform
/
/
- /
\\ /]
\
\ *
V
\
\
\
\ ,
L \ ' «
rA /
o ' /
90° ' / 90° \
\ / v /
Figure 16-7. SCR 90° phase-control circuit.
switch on g , ~(^ 2 + ^c)^i + ^oi + + (^ + ^g)^l
(/ 2 + 7 C )/?, = C| — V Di — V c — (/ 2 + Ig)Rl
R > = JJ^Jj[‘- V ‘>-( I 2 +I c)Ri.] ( I6 - 2 )
The circuit in Fig. 16-7 has an ac supply of 30 V peak and R L = 15 fl.
Determine the range of adjustment of /?, for the SCR to be triggered on
anywhere between 5° and 90°. The gate trigger current is 10 fx A and the
gate voltage is 0.5 V.
solution
let
/ 2 »/ c
/ 2 = 90 /i A
0.5 V
= 5.6 kfl
* 90 juA
/ 2 +/ c = 90^A+10/iA=100jLiA
At 5°, e t = 30 sin 5° = 30 X 0.0872 = 2.6 V.
From Eq. (16-2),
*,<«*.)- To^ f 2 ' 6 v_0 - 7 v_0 - 5 V_ ( 100 MX 15 «)]
1.4 V
100 jtiA
= 14 k!2
At 90°, ^, = peak voltage = 30 V.
/*!(«»)- To^X t 30 v “ a7 V— 0-5 v — (ioo jiAx 15 B)]
30 V- 1.2015 V
100 /i A
28.8 V
100 fiA
288 kS2
/?, should be adjustable from 14 kS2 to 288 kfi.
353
SCR Control
Circuits
Example 16-2
354
The
Silicon
Controlled
Rectifier
16 - 5.3
7 80° Phase
Control
16-6
The TRIAC
and DIAC
The circuit shown in Fig. 16-8 is identical to that in Fig. 16-7, except
that diode D 2 and capacitor C, have been added. During the negative
half -cycle of the input, C x is charged negatively as shown in the figure to the
peak of the input voltage. When the negative input peak is passed, D 2 is
reverse biased, because its anode (connected to Cj) is more negative than its
cathode. C, then commences to discharge via R v Depending upon the values
of C, and R lt the capacitor may be almost completely discharged at the
commencement of the input voltage positive half-cycle, or it may retain a
partially negative charge until almost 180° of positive half-cycle has passed.
While Cj remains negatively charged, D x is reverse biased and the gate
cannot go positive to trigger on the SCR. Thus, /?, and/or C x may be
adjusted to effect SCR triggering anywhere from 0° to 180° of input
waveform.
A simple modification of the 180° phase-control circuit is shown in
Fig. 16-9. The addition of rectifier Z ) 3 causes the negative half-cycle of the
input to appear across the load. Control is available only over the positive
half-cycle. Figure 16-10 shows two SCR’s and control circuits inverse paral-
lel connected. This affords separate control over positive and negative
half-cycles.
The various circuits described above are employed in such applications
as light dimmers, battery chargers, etc.
The construction, equivalent circuit and characteristics of a TRIAC
are shown in Fig. 16-11. The device amounts to two inverse parallel
connected SCR’s with a common gate terminal. Section n xt p 2 , n 3 , and p 3 in
Fig. 16-1 1(a) form one SCR, which can be represented by transistors and
Q _ 2 in Fig. 16-1 1(b). Similarly, p v n 2 > p 2 > and n 4 form another SCR, which
has the transistor equivalent circuit Q 3 and Qa- ? 2 t ^ ie lay er common to
both SCR’s, and it functions as a gate for both devices. Because of the
inverse parallel connection, the other terminals cannot be identified as
anode and cathode; instead they are designated A x and A 2 . When the gate is
made positive with respect to A x , and A 2 is also made positive with respect to
A j, transistors Q 3 and Q* switch on [Fig. 16-1 1(b)]. In this case A 2 is the
anode and A , is the cathode. When the gate and A x are made positive with
respect to A 2 , and Q 2 switch on. Now A x is the anode and A 2 the cathode.
SCR,
o 3
L
Control
/
circuit
*l\
Load waveform
Figure 16-9. Phase-control circuit with rectifier.
It is seen that the TRIAG can be made to conduct in either direction. No
matter what the bias polarity, the characteristics for the TRIAC are those of
a forward -biased SCR [Fig. 16- 11(c)].
A TRIAC control is shown in Fig. 16-12. Note that the circuit symbol
is composed of two inverse connected SCR symbols. During the positive
half-cycle of the input voltage, diode D x is forward biased, D 2 is reverse
biased, and the gate terminal is positive with respect to A x . During the
negative half-cycle, D x is reverse biased and D 2 is forward biased, so that the
gate becomes positive with respect XoA 2 . Adjustment of R x controls the point
at which conduction commences.
A DIAC is simply a TRIAC without a gate terminal. Switch on is
effected by raising the applied voltage to the breakover voltage. The DIAC
characteristics and symbol are shown in Fig. 16-13.
The four-layer diode , also called the Shockley diode after its inventor
William Shockley, is essentially a low-current SCR without a gate. To
switch the device on, the anodc-to-cathodc voltage must be increased to the
355
Other Four-
Layer
Devices
16-7
Other Four-
Layer
Devices
16 - 7.1
The Four-
Layer Diode
356
The
Silicon
Controlled
Rectifier
Figure 16-11. TRIAC construction, equivalent circuit, and characteristics.
Load waveform
Figure 16-12. TRIAC control circuit.
A.
TE
(a) Symbol
357
Other Four-
Layer
Devices
Figure 16-13. DIAC symbol and characteristics.
forward switching voltage. The circuit symbol and typical characteristics for the
four-layer diode are shown in Fig. 16-14. The forward switching voltage ( V s )
[Fig. 16-1 4(b)] is the equivalent of the SCR forward breakover voltage , and the
minimum current at which the device will switch on is the switching current
(/$). Holding current (I H ) and forward- conduction voltage ( V F ) are as defined for
the SCR.
One application for the four-layer diode is the relaxation oscillator
circuit shown in Fig. 16-15. In this circuit, capacitor C, is charged via
resistance R x from supply E. Charging continues until the capacitor voltage
reaches the diode switching voltage. The diode Z), then conducts heavily and
Anode
o
6
Cathode
(a) Symbol
Figure 16-14. Four-layer diode symbol and characteristics.
358
The
Silicon
Controlled
Rectifier
Example 16-3
Figure 16-15. Relaxation oscillator using four-layer diode.
rapidly discharges the capacitor. When the capacitor voltage falls so low
that the diode current becomes less than the holding current, the diode
switches off and the capacitor commences charging again. The output
voltage from the circuit is a sawtooth waveform as shown in the figure. For
the circuit to function correctly, R x must be small enough to allow the diode
switching current ( I s ) to flow when the four-layer diode switches on. If the
current through is less than I s , the diode will not switch on. Also, R x must
be large enough to prevent I H from flowing when the capacitor is dis-
charged. Otherwise, the four-layer diode will not switch off.
The four-layer diode employed in the circuit of Fig. 16-15 has V s =
10 V, V F =1 V, I s = 500 fiA, and ^=1.5 mA. If E = 30 V, calculate the
minimum and maximum values of R x for correct operation of the circuit.
solution
Summing the voltages around the circuit,
E=(IXR 1 )+V C
E- V c
R '—r
At the diode switching voltage,
E- V s
o — ±
T l(max) r
2 S
30 V-10 V
= 40 kfi
( 16 - 3 )
500X10- 6
At the diode forward conducting voltage, V c = V F and / (max) = I H .
E-V f
T l(min) r
30 V-l V
( 16 - 4 )
= 19.3 kfi
1.5 mA
zz
(b) Symbol
Figure 16-16. Characteristics and symbol for bilateral four-layer diode.
359
Other Four-
Layer
Devices
The four-layer diode discussed in Section 16-7.1 is sometimes referred
to as a unilateral four-layer diode , because it is a one-way device. A bilateral
four-layer diode, as the name suggests, is a two-way device. In construction, a
bilateral four-layer diode is simply two inverse parallel connected unilateral
four-layer diodes contained in one package. The bilateral device forward
and reverse characteristics are each identical to the forward characteristics of
the unilateral device [Fig. 16- 16(a)]. The circuit symbol used for the
bilateral four-layer diode as shown in Fig. 16- 16(b) is simply two inverse
parallel connected unilateral four-layer diode symbols.
16 - 7.2
Bilateral
Four-Layer
Diode
The silicon unilateral switch (SUS) and the silicon bilateral switch (SBS) are
essentially unilateral and bilateral four-layer diodes, respectively, with the
addition of gate terminals. Circuit symbols for the SUS and SBS are shown
in Fig. 16-17.
16 - 7.3
The SUS
and SBS
A
a 7
o-
G
C
^|(l
(a) Silicon unilateral switch (b) Silicon bilateral switch
Figure 16-17. Circuit symbols for SUS and SBS.
O A
360
The
Silicon
Controlled
Rectifier
Anode
gate
Cathode
gate
6C
(a) Equivalent circuit (b) Symbol
Figure 16-18. Silicon-controlled switch equivalent circuit and symbol.
16-7.4
The
Silicon-
Controlled
Switch
The silicon- controlled switch (SCS) is a low-current SCR with two gate
terminals. An anode gate is provided as well as the cathode gate. In the
two-transistor equivalent circuit shown in Fig. 16- 18(a), it is seen that a
negative pulse at the anode gate causes to switch on. Q., collector supplies
base current to Q 2 and both transistors switch on. Similarly, a positive pulse
at the cathode gate can switch the device on. Since only small currents are
involved, the SCS may be switched off by an appropriate polarity pulse at
one of the gates. At the cathode gate a negative pulse is required for switch
off, while at the anode gate a positive pulse is necessary. The SCS circuit
symbol is shown in Fig. 16- 18(b).
Glossary of
Important
Terms
SCR. Silicon controlled rectifier — a rectifier with a control element that
determines the anode-to-cathode voltage at which the device com-
mences to conduct.
Gate. Control element on SCR.
Thyristor. Collective name for SCR-type devices.
pnpn device. Another name for SCR-type devices.
Four-layer device. Another name for SCR-type devices.
Latching. The ability of the SCR to remain on after the triggering current
is removed.
Reverse blocking current, A small leakage current that flows when
the SCR is reverse biased.
Reverse breakdown voltage. Reverse voltage at which an SCR breaks
down.
Reverse blocking region. Region of SCR reverse characteristics before
breakdown occurs.
Forward blocking region. Region of SCR forward characteristics before
switch on occurs.
Forward leakage current, I FX . A small leakage current that flows before
switch on when the SCR is forward biased.
Forward breakover voltage, V F(BOy Forward voltage at which an SCR
switches on when the gate current is zero.
Forward conduction voltage, V F . SCR anode-to-cathode voltage when
conducting.
Gate current, I G . Current flowing into SCR gate terminal.
Holding current, I HQ . Minimum SCR anode current required to keep the
device conducting when gate is open circuited.
Holding current, 1^. Minimum SCR anode current required to keep the
device conducting when gate has a specified bias resistance.
Forward blocking voltage, Vfou- Maximum SCR forward voltage that
may be applied without causing the device to conduct when gate is
open circuited.
Forward blocking voltage, V FXM . Same as VfOM but with specified bias
resistance at gate.
Reverse blocking voltage, V ROM . Maximum SCR reverse voltage that may
be applied without causing breakdown when gate is open circuited.
Reverse blocking voltage, Vrxm‘ Same as V ROM but with specified bias
resistance at gate.
Average forward current, Ip^ v y Maximum permissible SCR average for-
ward current.
RMS forward current, 1^. Maximum permissible SCR rms forward cur-
rent.
Peak one-cycle surge current, I FM(tuniC y Nonrepetitive forward current
that can safely flow for one cycle.
TRIAC. Two inverse parallel connected SCR’s with a common gate,
contained in one package.
DIAC. Similar to a TRIAC but without a gate terminal.
Four-layer diode. Low-current SCR without gate.
Shockley diode. Same as four- layer diode.
Forward switching voltage, V s . Forward voltage at w’hich four-layer diode
commences conduction.
Switching current, I s . Minimum forward current for four-layer diode to
commence conduction.
Unilateral four-layer diode. Another name for the four-layer diode.
Bilateral four-layer diode. Two-w-ay device — two inverse parallel con-
nected unilateral four-layer diodes in one package.
SUS. Silicon unilateral switch — unilateral four-layer diode with a gate.
SBS. Silicon bilateral switch — bilateral four- layer diode with a gate.
SCS. Silicon-controlled switch — low current SCR with anode gate and
cathode gate.
361
Glossary of
Important
Terms
Review
Questions
Problems
16-1. Sketch the construction of a silicon-controlled rectifier. Also sketch
the two- transistor equivalent circuit and show how it is derived from
the SCR construction. Label all terminals and explain how the
device operates.
16-2. Sketch typical SCR forward and reverse characteristics. Identify all
regions of the characteristics and all important current and voltage
levels. Explain the shape of the characteristics in terms of the SCR
two-transistor equivalent circuit.
1 6-3. Sketch SCR phase control circuits for:
(a) 90° phase control.
(b) 180° phase control.
In each case show the load waveform and explain the circuit opera-
tion.
16-4. Show how an additional rectifier (not SCR) may be connected to
provide extra load current in the circuits of Question 16-3. Show the
effect on the load waveforms and briefly explain.
16-5. Draw an SCR control circuit using two SCR’s to provide phase
control for positive and negative half-cycles of the supply voltage.
16-6. Draw sketches to show the construction, equivalent circuit, and
characteristics of a TRIAC. Identify all important voltage and cur-
rent levels on the characteristics and explain the operation of the
device.
16-7. Sketch a TRIAC control circuit. Show the load waveform and
explain the operation of the circuit.
16-8. Sketch the characteristics and circuit symbols and briefly explain the
following:
(a) DIAC.
(b) Four-layer diode.
(c) Bilateral four-layer diode.
16-9. (a) Sketch the circuit of a relaxation oscillator using a four-layer
diode, and explain its operation.
(b) Sketch the circuit symbols and briefly explain (1) SUS, (2) SBS,
and (3) SCS.
16-1. A C6G SCR (data in Fig. 16-4) is employed to switch a 115 V ac
supply to a load. Determine the minimum load resistance that may
be supplied. If the SCR has a 2.2 kft bias resistor at the gate, estimate
the required gate trigger voltage and current. Also calculate the
instantaneous supply voltage at which the device switches off.
16-2. A load resistance of 33 ft is supplied from an ac source of 60 V peak.
Current to the load is to be switched on and off by an SCR triggered
by a 10 /is input pulse.
(a) Sketch the complete circuit.
362
16-3.
16-4.
16-5.
16-6.
16-7.
16 - 8 .
16-9.
16-10.
(b) Select a suitable SCR from the specifications in Figs. 16-4 and
16-5.
(c) If the gate bias resistance R c = 1 kft, specify the required trigger
voltage and current.
(d) Determine the supply voltage at which the SCR will switch off.
An SCR with a 1 15-V ac supply controls the current through a 150-ft
load resistor. A 90° phase-control circuit is employed to trigger the
SCR anywhere between 12° and 90°. The gate trigger current is 50
/xA. Calculate the value of the variable resistance, specify the diode
required, and select a suitable SCR from the C6 range.
The circuit in Fig. 16-7 has an ac supply of 30 V rms and R L = 20 ft.
Determine the range of adjustment of /?, for the SCR to be triggered
on anywhere between 7.5° and 90°. The gate trigger current is 500
/xA and the gate voltage is 0.6 V.
For Problem 16-4 the SCR holding current is 1 mA. Calculate the
instantaneous input voltage at which it will switch off.
The four-layer diode employed in the circuit of Fig. 16-15 has F 5 = 8
V, I s = 600 /xA, and I H — 1 mA. If E = 40 V, calculate the minimum
and maximum values of R { for correct operation of the circuit.
A four-layer diode is used in a relaxation oscillator which has a 25-V
supply, a l-/xF capacitor, and a 12-kft series resistor, (sec Fig. 16-15).
The capacitor is to charge up to 15 V, and then discharge to
approximately 1 V. Specify the four-layer diode in terms of forward
conduction voltage, forward switching voltage, switching current, and
holding current.
Design a 10° to 90° phase-control circuit to control a 1-kW heater.
The supply voltage is 120 V. Select a suitable SCR from the
specifications in Figs. 16-4 and 16-5.
A light dimmer uses a TRIAC with a control circuit by means of
which the device can be triggered on anywhere between the 5° and
90° points on the input waveform. The supply voltage is 220 V and
the total (lighting) load is 750 W. Assuming that the TRIAC gate
triggering current is 200 jtxA, design a suitable circuit and specify all
components.
A TRIAC circuit as in Fig. 16-12 has *, = 150 V, fl A = 100 ft, and
/?, = lOOkft to 2 kft. Determine the minimum points at which the
TRIAC can be triggered on. Specify all components.
363
Problems
CHAPTER
17
17-1
Introduction
17-2
Theory of
Operation
The
Unijunction
Transistor
The operation of a unijunction transistor (UJT) is quite different from
that of bipolar and field effect transistors although it is a three-terminal
device. The device input, called the emitter, has a resistance which rapidly
decreases when the input voltage reaches a certain level. This is termed a
negative resistance characteristic , and it is the characteristic which makes the
UJT useful in timing and oscillator circuits.
Basically, the unijunction transistor (also known as a double-base diode)
consists of a bar of lightly doped n-type silicon with a small piece of heavily
doped />-type material joined to one side. The concept is illustrated in Fig.
17-1 (a). The end terminals of the bar are designated base 1 (5,) and base 2
( B 2 ) as shown, and the />-type region is termed the emitter ( E ). Since the
silicon bar is lightly doped it has a high resistance, and it can be represented
as two resistors, r BX from B x to C and r B2 from B 2 to C as shown in Fig.
17- 1(b). The sum of r Bl and r B2 is designated R BB . The />-type emitter forms
364
Theory of
Operation
365
B ,
(a) Basic construction
(b) Equivalent circuit
Figure 17-1. Basic construction and equivalent circuit of unijunction transistor.
a /w-junction with the n-type silicon bar, and this is represented by a diode
in the equivalent circuit.
With a voltage V BXB2 applied as shown, the voltage at the junction of
where R BB = r Bl + r B2 •
V x is also the voltage at the cathode of the diode representing the
/^-junction. While the emitter terminal is open circuited, the only current
flowing is
If the emitter terminal is grounded, the />n-junction is reverse biased and
a small emitter reverse current ( l EO ) flows.
Now consider what happens when the emitter input voltage ( is
slowly increased from zero. As ^EB\ becomes equal to ^i> h:o will be reduced
to zero. With equal voltage levels on each side of the diode, no reverse
current or forward current will flow. With a further increase in V EBX the
/>n-junction becomes forward biased, and a forward emitter current I E begins
to flow from the emitter terminal into the n-type silicon bar. When this
r B \ and r B2 is
( 17 - 1 )
, _ K BIB2
l B2~ p
( 17 - 2 )
366
The
Unijunction
Transistor
Figure 17-2. UJT circuit symbol.
occurs, charge carriers are injected into the r Bl region of the bar. Since the
resistance of a semiconductor material is dependent upon doping, the
additional charge carriers cause the resistance of the r B1 region to rapidly
decrease. With decrease in resistance, the voltage drop across r Bl also
decreases, causing the /w-junction to be more heavily forward biased. This
results in a greater forward current, and consequently more charge carriers
are injected causing still further reduction in the resistance of the r Bl region.
The input voltage is also “pulled down,” and the input current (I E ) is
increased to a limit determined by the source resistance. The device remains
in this on condition until the input is open circuited or until I E is reduced to
a very low level.
The circuit symbol for a UJT is shown in Fig. 17-2. As always, the
arrowhead points in the conventional current direction for a forward- biased
junction. In this case it points from the p- type emitter to the n-type bar. The
voltage polarities and current directions for operation of the device are also
shown.
17-3 A plot of emitter voltage ( Veb\) versus emitter current ( I E ) gives the
UjT . emitter characteristics shown in Fig. 17-3.
Characteristics When I B2 — 0, (i.e., V B ib 2 ~Q)> and a small increase in V E
forward biases the emitter junction. The resultant plot of V E and I E is simply
the characteristic of a forward-biased diode with some series resistance.
When V BlB2 is appriximately 20 V and K £ = 0, the emitter junction is
reverse biased and the emitter reverse current ( I E0 ) flows as shown at point 1
on the characteristics. Increasing ^eb i reduces the emitter junction reverse
bias. When V E = V l [see Fig. 1 7-1 (b)], there is no reverse or forward bias and
I E — 0. This gives point 2 on the characteristic. Increasing ^EB 1 beyond this
point begins to forward bias the emitter junction. At the peak point where
^EB i = the junction is just forward biased, and a very small forward
emitter current is flowing. This is termed the peak current I P . Up until this
point, the UJT is said to be operating in the cutoff region. When I E increases
beyond I P the device enters the negative resistance region , in which the resis-
tance of r B { falls rapidly and V E falls to the valley voltage V v . V 0 is determined
by the forward-biased emitter diode voltage V D and by the saturation resistance r s
of r BV At this point 1 E equals the valley current (If). A further increase of I E
367
UJT
Parameters
and
Specification
causes the device to enter the saturation region, where V E is equal to the sum ol
V D and (I E X r s ).
When V BB is reduced below 20 V, V x will also be reduced and the UJT
will switch on at a lower value of V E . Thus, using various levels of V BB , a
family of ^EB ,/ I E characteristics for a given UJT can be plotted as shown in
Fig. 17-3.
17-4
UJT
Parameters
and
Specification
The interbase resistance (R BB ) is the sum of r BX and r B2 when the emitter
current is zero. Consider Fig. 17-4 showing a portion of the manufacturer’s
data sheet for 2N4948 and 2N4949 UJT’s. R BB is specified as 7 kS2 typical,
4 kfl minimum, and 12 kfi maximum. Rbb is very sensitive to temperature
variations, and an interbase resistance temperature coefficient {<xR BB ) is usually
specified on data sheets. For the 2N4948, aR BB can be as large as 0.9%/ °C.
17 - 4.1
Interbase
Resistance ,
^BB
2n4948 (SILICON)
2n4949
Silicon annular unijunction transistors designed for
military and industrial use in pulse, timing, triggering,
sensing, and oscillator circuits. The annular process
provides low leakage current, fast switching and low
peak-point currents as well as outstanding reliability
and uniformity.
CASE 22A
(TO- 18 Modified)
(Lead 3 connected to case)
MAXIMUM RATINGS (Ta = 25*C unless otherwise noted)
Rating
Symbol
Value
Unit
RMS Power Dissipation*
P D
360*
mW
RMS Emitter Current
>e
50
rnA
Peak Pulse Emitter Current**
i e
1.0**
Amp
Emitter Reverse Voltage
v
V B2E
30
Volts
Storage Temperature Range
T
stg
-65 to +200
°C
* Derate 2.4 mW/°C increase in ambient temperature.
ELECTRICAL CHARACTERISTICS <T. = 25 *C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Intrinsic Standoff Ratio
< V o,n, 1 I® V) Note 1 2N4948
BZB1 2N4949
n
0. 55
0.74
:
0.62
0.86
Interbase Resistance
< V B2B1 3 0 v - l E z °> 2N4948, 2N4949
R B8
4.0
7.0
12.0
k ohms
Interbase Resistance Temperature Coefficient
(V B2B) ’ 3 0 V ' ‘e ; °< t a ■ 65 ” C to ‘‘00*0
“ R B8
0. 1
0.9
V*c
Emitter Saturation Voltage
(V B2B1 = 10 v ' > E 50 mA > 2
V EBl(sat)
2.5
3.0
Volts
Modulated Interbase Current
,V B2B. 10V ' ‘ E =50 mA)
'B2(mod)
12
15
-
mA
Emitter Reverse Current
(V B2E 30 V W 0 *
<V B2E = 30V - «B1 =0 T A -125-C)
‘eB20
5.0
10
1.0
nA
M A
Peak Point Emitter Current
<V B2B1 - “ V)
2N4949
>P
0.6
0.6
2.0
1.0
HA
Valley Point Current
<V 82B1 r 20 V ' R 82 1 100 0hms) Not * 2 2N4948, 2N4949
'v
2.0
4.0
mA
Figure 17-4. Portion of UJT data sheet. (Courtesy of Motorola, Inc.)
368
This is a positive temperature coefficient; i.e., R BB increases with tempera-
ture increase. The value of R BB together with the maximum power dissipa-
tion P D determines the maximum value of V BiB2 that may be used. With
I E = 0, maximum power dissipated in the UJT is
Pp =
( ^BIB2)
Rrr
maximum V BlB2
^ Rrb x p d
(17-3)
369
UJT
Parameters
and
Specification
Determine the maximum value of V BXB2 that should be used with a Example 17-1
2N4948 UJT (a) at an ambient temperature of 25°C; (b) for operation up to
100°C.
solution (a)
From Fig. 17-4, at 25°G,
/ 5 d = 360 mW, Rrr — 4 kfi(min), 12 kfi(max)
To give the lowest possible value of V BXB2{mMx) use R BB(miny
V4kBx360mW «38V
This is larger than the maximum emitter reverse voltage ( V B2 £) which is 30
V. Therefore, at 25°G, V BXB2 should not exceed 30 V.
solution (b)
at 100° C
First note, from Fig. 17-4, that P D must be derated linearly at 2.4 mW/°C.
The temperature increase from 25°C s =(100 — 25)°G = 75°C.
at 75° C
P D = 360 mW - (2.4 X 75) mW = 360-1 80 mW = 1 80 mW
The minimum increase in R BB is 0.1%/°C, from aR BB . For a tempera-
ture increase of 75°C this is only a 7.5% increase in R BB , so for calculation of
V B \ B 2 ( m *xy ignore the R BB increase.
From Eq. (17-3),
\ATfiXl80mW * 26.8 V
17-4.2
Intrinsic
Stand-off
Ratio tj
The intnnsic stand-off ratio , which is represented by the symbol tj (Greek
letter eta), simply defines the ratio of r Bl to R BB . Together with V BlB2 and
the emitter junction voltage drop ( P^), tj also determines the peak voltage
V p for the UJT.
From Eq. (17-1),
, — V^BlB2
r B 1^ ' B 2
and the peak voltage is V D + V v
V p = V d + t)V bi b2 (17-4)
V D is the forward voltage drop of a silicon diode, typically 0.7 V.
Example 17-2
Determine the minimum and maximum emitter voltages at which a
2N4948 UJT will trigger on (or fire) when V BlB2 = 30 V.
solution
From Fig. 17-4,
tj = 0.55 min and 0.82 max
From Eq. (17-4)
V H min) = 0.7 V 4- (0.55 X 30) = 1 7.2 V
and
»WO=0.7 + (0.82 X 30) = 25.3V
Therefore, the device will fire at some emitter voltage between 17.2
and 25.3 V.
17-4.3
Emitter
Saturation
Voltage,
^EBI(sal)
V EB i(sat) IS t ^ ie emitter input voltage when the UJT is in its saturation
region. Therefore, it is the minimum level to which V EBl falls when the UJT
is triggered on. Since is affected by I E and V B2B1 , it must be
specified at given levels of I E and V B2Bl . From Fig. 17-4, for V B2Bi = \0 V
and I E — 50 mA, V EBl (sat) for a 2N4948 is 2.5 V typical and 3.0 V maximum.
17-4.4
Peak Point
Emitter
Current, l P
I p was explained in Section 1 7-3. It is important as a lower limit to the
emitter current. If the source resistance of the input voltage is so high that I E
370
is not greater than I p , then the UJT will simply not trigger on (see Examph
17-4).
This quantity was also explained in Section 17-3. It is important in
some circuits as an upper limit to the emitter current. If the source resistance
of the input voltage is so low that I E is equal to or greater than l v > then the
device will remain on when triggered (see Example 1 7-4).
This is the value of current flowing into B 2 after the device is first fired.
The current is said to be modulated by the UJT being fired.
The relaxation oscillator shown in Fig. 17-5 consists of a UJT and a
capacitor C,, which is charged via resistance R E . When the capacitor voltage
reaches V P , the UJT fires and rapidly discharges C x to Veb\(%*iy The device
then cuts off and the capacitor commences charging again. The cycle is
repeated continuously, generating a sawtooth waveform across C,. The time
(/) for the capacitor to charge from to V p may be calculated, and
the frequency of the sawtooth determined approximately as \/t. The
discharge time ( t D ) is difficult to calculate because the UJT is in its negative
resistance region and its resistance is changing. However, t D is normally very
much less than t, and can be neglected for approximation.
The relaxation oscillator in Fig. 17-5 uses a 2N4948 UJT. Calculate
the typical frequency of oscillation.
solution
The general equation for the charging time of a capacitor charged via a
Sawtooth
/W1
Figure 17-5.
17-43
Valley
Point
Current , ^
17-4.6
Modulated
In ter base
Current ,
^B2(mod)
17-5
UJT
Relaxation
Oscillator
Example 17-3
371
372
The
Unijunction
Transistor
series resistor is
j? g
( = 2.3Ctflog — i (17-5)
t-e c
where C = capacitance in farads
R = resistance in ohms
E = supply voltage
e c — capacitor voltage at time t
E 0 = initial voltage on capacitor
Since the UJT is to fire at time t
*.~v,
= Vd + vV b 1 B 2 [from Eq. (17-4)]
From the data sheet (Fig. 17-4) a typical value of intrinsic stand-off
ratio is 7) = 0.7. Also V D = 0.1 V.
^ = 0.7 V + (0.7X 15 V)
= 0.7 V+ 10.5 V= 11.2 V
When the UJT fires, the capacitor is discharged to V EBX (sat) . This is the
capacitor voltage E 0 at the start of each charging cycle. For the 2N4948,
*£/n(sat) = 2.5 V typically.
E= 2.5 V
From Eq. (17-5),
f = 2.3 X 0.1 /aF X 1 0 kS7 X log
= 2. 3X0.1 X 10 _6 X 10X 10 3 Xlogy^ = 1.16 ms
The frequency is
/= — = — 7T ms « 860 Hz
J t 1.16
The inclusion of resistors R l and R 2 in series with B x and B 2 provides
output spike waveforms from the oscillator as shown in Fig. 17-6. When the
UJT fires, the surge of current through B x causes a voltage drop across R x
and produces the positive-going spikes. Similarly, at the UJT firing time, the
UJT
Relaxation
Oscillator
Figure 17-6. Variable frequency UJT relaxation oscillator.
fall of V EBX causes I B2 to increase rapidly and generates the negative-going
pulse across R 2 . In practice, R x and R 2 should be much smaller than R-bb to
avoid altering the UJT firing voltage. Typically, /?, is selected less than 47
ft, and R 2 is usually 200 to 300 ft. A wide range of oscillation frequencies can
be achieved by making R E adjustable and including a switch to select
different values of capacitance.
For correct operation of the UJT there is an upper and lower limit to
the signal source resistance. For the UJT to fire in the circuit of Fig. 17-6, a
minimum current level equal to I P must flow through R E when the emitter
voltage is V F .
The upper limit on R E is
- (17-6)
l P
For the relaxation oscillator, R E must be large enough to prevent the
valley current from flowing continuously; otherwise, the UJT will not switch
off again.
The lower limit on R E is
(17-7)
l v
The circuit of Fig. 17-6 uses a 2N4948 UJT. If V RB is 15 V, determine
the maximum and minimum values for R E .
Example 17-4
374
The
Unijunction
Transistor
17-6
UJT Control
of SCR
solution
From Eq. (17-4),
Kp~ +
The largest value of V p will give the smallest /? £(max) . Therefore, from
the data sheet (Fig. 17-4), use 17 = 0.82.
F)> = 0.7 + (0.82 X 15)= 13 V
From Eq. (17-6),
For smallest R E(mzx) ,
ax) = ^ ^A.
use maximum I P . From the data sheet (Fig. 17-4),
„ 15 V— 13 V
%max) 2
From Eq. (17-7)
n £(min) “
V BB K ££L(«at)
Iy
For the largest value of 7? £(min) , use minimum V E b\(sm) an ^ minimum
I v . Deriving these values from the data sheet,
„ 15 V — 2.5 V
« E (nnn) g mA
= 6.25 k 12
In practice, R E should be selected somewhere between the upper and lower
limits.
Unijunction transistors are frequently employed for control of SCR’s.
In the typical circuit, shown in Fig. 17-7(a), the SCR is triggered on by the
voltage drop across R x when the UJT fires. Diode D x allows the positive
half -cycle of the supply to charge C x via R E . D x also isolates the UJT circuit
from the negative half-cycles of the input. By adjusting *£. the charging rate
of Cj , and therefore the UJT firing time, can be selected. The waveforms in
Fig. 17-7(b) show that almost 180° of control of SCR triggering is possible.
UJT firing
point
Figure 17-7. Circuit and waveforms for UJT control of SCR.
The programmable unijunction transistor (PUT) is not a unijunction transis-
tor at all, but an SCR-type device used in a particular way to simulate a
UJT. For the simulated UJT the interbase resistance ( R BB ) and the intrinsic
stand-off ratio ( 77 ) may be programmed to any desired values by selecting
two resistors. This means that the device firing voltage (the peak voltage V p )
can also be programmed.
Consider Fig. 17-8. The pnpn device shown in Fig. l7-8(a) has its gate
connected to the junction of resistors /?, and /? 2 . The four-layer construction
in Fig. l7-8(b) shows that the anode-gate junction is forward biased when
the anode becomes positive with respect to V c . When this occurs the device
is triggered on. The anode-to-cathode voltage then drops to a low level, and
375
Programmable
Unijunction
Transistor
17-7
Programmable
Unijunction
Transistor
376
The
Unijunction
Transistor
(a) Programmable UJT circuit
(b) Four-layer construction
of programmable UJT
(c) Characteristic of
programmable UJT
Figure 17-8. Circuit, four-layer construction, and characteristic of programmable UJT.
the device conducts heavily until the input voltage becomes too low to
sustain conduction. It is seen that this action simulates the performance of a
UJT. The anode of the device acts as the UJT emitter, and and R 2
operate as r Bi and r B2 , respectively. R BB , 77, and V p are programmed by the
selection of /?, and R 2 . The typical characteristic of a programmable UJT is
shown in Fig. 17-8(c).
Example 17-5
A programmable UJT has a forward voltage ( V F ) of 1 V when on, and
requires a gate trigger current (7 C ) of 0.1 mA. tj is to be programmed to 0.7.
Using a 20 V supply, determine R 1 and R 2 . Also calculate Vp* V v> and R BB .
solution
R x
y Rl = tjX F flfl = 0.7X20 V=14 V
If 7j is too small, V G may be significantly altered when I c flows. To
ensure a stable V G level, make /, > 10/ c .
/, = 10X0.1 mA = 1 mA
R 14V
/ '1mA
= 14 k«
20V-HV =6kn
1 mA
R BB = R i + R 2 = 2 °
Vp~ ^V^bs* where V D (anode-to-gate forward voltage drop) is about
0.7 V.
k)» = 0.7 + (0.7X20) = 14.7 V
V v = anode-to-cathode forward voltage drop ^ V F = 1 V
377
Glossary of
Important
Terms
Unijunction transistor (UJT). Three-terminal device having one /wi-junc- Glossary of
tion and an n-type resistive region. Important
Terms
Double-base diode. Another name for a UJT.
Base 1, By UJT terminal to which the negative terminal of supply is
connected.
Base 2, B 2 . UJT terminal to which the positive terminal of supply is
connected.
Emitter, E. UJT input terminal.
r BX . Resistance of «-type region between junction cathode and B x of UJT.
r B2 . Resistance of n-type region between junction cathode and B 2 of UJT.
Interbase resistance, R BB . Resistance of UJT measured between B x and B 2
— sum of r Bl and r B2 .
UJT input voltage applied between B x and E.
Peak point emitter current, I P . UJT emitter current at peak point on
characteristic — emitter current at instant of firing.
Valley point current, Iy. UJT emitter current at valley point on character-
istic.
Peak voltage, V p . UJT emitter-to-fi, voltage at instant of firing.
Valley voltage, V v . UJT emittcr-to-Z?, voltage at valley point on char-
acteristic.
Saturation resistance, r s . Resistance of r Bl after UJT has fired.
378
The
Unijunction
Transistor
Cutoff region. Region of UJT characteristics before junction becomes
forward biased.
Negative resistance region. Region of UJT characteristic between peak
point and valley point.
Saturation region. Region of UJT characteristic after device has fired
— beyond valley point.
Intrinsic stand-off ratio. Ratio r Bl / R BB — determines emitter-to-Z?! voltage
at which UJT fires.
Emitter saturation voltage, Emitter-to-Z?! voltage of UJT in
saturation region.
Modulated interbase current, /^(mod)* Current flowing into B 2 after UJT
has fired.
Programmable UJT, PUT. SCR-type device which simulates a UJT.
Review
Questions
17-1. Draw sketches to show the basic construction and equivalent circuit
of a unijunction transistor. Briefly explain the operation of the UJT.
17-2. Sketch typical UJT emitter characteristics for I B2 = 0, E BlB2 =20 V,
and E BlB2 = b V. Identify each region and all important points on the
characteristics, and explain their shape.
17-3. Sketch the circuit of a UJT relaxation oscillator with provision for
frequency adjustment and spike waveform. Show all waveforms and
explain the operation of the circuit.
17-4. Sketch a UJT circuit for control of an SCR. Also sketch input,
capacitor, and load waveforms, and briefly explain how the circuit
operates.
17-5. Using illustrations explain the operation of a programmable unijunc-
tion transistor. Sketch a typical characteristic for the device and
explain how the intrinsic stand-off ratio may be programmed.
Problems
17-1. Determine the maximum value of power dissipation for a 2N4948
UJT operating at an ambient termperature of 125°C. Also determine
the maximum value of V BlB2 that may be used at 125°C. The
condensed data sheet for the 2N4948 is shown in Fig. 17-4.
17-2. Calculate the minimum and maximum values of V EBI at which a
2N4948 UJT will trigger on when V BXB2 = 20 V.
17-3. A relaxation oscillator uses a 2N4948 UJT and has K 5j9 = 25 V. The
capacitor employed has a value of 0.5 /xF and the charging resistance
is 33 kft. Calculate the typical oscillation frequency.
17-4. For the circuit of Problem 17-3, calculate the maximum and mini-
mum values of capacitor charging resistance which will sustain
oscillations.
17-5. A programmable UJT operating from a 25- V supply has V F = 1.5 V
and / c = 0.05 mA. Determine the values of /?, and R 2 to program tj to
0.75. Also calculate V F , Vy, and R bb .
17-6. A UJT relaxation oscillator to have a frequency of 3 kHz is to
operate from a 20- V supply. A 3-juF capacitor is employed, and the
maximum and minimum output voltages are to be 7.5 and 1 V,
respectively. Determine a suitable value of series resistance, and
specify the UJT in terms of intrinsic stand-off ratio and valley
voltage.
17-7. A UJT relaxation oscillator has a 30-V dc supply, a 5-juF capacitor,
and a 12-kft charging resistor. If 77 ranges from 0.65 to 0.73 and
V v = 1 .5 V, determine the maximum and minimum values of oscillat-
ing frequency and peak output voltage.
17-8. The UJT in Problem 17-3 is to be replaced with a PUT. Determine
suitable values for /?, and /? 2 , and specify the PUT.
17-9. A programmable UJT has a forward voltage of F^-^0.9 V when on.
The gate trigger current is / c = 200 jttA. The device is to be pro-
grammed to switch on at V c =\5 V when operating from a 24- V
supply. Determine suitable values for /?, and R 2> and calculate V py
K>> and R bb .
379
Problems
CHAPTER
18
18-1
Introduction
Optoelectronic
Devices
Optoelectronic devices are light-operated devices (photoelectric),
light-emitting devices, or devices which modify light.
Photoelectric devices can be categorized as photoemissive , photoconductive ,
or photovoltaic. In photoemissive devices, radiation falling upon a cathode
causes electrons to be emitted from the cathode surface. In photoconductive
devices, the resistance of a material is changed when it is illuminated.
Photovoltaic cells generate an output voltage proportional to radiation
intensity.
Any light source emits energy only over a certain range of frequencies
or wavelengths. A graph of energy output plotted versus either frequency or
wavelength is termed the emission spectrum for the source. An electronic device
which is affected by light is sensitive only to a certain range of radiation
frequencies. A graph of device current, voltage, or resistance plotted versus
radiation frequency is known as its spectral response. For a given photosensitive
material there is a minimum radiation frequency (or maximum wavelength)
that can produce a photoelectric affect; this is known as the threshold frequency
or threshold wavelength.
380
The total light energy output, or luminous flux , from a source can be 18-2
measured in milliwatts (mW) or in lumens (!m). Light
Units
1 lm= 1.496 mVV
Light intensity is the amount of light that falls on a unit area. Light
intensity is expressed in milliwatts per square centimeter (mW/cm 2 ), in lumens per
square meter (lm/m 2 ), or in the older unit lumens per square foot (lm/ft 2 ) which
is also known as a foot candle (fc).
1 fc = 10.764 lm/m 2
The light intensity of sunlight on the earth at noon on a clear day is
approximately 10,000 fc, or 107,640 lm/m 2 . Using 1 lm= 1.496 mVV,
sunlight intensity becomes 161 W/m 2 .
Consider a point source which emits light evenly in all directions. To
determine the light intensity at a given distance from the source, it is
necessary to consider the surface area of a sphere surrounding the source.
At a distance of 1 m from the source the luminous flux is spread over a
total surface area of a sphere with a radius of 1 m.
Surface area of sphere = 47rr 2
Light intensity
luminous flux
4 AT 2
(18-1)
Calculate the light intensity at a distance of 3 m from a lamp which Example 18-1
emits 25 W of light energy. Also determine the total luminous flux which
strikes an area of 0.25 cm 2 at 3 m from the lamp.
solution
From Eq. (18-1),
T . , . 25 W
Light intensity = -
4^(3 m) 2
= 221 mW/m 2 = 22lX10' 4 mYV/cm 2
Total flux = (flux per unit area) X (area)
= (light intensity) X (area)
= (221 X 10“ 4 m\V/cm 2 ) X (0.25 cm 2 )
^5.5 mW
381
382
Optoelectronic
Devices
Light energy is an electromagnetic radiation; i.e., it is in the form of
electromagnetic waves. Therefore, it can be defined in terms of frequency or
wavelength as well as intensity. Wavelength, frequency, and velocity are
related by the equation
c=f\
(18-2)
where c = velocity
= 3 X 10 8 m/s for electromagnetic waves
/ = frequency in Hz
A = wavelength in meters
Visible light ranges approximately from violet at 380 nm (380 nano-
meters or 380X10 -9 m) to red at 720 nm. From Eq.(18-2), the frequency
extremes are
and
c 3X10 8
* \ ~ r,™ w ,^-9
/ =
380X10
3X10 8
=:8X10 14 Hz
720X10 -9
-4X10 14 Hz
18-3
Photo-
multiplier
Tube
Although many solid-state photoelectric devices are available today,
the photomultiplier tube is still widely applied, mainly because it is an
extremely sensitive device. A photomultiplier tube consists of an evacuated glass
envelope containing a photocathode , an anode y and several additional electrodes
termed dynodes. Figure 18-1 illustrates the principle of the photomultiplier.
Radiation striking the photocathode imparts energy to electrons within the
surface material of the cathode. When the radiation frequency exceeds the
threshold frequency of the cathode material, electrons are emitted from
the surface. The emitted electrons (negative charge carriers) are accelerated
toward dynode 1 by the positive potential on that dynode. The dynodes have
surfaces which facilitate secondary emission. Thus, if the electrons strike the
surface of dynode 1 with sufficient energy, secondary electrons are knocked out
of the surface and are accelerated toward the more positive dynode 2. Each
electron which strikes dynode 2 produces more secondary electrons, which
are then accelerated to dynode 3, and so on.
The electrons emitted from the dynode surface are termed secondary
electrons to distinguish them from the primary or incident electrons. The energy of
the incident electrons depends upon the voltage applied to accelerate them,
i.e., the dynode voltage. Since there are many more secondary electrons than
primary electrons, the original photoemission current is amplified, or, in
other words, the number of electrons is multiplied.
Emitted
electron
Secondary
electrons
383
Photo-
multiplier
Tube
After moving from dynode 1 to dynode 2 and successive dynodes, the
electrons are finally collected at the anode. In this way photoemission
currents of the order of microamperes are converted to more useful milli-
ampere levels. Current amplifications of up to 10 6 are possible, depending
upon the number of dynodes employed.
The characteristics of a typical photomultiplier tube are shown in Fig.
18-2. High voltages are required to operate the device. The anode voltages
used with various photomultiplier tubes range from 500 to 5000 V. The dark
current , which flows when the cathode is not illuminated, results from thermal
emission and the influence of the high-voltage electrodes. For incident
illumination of a given wavelength the number of emitted electrons is
directly proportional to the illumination intensity. Thus, for a particular
Anode voltage *-
Figure 18-2. Typical characteristics of a photomultiplier tube
384
Optoelectronic
Devices
18-4
The
Photo-
conductive
Cell
9 X 200 kn
Dynodes
Cathode'" Anode
(a) Photomultiplier
circuit symbol
Figure 18-3.
Photomultiplier circuit symbol and typical circuit.
illumination intensity the anode current of the photomultiplier tube should
tend to remain constant as the anode voltage is increased. However, the dark
current always adds to the anode current produced by illumination, and the
secondary emission improves with increase in applied voltage; consequently,
the anode current tends to increase slightly with increase in anode voltage.
Since the illumination levels indicated on the characteristics are
measured in microlumens , it is seen that the photomultiplier tube is very
sensitive indeed. In fact, the device is so sensitive that destructively large
currents could flow if it is exposed to ordinary daylight levels when voltage is
applied to its electrodes. Various spectral responses are available in photo-
multiplier tubes, ranging approximately from 150 to 600 nm, or from 400 to
1000 nm.
The symbol for a photomultiplier tube and a typical circuit arrange-
ment are shown in Fig. 18-3. The cathode is provided with a high negative
voltage, and the dynodes are biased via a potential divider arrangement
between ground and the negative supply. The anode is connected via a high
value of load resistance to a level more positive than ground. Although the
device requires high operating voltages, the circuit arrangement enables the
output voltage to be relatively close to ground.
Light striking the surface of a material can provide sufficient energy to
cause electrons within the material to break away from their atoms. Thus,
free electrons and holes (i.e., charge carriers) are created within the
material, and consequently its resistance is reduced. The circuit symbol and
construction of a typical photoconductive cell are shown in Fig. 18-4.
Light-sensitive material is arranged in the form of a long strip, zigzagged
across a disc-shaped base with protective sides. For added protection, a glass
or plastic cover may be included. The two ends of the strip are brought out
to connecting pins below the base.
From the illumination characteristic shown in Fig. 18-5, it is seen that
when not illuminated the cell resistance may be greater than 1 00 k£2. This is
known as the dark resistance of the cell. When illuminated, the cell resistance
Light sensitive
Figure 18-4. Construction and circuit symbol for photoconductive cell.
may fall to a few hundred ohms. Note that the scales on the illumination
characteristic are logarithmic. The cell sensitivity may be expressed in terms
of the cell current for a given voltage and given level of illumination.
The two materials normally employed in photoconductive cells are
cadmium sulfide (CdS) and cadmium selenide (CdSe). Both materials respond
rather slowly to changes in light intensity. For cadmium selenide the
response time is around 10 ms, while cadmium sulfide may take as long as
100 ms. Another important difference between the two materials is their
temperature sensitivity. There is a large change in the resistance of a
cadmium selenide cell with changes in ambient temperature, but the
cadmium sulfide resistance remains relatively stable. As with all other
devices, care must be taken to ensure that the power dissipation is not
Figure 18-5. Illumination characteristic for photoconductive cell.
386
Optoelectronic
Devices
Example 18-2
excessive. The spectral response of a cadmium sulfide cell is similar to that of
the human eye; i.e., it responds to visible light. For a cadmium selenide cell,
the spectral response is at the longer wavelength end of the visible spectrum
and extends into the infrared region.
Two photoconductive cell applications are given in Examples 18-2 and
18-3. Other applications are shown in Figs. 18-8 and 18-9.
A relay is to be controlled by a photoconductive cell with the char-
acteristics shown in Fig. 18-5. The relay is to be supplied with 10 mA from a
30- V supply when the cell is illuminated with about 400 lm/m 2 , and is
required to be de-energized when the cell is dark. Sketch a suitable circuit
and calculate the required series resistance and the level of the dark current.
solution
The circuit is shown in Fig. 18-6. A series resistor Ry is included to limit the
current.
The current is
7 _ 30 V
R { + (cell resistance)
30
R { = — — (cell resistance)
From Fig. 18-5, the cell resistance at 400 lm/m 2 sl M2:
30 V
= --1 M2 = 2M2
1 10 mA
and cell dark resistances 100 M2 (from Fig. 18-5).
Dark currents
30 V
2M2+100M2
s0.3 mA
Example 18-3
An npn transistor is to be biased on when a photoconductive cell is
dark, and off when it is illuminated. The supply voltage is ±6 V, and the
transistor base current is to be 200 /iA when on. If the photoconductive cell
has the characteristics shown in Fig. 18-5, design a suitable circuit.
solution
The circuit is as shown in Fig. 18-7. When dark the cell resistance is high,
and the transistor base is biased above its grounded emitter. When
illuminated, the base voltage is below ground level.
Figure 10-7. Circuit to switch transistor off when photoconductive cell is illuminated.
From Fig. 18-5, the cell dark resistances 1 00 k!2.
When the transistor is on,
Cell voltage — 6 V + ^ = 6.7 V (for a silicon transistor)
Cell current « -j^ = 67,. A
The current through is
Cell current + I B = 67 fiA + 200 /t A = 267 fiA
The voltage across /?, = 6 V— V BE — 5.3 V.
5.3 V
* 1 -
267 pA
20 k£2
When the transistor is off, the transistor base is at or below zero volts.
^«6V
387
388
Optoelectronic
Devices
Figure 18-8. Circuit to switch transistor on when cell is illuminated.
'*• 20 kfl ~ 300
Since cell current — I R , and cell voltage«=;6 V.
6 V
Cell resistance = — — — - = 20 kS2
300 fiA
50 pA
meter
Figure 18-9. Light meter using photoconductive cell.
Therefore, Q x will be off when the cell resistance is 20 kfi or less, i.e.,
when the illumination level is above approximately 7 lm/m 2 (see character-
istics).
18-5
The
Photodiode
When a pn -junction is reverse biased, a reverse saturation current I s
flows due to thermally generated holes and electrons being swept across the
junction as minority carriers. Increasing the junction temperature will
generate more hole-electron pairs, and so the minority carrier (reverse)
current will be increased. The same effect occurs if the junction is
illuminated. Hole-electron pairs are generated by the incident light energy,
and minority charge carriers are swept across the junction. Increasing the
level of illumination increases the number of charge carriers generated and
increases the level of reverse current flowing. Increasing the reverse voltage
does not increase the reverse current significantly, because all available
^ Reverse
voltage (E R )
— 3 V — 2 V -IV
Forward ^
voltage
0 +0.5V
389
The
Photodiode
Figure 18-10. Illumination characteristics of photodiode.
charge carriers are already being swept across the junction. Even when the
applied external bias is reduced to zero, the available minority carriers are
swept across the junction by the junction barrier potential. To reduce the
current to zero, it is necessary to forward bias the junction by an amount
equal to the barrier potential.
Consider the typical illumination characteristics of a photodiode as
shown in Fig. 18-10.
When dark, I R ^ 20 /iA at E R = 2 V.
E r 2 V
Dark resistance = — — « — = 100 k!2
I R 20 M
When illuminated with 25,000 lm/m 2 ,
/*« 375 /iA
2 V
and Illuminated resistances — — — — =*5.3 kft
375 n A
The resistance has changed by a factor of approximately 20, and it is
seen that the photodiode can be employed as a photoconductive dev\ce.
When the reverse-bias voltage across a photodiode is removed, minor-
ity charge carriers will continue to be swept across the junction while the
diode is illuminated. This has the effect of increasing the number of holes in
the />-side and the number of electrons in the n-sidc. But the barrier
potential is negative on the p-sldc and positive on the n-side, and was
produced by holes flowing from p to n and electrons from n to p. Therefore,
the minority carrier flow tends to reduce the barrier potential. When an
external circuit is connected across the diode terminals, the minority carriers
390
Optoelectronic
Devices
will return to their original side via the external circuit. The electrons which
crossed the junction from p to n will now flow out through the n -terminal
and into the //-terminal. Similarly, the holes generated in the n-material
cross the junction and flow out through the //-terminal and into the n-termi-
nal. This means that the device is behaving as a battery with the n-side
being the negative terminal and the //-side the positive terminal. In fact, a
voltage can be measured at the photodiode terminal, positive on the //-side
and negative on the n-side. Thus, the photodiode is a photovoltaic device as
well as a photoconductive device.
Typical silicon photodiode illumination characteristics (plotted in the
first and second quadrants for convenience) are shown in Fig. 18-11. When
the device operates with a reverse voltage applied, it functions as a photo-
conductive device. When operating without the reverse voltage, it operates
as a photovoltaic device. It is also possible to arrange for a photodiode to
change from the photoconductive mode to the photovoltaic mode. The
circuit symbol for the device is also shown in Fig. 18-11.
(a) Photodiode
symbol
Reverse 1 Forward ^
voltage | voltage
(b) Illumination characteristics
Figure 18-11. Symbol and typical illumination characteristic for silicon photodiode.
A photodiode with the illumination characteristics shown in Fig. 18-11
is connected in series with a 200-12 resistance and a 0.5 V supply. The supply
polarity reverse biases the device. Draw the dc load line for the circuit and
determine the diode currents and voltages at 1500, 10,000, and 20,000
lm/m 2 illumination.
solution
The circuit is as shown in Fig. 18-12.
E s = I d Ri + V D
When 1 D = 0,
V d = E s =- 0.5 V
Plot points on Fig. 18-11 at / D = 0 and V D = — 0.5 V.
When V D = 0, V r =E s .
Id
-0.5 V
200 12
= 2.5 mA
1 t
Figure lft-12. Photodiode with load resistance.
Plot point B at I n = —2.5 mA and V D = 0 V.
Draw the dc load line through points A and B.
From the load line,
At 1500 lm/m 2 , / D « -0.2 mA and V D ^ -0.45 V
At 10,000 tm/m 2 , / D «- 1.9 mA and V D v -0.12 V
At 20,000 lm/m 2 , / D «- 3.6 mA and V D *z +0.22 V
Note that the polarity of V p changed from negative to positive at the
highest level of illumination.
Example 18-4
391
18-6
The Solar
Cell
The solar cell, or solar energy converter, is simply a large photodiode
designed to operate solely as a photovoltaic device and to give as much
output power as possible. Low-current photodiodes are generally packaged
in TO-type cans with an opening or a window on top. Devices for operation
as solar energy converters require larger surface areas to provide maximum
current capacity. The construction and cross section of a typical power solar
cell for use as an energy converter are shown in Fig. 18-13. The surface layer
of />-type material is extremely thin so that light can penetrate to the
junction. The nickel-plated ring around the p - type material is the positive
output terminal, and the plating at the bottom of the fl-type is the negative
output terminal. Power solar cells are also available in flat strip form for
Symbol
(a) Symbol and Construction
Light energy
mini
, Solder {positive contact)
Nickel plating
©
(§/ Direction of hole flow
Direction of electron flow
Solder (negative contact)
(b) Cross section
Figure 18-13. Symbol, construction, and cross section of a solar cell. (Courtesy of Solar
Systems, Inc.)
392
0 0.1 0.2 0.3 0.4 0-5 0.6 0.7 V
Outpui voltage
Figure 18-14. Typical output characteristics of power photocell for use as a solar energy
converter. (Courtesy of Solar Systems, Inc.)
efficient coverage of available surface areas. The circuit symbol normally
used for a photovoltaic device is also shown in Fig. 18-13.
Typical output characteristics of a power photocell arc shown in Fig.
18-14. Consider the device characteristic when the incident illumination is
100 mW/cm 2 . If the cell is short circuited, the output current is 50 mA.
Since the cell voltage is zero, the output power is zero. If the cell is open
circuited, the output current is zero. Therefore, the output power is again
zero. For maximum output power the device must be operated on the knee
of the characteristic. As in the case of all other devices, the output power
must also be derated at high temperatures.
An earth satellite has 12-V batteries which supply a continuous
current of 0.5 A. Solar cells with the characteristics shown in Fig. 18-14 are
employed to keep the batteries charged. If the illumination from the sun for
12 hours in every’ 24 is 125 mW/cm 2 , determine approximately the total
number of cells required.
solution
The circuit for the solar cell battery charger is shown in Fig. 18-15. The cells
must be connected in series to provide the required output voltage, and
393
The Solar
Cell
Example 18-5
394
Optoelectronic
Devices
13 V
Battery -=•
Figure IB-15. Array of solar cells connected as a battery charger.
groups of series-connected cells must be connected in parallel to produce the
necessary current.
For maximum output power, each device should be operated at
approximately 0.45 V and 57 mA (Fig. 18-14). Allowing for the voltage drop
across the rectifier, a maximum output of approximately 13 V is required.
Number of series-connected cells= out P ut volta g* = JiX- «29
cell voltage 0.45 V
The charge taken from the batteries over a 24-hour period is 24 hours X 0.5
A or 12 ampere-hours.
Therefore, the charge delivered by solar cells must be 12 ampere-
hours.
The solar cells deliver current only while they are illuminated, i.e., for
12 hours in every 24. Thus, the necessary charging current from the solar
cells is 12 ampere-hours/ 12 hours, or 1 A.
Total number of groups of cells in parallel = out P ut current
r cell current
The total number of cells required is (number in parallel) X (number in
series) = 18 X 29 = 522
18-7
The
Photo-
transistor
and Photo-
darlington
A phototransistor is similar to an ordinary bipolar transistor, except
that no base terminal is provided. Instead of a base current, the input to the
transistor is provided in the form of light. Consider an ordinary transistor
with its base terminal open circuited (Fig. 18-16). The collector- base
leakage current ( I CBO ) will act as a base current.
* CBO + &CBO
395
The Photo-
transistor
and
Photodarlington
Figure 18 - 16 . Currents in a transistor with its base open circuited.
Since
h = fidJB + ( Pdc + 1 ) IcBO ( 4 - 6 )
and
U - o
Ic~( Pdc + * ) I CBO
In this case, I c = Iceo> collector-emitter leakage current with the base
open circuited.
In the case of the photodiode, it was shown that the reverse saturation
current was increased by the light energy incident on the junction. Similarly,
in the phototransistor l CB0 increases when the collector-base junction is
illuminated. When I CBO is increased, the collector current [(/? dc + IKcboI * s
also increased. Therefore, for a given amount of illumination on a very small
area, the phototransistor provides a much larger output current than that
available from a photodiode; i.e., the phototransistor is the more sensitive of
the two.
The circuit symbol and typical output characteristics of the phototran-
sistor are shown in Fig. 18-17. Some phototransistors have no base terminal
and rely upon the incident illumination to generate a base current. Others
have a base connection provided so that an external bias circuit may be
connected. The device is usually packaged in a metal can with a lens on top.
Clear plastic encapsulated phototransistors arc also available.
Arrays of phototransistors and photodiodes arc widely applied as
photodetectors for such applications as punched card and tape read out. The
phototransistors have the advantage of greater sensitivity than photodiodes.
For a given level of illumination a greater output current is produced by a
phototransistor than by a photodiode. However, photodiodes arc the faster of
the two, switching in less than nanoseconds, compared to typical phototran-
sistor switching times of microseconds.
3%
Optoelectronic
Devices
Example 18-6
Figure 18*17. Phototransistor circuit and dc load line.
A phototransistor having the characteristics shown in Fig. 18-17 has a
supply of 20 V and a collector load resistance of 2 k£2. Determine the output
voltage when the illumination level is (a) zero, (b) 20 mW/cm 2 , and (c)
40 m W / cm 2 .
solution
The load line is drawn in the usual way.
When 7 C = 0, V CE = V cc .
Plot point A at 7 C = 0, V CE = 20 V.
When V CE = 0 y 7 C = V CC /R L = 20 V/2 k«=10 mA.
Plot point B at ^CE = 0, I c = 10 mA.
Draw the dc load line through points A and B.
From the intersections of the load line and the characteristics,
At illumination level = 0, output voltages V CE = 20 V
At illumination level = 20 mW/ cm 2 , outputs 12.5 V
At illumination level = 40 mW / cm 2 , output«s4 V
The photoda rlington (Fig. 18-18) consists of a phototransistor connected
in Darlington arrangement (see Chapter 9) with another transistor. The
device is capable of much higher output currents than a phototransistor, and
so it has a greater sensitivity to illumination levels than either a phototran-
sistor or a photodiode. With the additional transistor involved, the photo-
darlington has a considerably longer switching time than a phototransistor.
397
The
PhoioFET
Figure 18-18. The photodarlington.
If a junction field effect transistor has light focused on its gate-channel
junction, the light will act as a signal and produce a change in the drain
current. Consider the n-channel junction FET and the photoFET in Fig.
18-19. The gate-source leakage current (less) * s rever se saturation current at
a reverse-biased /^-junction and is temperature dependent. As in the case of
the phototransistor, the junction reverse saturation current is also susceptible
to light. Illumination on the junction causes more charge carriers to be
generated and hence causes I^s to increase. flows through bias resis-
tance R g and causes a voltage drop across R G with the polarity shown. Thus,
if — V G were just sufficient to bias the device off when dark, then when the
junction is sufficiently illuminated the increase would cause the gate
voltage to increase and bias the FET on. A gate bias voltage that partially
biases the device on might also be employed, so that increasing and
decreasing the light level causes the I D to increase and decrease. In a
photoFET, the light-controlled is referred to as the gate current (A/ # ). J ^
then becomes the dark gate leakage current. The light-controlled drain current
is designated \I d .
18-8
The
PhotoFET
Junction FET circuit
Photofel circuit
Figure 18-19. Junction FET and photoFET circuits showing effect of leakage currents.
398
Optoelectronic
Devices
18-9
Light-
Emitting
Diodes
The gate-source voltage changes are proportional to the gate current
and the gate bias resistance.
&V GS = \I g XR G
and
M d — g m X A Vqs
=g m K R o
The selected value of R G determines the sensitivity of the photoFET. For
\I g =lO nA,g m = 8 mA / V and R G = 1 Mfl,
\I d = 8mA/VX10nAXl
= 80 (jlA
If R c is increased to 10 M£2, \I d becomes 800 pA.
Typical photoFET currents are
less ~ 8.5 nA
\I g = 50 nA / n W /cm 2
\I d = 500 fiA/ fiW/cm 2
Charge carrier recombination takes place at a ^i-junction as electrons
cross from the n-side and recombine with holes on the /?-side. Free electrons
are in the conduction band of energy levels while holes are in the valence
band. Therefore, electrons are at a higher energy level than holes, and some
of this energy is given up in the forms of heat and light when recombination
takes place. If the semiconductor material is translucent, the light will be
emitted and the junction becomes a light source, i.e., a light- emitting diode
(LED).
A cross section view of a typical diffused LED is shown in Fig. 18-20.
The semiconductor material employed is gallium arsenide (GaAs), gallium
arsenide phosphide (GaAsP), or gallium phosphide (GaP).
A n-type epitaxial layer is grown upon a substrate, and the /^-region is
created by diffusion. Charge carrier recombinations occur in the /^-region, so
it must be kept uppermost. The /^-region, therefore, becomes the surface of
the device, and the metal film anode connection must be patterned to allow
most of the light to be emitted. This is done by making connection to the
outside edges of the p - type layer, or by depositing a comb-shaped pattern at
the center of the p - type surface. A gold film is applied to the bottom of the
substrate to reflect as much as possible of the light toward the surface of the
device and to provide a cathode connection. LED’s made from GaAs emit
infrared radiation (i.e., it is invisible). GaAsP material provides either red
light or yellow light while red or green emission can be produced by using
GaP.
Charge carrier
recombination
Metal film
399
anode
Light-
connections
Emitting
Diodes
- Diffused
p-type
-Epitaxial
type
Gold film
cathode
connection
Figure 18-20. Cross section of light-emitting diode.
Figure 18-21 shows the LED circuit symbol (the arrow directions
indicate emitted light) and the arrangement of a typical seven-segment LED
numerical display. Any desired numeral from 0 to 9 can be displayed by
passing current through the appropriate segments. The actual LED device is
very small, so to enlarge the lighted surface solid plastic light pipes are often
employed, as illustrated in Fig. 18-21(c).
(a) Circuit system
(b) Seven-segment arrangement
Light pipe
LED
(c) Construction of seven-segment
LED display
Figure 18-21. Light-emitting diode and seven-segment display.
400
Optoelectronic
Devices
Example 18-7
Figure 18-22. LED and transistor switch.
The forward voltage for a LED is typically 1.2 V, and for forward
current 20 mA is typical. The relatively large amounts of current consumed
by LED’s are their major disadvantage. Excluding displays, all the circuitry
of an electronic counter might require a total operating current of less than
100 mA. Four seven-segment LED displays could add 500 mA to this
requirement, necessitating the inclusion of a much bulkier power supply.
Apart from this, LED’s do have the advantage of long life and ruggedness.
Light-emitting diodes are usually switched on and off by means of a
transistor circuit like the one illustrated in Fig. 18-22. The voltage drop
across the LED is typically 1.2 V, and the transistor saturation voltage is
approximately 0.2 V (i.e., for low I c levels). Resistor R 2 is necessary to limit
the current through the LED to the desired level. Example 18-7 shows how
to design such a circuit.
The LED shown in Fig. 18-22 is to have a current of approximately 10
mA passed through it when the transistor is on. The transistor employed is a
2N3904 (data sheet in Fig. 8-1). The supply voltage is V cc = 9 V, and the
input voltage is V- = 7 V. Calculate the required values of /?, and R 2 .
solution
^CC = 1 + IcR 2 + VcE( sat)
r, _ V CC~ V Dl~ ^CE( sat)
r 2 -
l C
_ 9V-1.2V-0.2V
10 mA
= 760 fi (use 680-& standard value; see Appendix 1 )
I c becomes
9 V- 1.2 V — 0.2 V
680
= 11.2 mA
401
Liquid-
Crystal
Displays
(LCD)
1b ~ lc/^FE(iruny
From Fig. 8-1, A ££(inin) = 100 when / c ^10 mA.
_ 1 1.2 mA _
B 100
v-i b r x +v be
12 mA
K- v be _ 7 V — 0.7 V
I B 1 12 |xA
«56 kfi (standard value)
18-10
Liquid-
Crystal
Displays
(LCD)
The molecules in ordinary liquids normally have random orientations. 18-10.1
In liquid crystals the molecules are oriented in a definite crystal pattern. Dynamic
When an electric field is applied to the liquid crystal, the molecules, which
are approximately cigar shaped, tend to align themselves perpendicular to
the field. Charge carriers flowing through the liquid disrupt the molecular
alignment and cause a turbulence within the liquid. This is illustrated in
Fig. 18-23. When not activated, the liquid crystal is transparent. When
activated, the molecular turbulence causes the light to be scattered in all
directions so that the activated areas appear bright. This phenomenon is
known as dynamic scattering. The actual liquid-crystal material may be one of
several organic compounds which exhibit the optical properties of a solid
while retaining the fluidity of a liquid. Examples of such compunds arc
cholesleryl nonanoate and p-azoxyanisole.
A liquid-crystal cell consists of a layer of liquid -crystal material
sandwiched between glass sheets with transparent metal film electrodes
deposited on the inside faces (Fig. 18-24). With both glass sheets transparent,
the cell is known as a transmittive-type cell. When only one glass sheet is
transparent and the other has a reflective coating, the cell is termed reflective
type. The application of both types is illustrated in Fig. 18-25.
When not activated, the transmittive-type cell will simply transmit
rear or edge lighting through the cell in straight lines. In this condition the
cell will not appear bright. When activated, the incident light is diffusely
402
Optoelectronic
Devices
18 - 10.2
Field
Effect
LCD
18 - 10.3
Electrical
Characteristics
CD CD ^ CD
°o CD^
CD Q CD) CD
3 CD CD
(a) Molecules in liquid crystal
(b) Charge carrier flow through
when no current flowing
liquid crystal disturbs molecular
alignment and causes turbulence
Figure 18-23. Molecules in a liquid crystal and effect of charge carrier flow.
Liquid
Transparent
crystal
electrodes
\
Glass
//
\ jaftr- r-
h v -:
\
1
Spacer Mirror surface
in reflective
type cell
Figure 18-24. Construction of liquid-crystal cell.
scattered forward, as shown in Fig. 18-25(a), and the cell appears quite
bright even under high-intensity ambient light conditions. The reflective-
type cell operates from light incident on its front surface. When not
activated, light is reflected in the usual way from the mirror surface, and the
cell does not appear bright. When activated the dynamic scattering phenom-
enon occurs, and the cell appears quite bright [Fig. 18- 25(b)].
The field effect LCD is constructed similarly to the dynamic scattering
type (Fig. 18-24), with the exception that two thin polarizing optical filters
are placed at the surface of each glass sheet. The liquid-crystal material
employed is known as twisted nematic type, and it actually twists the light
passing through when the cell is not energized. This twisting allows the light
to pass through the polarizing filters. Thus, in the case of a transmittive-type
cell, Fig. 18-25(a), the unenergized cell can appear dark against a bright
background. When energized, the cell becomes transparent and disappears
into the background.
Since liquid-crystal cells are light reflectors or transmitters rather than
light generators, they consume very small amounts of energy. The only
energy required by the cell is that needed to activate the liquid crystal. The
total current flow through four small seven-segment displays is typically
about 25 juA for dynamic scattering cells and 300 pA for field effect cells.
However, the LCD requires an ac voltage supply, either in the form of a sine
(a) Transmittive type
403
Liquid-
Crystal
Displays
(LCD)
Light reflected
Light
source
Light scattered
(b) Reflective type
Figure 18-25. Operation of liquid-crystal cells.
wave or a square wave. This is because a continuous direct current flow
produces a plating of the cell electrodes, which could damage the device.
Repeatedly reversing the current avoids this problem.
A typical supply for a dynamic scattering LCD is a 30 V peak-to-peak
square wave with a frequency of 60 Hz. A field effect cell typicaJIy uses 8 V
peak-to-peak. Figure 18-26 illustrates the square wave drive method for
liquid-crystal cells. The back plane , which is one terminal common to all cells,
is supplied with a square wave. A similar square wave is applied to each of
the other terminals. These square waves are either in phase or in antiphase
with the back plane square wave. Those cells with waveforms in phase with
the back plane waveform (cell e and / in Figure 18-26) have no voltage
developed across them (both terminals of the segment are at the same
potential); therefore, they are off. The cells with square waves in antiphase
with the back plane input have an ac voltage developed across them (e.g.,
positive square waves with 15 V peak effectively produce 30 V peak-to-peak
when in antiphase). Therefore, the cells which have square wave inputs in
antiphase with the back plane input are energized and appear bright.
Unlike LED displays, which are usually quite small, liquid-crystal
displays can be fabricated in almost any convenient size. The maximum
power consumed for a typical LCD used in electronics equipment is around
20 jiW per segment, or 140 /iW per numeral when all seven segments are
energized. Comparing this to about 400 mW per numeral for a LED display
(including series resistors), the major advantage of liquid-crystal devices is
404
Optoelectronic
Devices
Back plane input V t
Effective voltage
waveform across
energized segment
Back plane
Figure 18-26. Square wave drive method for liquid-crystal display.
obvious. Perhaps the major disadvantage of the LCD is its decay time of
150 ms (or more). This is very slow compared to the rise and fall times of
LED’s. In fact, the human eye can sometimes observe the fading out
of LCD segments switching off. At low temperatures the response time is
considerably increased.
18-11
Gas-
Discharge
Displays
The type of seven-segment gas-discharge display illustrated in Fig.
18-27 is widely applied today in electronic calculators. It is actually a
gas-filled tube. Separate cathodes in seven-segment format are provided on
the base of the device, and the anode (for each seven-segment group) is a
transparent metal film deposited on the covering faceplate. Gas is contained
in the narrow space between the faceplate and the base.
When a high voltage is provided between the anode (positive polarity
here) and one or more of the cathodes, the gas is ionized and causes a glow
around each cathode. Thus, any desired numerals can be displayed depend-
ing upon the cathodes selected. Neon gas is usually employed, and this gives
a red-orange glow; however, other colors are available with different gases.
The supply voltage required for gas-discharge displays is on the order
of 140 to 200 V. This is the most serious disadvantage of the device when
used with transistor circuits. Offsetting this is the fact that relatively bright
displays are possible with current levels of only 200 juA. A 50-juA current
anode pattern
Figure 18-27. Seven-segment gas-discharge display.
(Courtesy of Beckman Instruments, Inc.)
405
Oplo-electronic
Couplers
(normally not enough to produce a glow) is usually maintained through the
keep alive cathode (see Fig. 18-27) to ensure that the device switches on rapidly.
An optoelectronic coupler (or optically coupled isolator) is basically a photo-
transistor and a light-emitting diode combined in one package. Figure 18-28
shows the typical circuit and terminal arrangement for one such device
contained in a dual-in-line plastic package.
When current flows in the diode, the emitted light is directed to the
phototransistor and causes current flow in the transistor. The coupler may
be operated as a switch y in which case both the LED and phototransistor arc
normally off. A pulse of current through the LED causes the transistor to be
switched on for the duration of the pulse. Since the coupling is optical, there
is a high degree of electrical isolation between input and output terminals.
Three additional types of optical couplers are illustrated in Fig. 18-29.
They are (a) Darlington output type, (b) SCR output, and (c) TRIAC
18-12
Opto-
electronic
Couplers
6
5
4
Figure 18-28. Optoelectronic coupler with transistor output
406
Optoelectronic
Devices
u
i i i o
(b) SCR output
r
(c) Triac output
Figure 18-29. Three types of optoelectronic coupler.
output. In (a) the photodarlington output stage provides much higher
output current (i.e., for a given LED current) than is possible with a
phototransistor output stage. The output stages in (b) and (c) are a light-
activated SCR and a light-activated TRIAC, respectively. They are applied
in the kind of control circuits discussed in Chapter 16, where an additional
requirement is high electrical isolation between triggering current and
control device.
The following is a list of the most important parameters for an
optoelectronic coupler:
Input to output isolation voltage (V^). This is the maximum voltage
difference that can exist between input and output terminals. Typical values
range up to 7500 V.
Current transfer ratio (CTR). The ratio of output (photo transistor) current
to input (LED) current, expressed as a percentage. For a phototransistor
output stage CTR values can be anything from 10% to 150%. For a 407
photodarlington, CTR might easily be 500%. CTR does not apply to SCR Lasef
and TRIAC output stages; instead, the required triggering current (through
the LED) is of interest.
Response time. Divided into rise time (/,) and fall time (tf). For phototransistor
output stages l T and t f are usually around 2 to 5 /is. With a Darlington
output, t r may be 1 /is or less while t f could be 1 7 /is.
Laser is the shortened form of light amplification by stimulated emission of 18-13
radiation . A laser emits radiation of essentially one wavelength (or a very Laser
narrow band of wavelengths). This means that the light has a single color (is Diode
monochromatic); i.e., it is not a combination of several colors. Laser light is
referred to as coherent light as opposed to light made up of a wide band of
wavelengths, which is termed incoherent.
The unique property of light generated by a laser is that the emission
is in the form of a very narrow beam without significant divergence. The
beam of light contains sufficient energy to weld metals or to destroy
cancerous growths. It can also be applied to precise measurements, to
guidance of industrial machinery, and to optical fiber communication tech-
niques.
Consider the light-emitting diode. The source of light is the energy
emitted by electrons which recombine with holes (at a lower energy level).
In the case of an LED, the light is incoherent; i.e., it is made up of a wide
spectrum of wavelengths.
In a laser the atoms are struck by photons (or packets of energy) which
are exactly similar to the photons of energy emitted when recombination
occurs. This triggers the energy emission and results in two identical photons
for each recombination: the incident photon and the emitted photon. The
photons produce further emission of similar photons, which in turn creates
more similar photons. The result is an emission of energy in the form of a
beam of coherent light.
The operating principle of the laser diode is illustrated in Fig. 18-30. A
pn junction of gallium arsenide (GaAs), or GaAs combined with other
materials, is manufactured with a precisely defined length ( L ) [Fig. 18-30
(a)]. The junction length is related to the wavelength of the light to be
emitted. The ends of the junction are each polished to a mirror surface and
may have an additional reflective coating. The purpose of this is to reflect
internally generated light back into the junction. One end is only partially
reflective so that light can pass through when lasing occurs.
Consider the effect of charge carrier injection into the depletion region
when the junction is forward biased [Fig. 18-30(b)]. As the forward current
increases, a growing number of charge carriers enter the depletion region
and excite the atoms that they strike. The atoms at first emit photons of
energy randomly, as electrons are raised to a high energy level and then fall
back to a lower level. Sooner or later several photons strike the reflective
408
Optoelectronic
Devices
Reflective end
Reflective end
Depletion
region
(a) Basic construction of laser diode.
(b) Random emission and laser action within
depletion region.
Figure 18*30. Laser diode construction and operation.
ends of the junction perpendicularly so that they are reflected back along 409
their original (incident) path. These reflected photons arc then reflected ^Im^rtant
back again from the other end of the junction. The reflection back and Terms
forward continues thousands of times, and the photons increase in number as
they cause other similar photons to be emitted from atoms. This activity of
reflection and generation of increasing numbers of photons amounts to
amplification of the initial reflected photons of light. The beam of laser light
emerges through the partially reflective end of the junction.
GaAs laser diodes normally require high forward current levels, any-
thing from about 100 mA up to tens of amperes. At low current levels the
device emits light like a LED. Beyond a threshold current level the light
intensity increases sharply, and its bandwidth decreases as lasing com-
mences. Because of the high-energy density a laser beam can be quite
dangerous. Eye protection must be worn when working with these devices.
Laser diodes which operate in a pulsed manner are termed injection laser
diodes. Those which produce a continuous output are referred to as continuous
wave or CW laser diodes. Each type has a threshold input current level, and
each emits a particular light wavelength dependent upon the material and
dimensions of the junction.
Optoelectronic device. Electronic device which emits light, is operated by Glossary of
light, or modifies light. Important
Photoemissive device. Device in which incident radiation causes electrons
to be emitted from a photocathode.
Photoconductive device. Device which changes its resistance when
illuminated.
Photovoltaic device. Device which generates a voltage when illuminated.
Spectral response. Plot of device response to illumination versus illumina-
tion frequency.
Threshold frequency. Minimum frequency of incident radiation that will
produce a photoelectric effect in a given device.
Threshold wavelength. l/(threshold frequency) — maximum wavelength
of incident radiation that will produce a photoelectric effect in a given
device.
Lumen. Unit of luminous flux.
Microlumen. 10 -6 lumens.
Lumen per square meter (lm/m 2 ). Unit of luminous flux density.
Milliwatts/square centimeter (mVV/cm 2 ). Unit of luminous flux density.
Photomultiplier. Electron tube in which incident radiation produces elec-
tron emission which is multiplied by secondary emission to produce
usable current levels.
Photocathode. Electrode with surface that emits electrons when
illuminated.
410
Optoelectronic
Devices
Review
Questions
Dark current. Current which flows in photoelectric device when not
illuminated.
Illumination characteristic. Graph showing change of resistance, voltage,
and/or current with illumination change.
Cadmium sulfide. Material used in the manufacture of photoconductive
device — rise time « 100 ms — spectral response similar to human eye.
Cadmium selenide. Material used in the manufacture of photoconductive
device — rise time «10 ms — spectral response extends into infrared
region.
Photodiode. Diode in which the reverse saturation current level changes
when the junction is illuminated — photoconductive-photovoltaic de-
vice.
Solar cell. Photovoltaic cell — generates a voltage when illuminated.
Phototransistor. Transistor in which I c changes when the collector-base
junction is illuminated.
Photodetector. Phototransistor or photodiode employed to detect presence
of light.
Photodarlington. Phototransistor connected in Darlington arrangement
with another transistor.
PhotoFET. Junction field effect transistor in which I D changes when
gate-channel junction is illuminated.
Light-emitting diode (LED). Diode in which charge carrier recombination
produces light emission.
Liquid-crystal cell. Electronic display device in which liquid-crystal
material can be made to appear bright or dark.
Seven-segment display. Arrangement of seven LED’s, LCD’s, or other
light-emitting devices to display numerals from 0 to 9.
Gas-discharge display. Gas-filled tube in which ionized gas displays
numerals.
Optoelectronic coupler. Combination of light-emitting diode and photo-
transistor, photodarlington, light-activated SCR or TRIAC.
Laser. Light amplification by stimulated emission of radiation.
18-1. Using illustrations, explain the operation of a photomultiplier tube.
Also sketch typical characteristics for a photomultiplier tube and
briefly explain.
18-2. Draw a sketch of a typical photomultiplier circuit. Briefly explain.
18-3. Sketch the symbol, typical construction, and characteristics for a
photoconductive cell. Discuss the principle of this type of photocell,
and compare the kinds of material usually employed.
18-4. Sketch typical illumination characteristics for a photodiode, and
explain the theory of the device.
18-5. Draw circuit diagrams to show how a photoconductive cell may be
employed for
(a) Biasing a pnp transistor off when the cell is illuminated.
(b) Biasing an npn transistor on when illuminated.
(c) Measuring light level.
(d) Energizing a relay when illuminated.
18-6. Sketch the cross section of a typical solar cell, and briefly explain how
it operates.
18-7. Sketch the circuit diagram for an array of solar cells employed as a
battery charger. Briefly explain.
18-8. Sketch the circuit symbol and characteristics for a phototransistor.
Explain how it operates. Discuss the application of phototransistors,
photodarlingtons, and photodiodes as photodetectors.
18-9. Sketch a circuit diagram to show the operation of a photoFET
circuit. Briefly explain the principle of the device.
18-10. Using illustrations, explain the construction and operation of light-
emitting diodes. Show the circuit symbol for a light-emitting diode,
and show how an LED numerical display is arranged. Also discuss
the current levels required by LED numerical displays.
18-11. Using illustrations, explain the theory of the liquid-crystal cell. Show
how a liquid-crystal cell is constructed, and explain the difference
between dynamic scattering and field effect LCD’s and between
reflective- and transmittive-type cells. Also compare liquid-crystal
cells and light-emitting diodes.
18-12. Sketch a seven-segment LCD and show the waveforms involved in
controlling the cells. Explain.
18-13. Draw a sketch to show the construction of a seven-segment gas-dis-
charge display. Explain how' the device operates and discuss its
advantages and disadvantages.
18-14. Using diagrams, explain the various types of optoelectronic couplers.
Discuss the most important parameters and the applications of
optoelectronic couplers.
18-15. Draw sketches to show the basic construction and operation of a laser
diode. Explain how the device operates and compare its performance
to that of an LED.
18-1. A photoconductive cell 2 cm in diameter is to receive 400 Im/m of
light energy from a lamp 7 meters distant from the cell. If the lamp
emits energy evenly in all directions, determine the required light
energy output from the lamp. Also calculate the total luminous flux
striking the photocell.
18-2. The total luminous flux striking a surface of a solar cell is measured
as 12.5 mW. The light source is 4.5 meters from the solar cell.
411
Problems
Problems
412
Optoelectronic
Devices
Calculate the light energy output from the source if it emits light
evenly in all directions. The surface area of the solar cell is 6 cm 2 .
18-3. A pnp transistor is to be biased on when the level of illumination on a
photoconductive cell is greater than 100 lm/m 2 and off when dark.
The supply voltage available is ±5 V, and the transistor collector
current is to be 10 mA when on. If the transistor has a h FE of 50 and
the photoconductive cell has the characteristics shown in Fig. 18-5,
design a suitable circuit.
18-4. The light meter in Fig. 18-9 has the following components: E B =\.h
V, £ t = 13.8 k£2, £ 2 = 390 12, and meter resistance £ m = 390 12. The
photoconductive cell has the characteristics in Fig. 18-5. Calculate
the meter indication when the illumination level is (a) 400 lm/m 2 ;
(b) 7 lm/m 2 .
18-5. A photodiode is connected in series with a resistance and a reverse
bias supply of 0.4 V. The diode has the illumination characteristics of
Fig. 18-11 and is required to produce an output of +0.2 V when
illuminated with 20,000 lm/m 2 . Calculate the value of the series
resistance required, and determine the device voltage and current at
5000 lm/m 2 of illumination.
18-6. A photodiode with the characteristics shown in Fig. 18-11 is con-
nected in series with a 0.4- V supply and a 100-S2 resistance. De-
termine the resistance offered by the photodiode at 15,000 lm/m 2 ,
10,000 lm/m 2 , and 5000 lm/m 2 .
18-7. Two photodiodes are each connected in series with 100-12 resistors
and a 0.5 V supply. A voltmeter is connected to measure the
difference in voltage drops across the two diodes. Assuming that each
photodiode has the characteristics illustrated in Fig. 18-11, estimate
the voltmeter reading when one diode has 10,000 lm/m 2 incident
illumination and that on the other diode is 12,500 lm/m 2 .
18-8. A rural telephone system uses 6-V rechargeable batteries which
supply an average current of 50 mA. The batteries are recharged
from an array of solar cells which each have the characteristics shown
in Fig. 18-14. The average level of sunshine is 50 mW/cm 2 for
12 hours of each 24-hour period. Calculate the number of solar cells
required, and determine how they should be connected.
18-9. The roof of a house has an area of 200 m 2 and is covered with solar
cells which are each 2 cmX2 cm. If the cells have the output
characteristics shown in Fig. 18-14, determine how they should be
connected to provide an output voltage of approximately 120 V.
Take the average daytime level of illumination as 100 mW/cm 2 . If
the sun shines for an average of 12 hours in every 24, calculate the
kilowatthours generated by the solar cells each day.
18-10. A phototransistor operating from a 25 V supply has the output
characteristics shown in Fig. 18-18. If V C E is to be 10 V when the
illumination level is 30 mW/cm 2 , determine the value of load
resistance that should be used.
18-11. A phototransistor with the characteristics shown in Fig. 18-17 is
connected in series with a relay coil which has a resistance of 1 kft.
The coil current is to be 8 mA when the illumination level is 40
mW/cm 2 . Determine the required supply voltage level, and estimate
the coil current when the illumination falls 10 mW/cm 2 .
18-12. Two light-emitting diodes are connected in series. The current
through the diodes is to be controlled by a 2N3903 transistor (see Fig.
8-1), and the supply voltage is J'cc = 1 2 V. The diode current is to be
approximately 15 mA. Design a suitable circuit.
18-13. A light-emitting diode is to be used to indicate when a 25 V supply is
switched on. The LED current is to be 20 mA. Sketch a suitable
circuit and make all necessary calculations.
413
Problems
CHAPTER
19
19-1
Piezo-
electricity
19-2
Piezoelectric
Crystals
19 - 2.1
Theory of
Piezo-
electricity
Miscellaneous
Devices
If a mechanical pressure is applied to a quartz crystal, a voltage
proportional to the pressure appears across the crystal. Conversely, when a
voltage is applied across the crystal surfaces, the crystal is distorted by an
amount proportional to the voltage. All crystals with this property are
termed piezoelectric. An alternating voltage applied to a crystal causes it to
vibrate at its natural resonance frequency. Since this frequency is a very
stable quantity, piezoelectric crystals are used to stabilize the frequency of
oscillators.
Consider the flat plan diagram of a piezoelectric crystal structure in
Fig. 19- 1(a). The broken lines join groups of ions. It is seen that each group
consists of three positive ions at the corners of an equilateral triangle and
414
415
Piezoelectric
Crystals
Pressure applied
(c) Crystal distortion
resulting from
applied voltage
Movement
Figure 19-1. Flat plan diagrams of piezoelectric crystal, showing how voltag
ated by applied pressure, and how distortion is produced by applied voltage.
e is gener-
416
Miscellaneous
Devices
three negative ions at the corners of another triangle. The charge from the
three positive ions is concentrated at the geometric center of the triangle
formed by the positive ions, and the negative charge is concentrated at the
geometric center of the triangle formed by the negative ions. Since these
geometric centers are coincident the charges cancel, and each group of ions
is electrically neutral.
Figure 19- 1(b) shows the result of applying a mechanical force along
the Y axis of the structure. The distance between negative ions a and b is
reduced, and the distance from a and b to negative ion c is increased. The
three ions are now no longer at the corners of an equilateral triangle. The
geometrical center of the triangle has been moved to the left, and thus the
center of the negative charge has been moved left. In a similar way the
center of positive charge for each system of positive ions has been moved to
the right. Thus, along the X axis there is now a potential, negative on the left
and positive on the right. The potential produced by one group of ions is
extremely small. However, each crystal consists of a great many such atomic
groups, so the resultant potential is measurable.
To understand the converse effect, consider Fig. 19- 1(c). Instead of
applying a pressure at the Y axis , an electrical potential is applied at the X
axis. All negative ions are now displaced toward the positive terminal, and
positive ions are displaced toward the negative terminal. The result is that
the crystal is distorted along the Y axis. The distortion may be reversed by
reversing the potential. Applying an alternating potential causes the crystal
to vibrate. For each crystal there is a natural frequency of resonance at
which maximum continuous oscillations can be made to occur.
19 - 2.2
Manufacture
of Quartz
Crystals
Crystals of Rochelle salt, tourmaline , and quartz all possess piezoelectric
properties. Rochelle salt demonstrates the greatest piezoelectric effect, but its
applications are limited because it is strongly affected by moisture and heat.
Tourmaline and quartz show approximately similar piezoelectric effects, but
tourmaline is semiprecious and quartz is inexpensive, so quartz is universally
employed in electronics.
The manufacture of electronic crystals begins by cutting a natural or
cultured quartz crystal into sections. In its uncut state the crystal is ap-
proximately in the form of the hexagonal prism as shown in Fig. 19-2(a).
The Z axis, passing through the ends of the prism, is known as the optical axis.
No piezoelectric effect is produced by electrical or mechanical stresses along
the Z axis. The X axes, which pass through the corners of the hexagonal
cross section and are perpendicular to the Z axis, are termed the electrical axes
[Fig. 1 9— 2(b)]. The mechanical axes are the Y axes passing through the faces of
the hexagonal prism. Mechanical stress along a Y axis produces a voltage
along the perpendicular X axis.
A great variety of crystal cuts is possible and each has its own particular
characteristics. Figure 19-3 shows an X-cut and a Y-cut. A mechanical stress
(a) Approximate shape (b) Cross section
of natural crystal
Figure 19-2. Approximate shape and cross section of natural quartz crystal.
417
Piezoelectric
Crystals
applied to the edges of an A'-cut crystal generates an electrical potential
across the flat sides. Similarly, a mechanical stress on the flat sides of a V'-cut
crystal generates an electrical potential across its edges. The change of
crystal resonant frequency with temperature increase or decrease is termed
the crystal temperature coefficient. Obviously, for greatest frequency' stability of
oscillations, the smallest possible temperature coefficient is desirable. Two
cuts, the GT cut and the ring-shaped cut, shown in Fig. 19-4, are widely
employed because they have near-zero temperature coefficients.
The sections cut from the crystal are referred to as blanks. Each blank
must be carefully ground to accurate dimensions to achieve the desired
resonance frequency. After grinding, silver or gold electrodes are plated onto
opposite sides of the blank to form electrical connections. The crystal is then
mounted inside a vacuum-sealed glass envelope or in a hermetically sealed
Figure 19-3. X -and V-cut crystal sections.
418
Miscellaneous
Devices
(a) GT*cut (b) Ring shaped cut
Figure 19-4. CT - cut and ring-shaped crystal cut give near-zero temperature coefficient.
metal can. Figure 19-5 shows a ring-shaped crystal mounted on a base and
its can-type enclosure.
19 - 2.3
Crystal
Equivalent
Circuit and
Performance
The electrical equivalent circuit for a crystal is shown in Fig. 19-6(a).
The crystal actually behaves as a series LCR circuit in parallel with C m , the
capacitance of the mounting electrodes. Because of the presence of C m , the
crystal has two resonance frequencies [Fig. 19— 6(b)]. One of these is the series
Figure 19-5. Ring-shaped crystal and hermetically sealed metal can. (Courtesy of Inter-
national Crystal Mfg., Inc.)
C m i
Frequency
(a) Equivalent circuit
(b) Resonance frequencies
Figure 19-6. Crystal equivalent circuit and resonance frequencies.
resonance frequency (/j) at which 2itfL = 1 /(2fl/C). In this case the crystal
impedance is very low. The other resonance frequency (/ 2 ) is slightly higher
than /,, and is due to parallel resonance of the capacitance C m and the
reactance of the series circuit. At / 2 the crystal impedance is very high.
When a circuit is operating at its resonance frequency, the capacitive
and inductive reactances cancel each other out, and the power supplied to
the circuit is dissipated in the resistance. If the resistance is large, the power
dissipation can cause drift of the resonance frequency. A measure of the
quality of a resonance circuit is the ratio of reactance to resistance. This is
termed the Q factor. Since the resistive component of the crystal equivalent
circuit tends to be very small, crystals have very large Q factors. Crystal Q
factors range approximately from 10 4 to 10 6 compared to a maximum of
about 400 for an ordinary electrical resonance circuit.
Most crystals will maintain frequency drift to within a few cycles at
25°C. For greater frequency stability, the crystal is often contained in an
insulated enclosure termed a crystal oven. A typical crystal oven is shown in
Fig. 19-7. The temperature is thermostatically controlled. Typical heater
power is 4 W and heater voltage is 6 to 24 V.
419
Piezoelectric
Crystals
To stabilize the frequency of an oscillator, a crystal may be operated at
either its parallel or series resonance frequency. For very high frequency
applications, crystals are often used to control oscillators operating at a
multiple of the crystal resonance frequency. In this situation, the crystal is
said to be operating in overtone.
Figure 19-8 shows an oscillator in which the crystal is operating in
parallel resonance; note the circuit symbol for the crystal. Transistor Qj
combined with /?,, R 2 , RFC , and R E constitutes a common base circuit.
Capacitor C x provides an ac short circuit across R 2 to ensure that the
19 - 2.4
Crystal
Oscillators
420
Miscellaneous
Devices
Figure 19-7. Temperature-controlled crystal oven. (Courtesy of Erie Technological Prod-
ucts, Inc.)
transistor base remains at a fixed voltage level. C 2 and C 3 form a capacitive
voltage divider which returns a portion of the output voltage to the emitter
of Qj. As the output voltage increases positively, the emitter voltage also
increases, and since the base voltage is fixed, the base-emitter voltage is
reduced. The reduction in Vbe causes I c to be reduced, and this in turn
causes the collector voltage V c to increase positively. Thus, the circuit is
supplying its own input and a state of oscillation exists. The crystal in
parallel with C 2 and C 3 permits maximum voltage feedback from collector to
emitter when its impedance is very high, i.e., at its parallel resonance
frequency. At other frequencies the crystal impedance is low, and the low
impedance causes the feedback voltage to be too small to sustain oscillations.
The oscillation frequency is stabilized at the parallel resonance frequency of
the crystal.
The Colpitts oscillator in Fig. 10-4 is one circuit in which a crystal
could be employed in its series resonance mode. The crystal should be
Figure 19-8. Crystal-controlled oscillator with crystal operating in parallel resonance.
substituted in place of coupling capacitor C c . Maximum feedback occurs
when the crystal impedance is a minimum, i.e., at the series resonance
frequency.
Crystal oscillators must be designed to provide a load capacitance on
the crystal as specified by the manufacturer. This is necessary to obtain
oscillation at the specified frequency. It is also important that the power fed
to the crystal be held to the specified maximum. Too much crystal power
produces distortion in the oscillator waveform. It also causes overheating of
the crystal and consequently renders the resonant frequency unstable. More
important is that the thin-plated electrodes may be melted off an overdriven
crystal, destroying the device. In older types of crystals where more solid
plates were employed, the crystal was sometimes shattered by overdriving.
Typical maximum drive levels for plated crystals range from 2 to 10 m\V.
The maximum allowable drive power limits the ac voltages that may
be applied across the crystal, and consequently affects the design of oscillator
circuits. Crystal manufacturers usually specify the resistance of each crystal,
as well as a maximum drive power. From these two, the maximum crystal ac
voltage may be calculated.
A certain crystal is specified as having a resistance of 625 S2. If the
drive power is not to exceed 10 mW, calculate the maximum peak-to-peak
ac voltage that may be developed across the crystal.
solution
V 2
Power dissipated = P= ——
where V is an rms voltage.
V= (PR )' /2 = ( 10 X 10" 3 X 625) l/2 = (6.25) 1/2 - 2.5 V
and peak-to-peak volts is 2 X 1 .4 1 4 X Vrms = 7.07 V.
Piezoelectric crystals cut from quartz and other natural materials are
limited to a few shapes. This is a disadvantage because it limits the
applications of natural crystals. Synthetic piezoelectric devices can be
manufactured in almost any desired shape. Although they are generally
unsuitable for such applications as oscillator stabilization, they can be used
in other situations where quartz crystals are not appropriate.
The manufacture of synthetic piezoelectric devices involves pressing a
ceramic powder, such as barium titanate , into required shapes, and then firing
it in a high-temperature oven. During the firing process the material is
421
Synthetic
Piezoelectric
Devices
Example 19-1
19-3
Synthetic
Piezoelectric
Devices
422
Miscellaneous
Devices
Plated
electrodes
Plated
electrodes
(a) Cylindrical transducer
(b) Bimorph
Figure 19-9. Ceramic piezoelectric transducers.
subjected to a high direct voltage. This has the effect of polarizing or aligning
the atomic groups within the material into a pattern which can produce a
piezoelectric effect. The finished devices generate an electrical output when
the mechanical faces are distorted, and produce movement at the mechani-
cal faces when an electrical potential is applied.
Two types of synthetic piezoelectric transducers are illustrated in Fig.
19-9. Figure 19-9(a) shows a cylindrical-shaped ceramic device with electri-
cal contacts plated on each end. This kind of transducer is frequently used
for listening to sea noises. A preamplifier is inserted inside, the cylinder is
sealed at each end, and it is then suspended at the end of a long cable from
a buoy or a boat at the surface. Every noise (ship engines and the like)
causes a change in pressure on the sides of the transducer. The pressure
variations in turn produce electrical signals at the device terminals. These
are amplified and fed to the surface for conversion back to audio signals.
Figure 19-9(b) shows a ceramic device known as a multimorph. When
supported at one end, electrical signals are generated at the internal and
external electrodes by vibrations picked up at the other end. This device is
basic to a record-player cartridge. The minute vibrations generated as the
stylus moves in the record track are converted into electrical signals, and
then amplified and fed to speakers.
19-4
Voltage-
Variable
Capacitor
Diodes
Voltage-variable capacitor diodes (WC’s) are also known as varicaps, varac-
tors, and epicaps, as well as by several trade names. Basically, a WC is
simply a reverse-biased diode, and its capacitance is that of the junction
depletion region. Recall that the width of the depletion region at a /w-junc-
tion depends upon the reverse-bias voltage [Fig. 19- 10(a)]. A large reverse
bias produces a wide depletion region, and with a small reverse bias the
Large reverse bias
Small reverse bias
Conducting
plates
—•I —
Reverse bias
Depletion region
width
-o
(a) Principle of voltage variable capacitance diode (b) Circuit symbol
Figure 19*10. Principle of operation and circuit symbol for voltage-variable capacitor
diode.
423
Voltage-
Variable
Capacitor
Diodes
depletion region tends to be very narrow. Since the depletion region acts as a
dielectric between two conducting plates, the device has the characteristics
of a capacitor. As with all capacitors, the depletion layer capacitance (C^) is
proportional to the junction area and inversely proportional to the width of
the depletion region. Since the depiction region width is proportional to the
reverse-bias voltage, C ^ is inversely proportional to the reverse-bias voltage.
This is not a direct proportionality, oc 1 / V n , where V is reverse bias
voltage and n depends upon doping density. The circuit symbol for a WC
diode is shown in Fig. 19- 10(b).
Figure 19- 11 (a) shows the equivalent circuit for a WC diode. Cj is
the junction capacitance shunted by Rj (the junction reverse leakage resistance).
R , represents the resistance of the semiconductor material, L t is the package
inductance, and C c is the capacitance of the package. L t is normally very
small and Rj is very large, so for most purposes the equivalent circuit can be
simplified to that of Fig. 19-1 1(b). In this case the diode capacitance is
C T — Cj + C c . Qfactors for the device can be as high as 600 at a frequency of
50 MHz. However, since the () varies with bias voltage and frequency, it can
be used only as a figure of merit for comparing the performance of different
WC’s.
A wide selection of device nominal capacitances is available, ranging
from 6 to 550 pF. The capacitance tuning ratio TR is the ratio of C T at a small
reverse voltage to C T at a large reverse voltage. Depending upon the doping
profile of the device, TR may be as small as 2 or as large as 15. Figure 19-12
shows the doping profiles for an abrupt junction diode and for a hyperabrupt
o-
(a) Equivalent circuit
o
*S
-AAAAr
C T
-o
(b) Simplified equivalent circuit
Figure 19-11. Equivalent circuits for voltage-variable capacitor diode.
Abrupt change
from constant
density of p to
constant density
of n
P
Density
Density
(a) Abrupt junction
(b) Hyperabrupt junction
Figure 19-12. Doping profile at abrupt and hyperabrupt junction.
424
junction device. For the abrupt junction doping profile, the semiconductor
material is uniformly doped and changes abruptly from p - type to n-type at
the junction. In the case of the hyperabrupt junction, the doping density is
increased close to the junction. This increased density makes the depletion
region narrower and consequently produces a larger value of junction
capacitance. It also causes the depletion region width to be more sensitive to
bias voltage variations, and thus it produces the largest values of TR. Figure
19-13 shows typical graphs of diode capacitance plotted against reverse bias
for abrupt and hyperabrupt junction devices.
The major application of WC diodes is as tuning capacitors to adjust
the frequency of resonance circuits. An example of this is the circuit shown
in Fig. 19- 14, which is an amplifer with a tuned circuit load. The amplifier
produces an output at the resonance frequency of the tuned circuit. Since
the WC diode provides the capacitance of the circuit, and since C T can be
altered by adjusting the diode bias, the resonance frequency of the circuit
can be varied. C c is a coupling capacitor with a value much larger than that
of the WC diode.
425
Voltage-
Variable
Capacitor
Diodes
Calculate the capacitance tuning ratio (TR) at 1 V and 10 V for the Example 19-2
abrupt junction and hyperabrupt junction devices with the characteristics in
Fig. 19-13.
pF
Figure 19-13. Capacitance-voltage characteristics for abrupt and hyperabrupt junction
devices.
426
Miscellaneous
Devices
Example 19-3
Figure 19-14. Amplifier with WC diode frequency control.
solution
From the abrupt junction device characteristics in Fig. 19-13,
At IV, Ctel50pF
At 10 V, Css60pF
For the abrupt junction device,
TR(,v- 1 av) = f =2^
From the hyperabrupt junction device characteristics in Fig. 19-13,
Atl V,C«220pF
At 10 V, C«15pF
For the hyperabrupt junction device,
TR(iv- v)“ W =
For the circuit of Fig. 19-14, 1^ = 9 V, L = 100 pH, /?, =4.7 kQ,
R 2 = 10 k£2, and Z), is a hyperabrupt junction WC diode with the char-
acteristic shown in Fig. 19-13. Calculate the maximum and minimum
resonance frequency for the drcuit.
solution
and
K,
R, + R 2 XVoc 4.7kQ+10kQ
4.7k£2
X9V=2.9V
From the hyperabrupt device characteristics in Fig. 19-13,
427
Thermistors
At V= 2.9 V CaslOO pF At V=9 V, 15 pF
At resonance,
2^rfL = \/2vfC,
2tt (LC) ,/2
For V ni
257(100X 10" 6 X 100X 10" ,2 ) ,/2
si. 6 MHz
For V n ,
/= %4.1 MHz
2t7(100X 10~ 6 X 15X 10" ,2 ) ,/2
The resonance frequency range is 1.6 to 4.1 MHz.
The word thermistor is a combination of thermal and resistor. A thermistor
is a resistor with definite thermal characteristics. Most thermistors have a
negative temperature coefficient (NTC), but positive temperature coefficient (PTC)
devices are also available. Thermistors are widely applied for temperature
compensation , i.e., canceling the effects of temperature on other electronic
devices. They are also employed for measurement and control of tempera-
ture, liquid level, gas flow, etc.
Silicon and germanium are not normally used for thermistor manufac-
ture, because larger and more predictable temperature coefficients are
available with metallic oxides. Various mixtures of manganese, nickel,
cobalt, copper, iron, and uranium are pressed into desired shapes and
sintered (or baked) at high temperature to form thermistors. Electrical
connections are made either by including fine wires during the shaping
process or by silvering the surfaces after sintering. Thermistors arc made in
the shape of beads, probes, discs, washers, etc. (Fig. 19-15). Beads may be
glass coated or enclosed in evacuated or gas-filled envelopes for protection
against corrosion. Washer-shaped thermistors can be bolted together for
series or parallel connection. Tiny thin-film thermistors, formed by sintering
metal oxide coatings onto a ceramic or foil substrate, are also available.
A typical thermistor resistance- temperature characteristic is shown in
Fig. 19-16. It is seen that the device resistance decreases by approximately
19-5
Thermistors
428
Miscellaneous
Devices
Figure 19-15. Some typical thermistor shapes.
500 times when heated through 150°C. Current through a thermistor causes
power dissipation which raises the device temperature. Thus, the device
resistance is dependent upon ambient temperature and self-heating. For a
fixed ambient temperature the thermistor resistance is dependent upon its
own power dissipation. Very small currents have no effect, so that a plot of
voltage versus current (Fig. 19-17) shows the device behaving initially as a
constant value resistance. As the current increases a peak is reached at
which the heating effect of the current begins to significantly change the
thermistor resistance. Further increase in current causes a progressive reduc-
tion in reistance, and consequently produces a reduction in voltage across
the device.
Example 19-4
A thermistor with the resistance-temperature characteristic in Fig.
19-16 is employed in the circuit of Fig. 19-18. The relay coil has a
resistance of 5 kO at — 15°C, and 6.5 kfl at 50°C. If the relay is energized by
a current of 1 mA, calculate the required value of R x at — 15°C and
50°C(a) with the thermistor and R 2 not in circuit; (b) with the thermistor in
circuit; (c) with the thermistor and R 2 in the circuit.
solution
(a) Without the thermistor and R 2i
R x + R c
\o 7 10 6 io ~ 5 10 4 10 - 3 10 7 a
/ ~
Figure 19-17. Static voltage-current characteristic for thermistor.
n
10,000
4
3
2
4
3
Resistance 2
100
4
3
2
10
4
3
2
1.0
\
1
1
—
„ .
r
!
1
'
I
1
1
H
• -i
1
■
—
r
1
. .
1 —
; j
-40 -20 0 20 40 60 80 100 120 °C
Temperature
Figure 19-16. Typical resistance-temperature characteristic for thermistor.
Power dissipation
Resistance
429
430
Miscellaneous
Devices
*2
Figure 19-18. Thermistor compensation of relay circuit.
at — 15° C
20 V
R. = - — --5kS2 = 15kfl
1 mA
at50°C
20 V
R . = - 6.5 kfi = 1 3.5 kS2
1 mA
(b) With the thermistor,
7 £
R { + R t + R c
7?i = — — R t —R c
From Fig. 19-16, R r = 3 kfl at -15°C and 100 8 at 50°C.
at — 15° C
20 V
/?. = -p4-3kfl-5 kG = 12kfl
1 mA
at50°C
- 100 fl-6.5 kS2 = 13.4 kfl
1 mA
(c) With R 2 and the thermistor,
/ £
R,-j-(Rt\\Ri)-Rc
431
Thermistors
Meter
(a) Temperature measurement
Figure 19-19. Other thermistor applications.
at — 15° C
at 50° C
R l = - — - - (3 kfi||3 kfl) - 5 kSl = 1 3.5 kti
1mA
20 V
/?, = -p— - (3 kfl || 1 00 G) - 6.5 kft = 1 3.4 kfi
1 mA
From Example 19-4 we see that, without the thermistor in circuit, /?,
must be reduced from 15 to 13.5 kfi when the ambient temperature is
increased from — 15° to 50°G. This is necessary to allow the 1 mA
energizing current to flow through the relay coil. With the unshunted
thermistor in circuit, /?j must be increased from 12 to 13.4 kfl when the
temperature goes from — 15° to 50°G. This means that the thermistor is
overcompensating for the change in coil resistance. Finally, when the thermistor
and 3 ktt shunt are included in the circuit, virtually no adjustment of R x is
necessary at the temperature extremes. Thus, the shunted thermistor com-
pletely compensates for the coil resistance change with temperature. Two
points should be noted about Example 19-4 . One is that only the tempera-
ture extremes were looked at, and obviously the adequacy of compensation
between the extremes should be considered. The other point is that the
heating effect of current through the thermistor was assumed negligible.
Other thermistor applications are illustrated in Fig. 19-19.
19-6
Lambda
Diode
The lambda diode is a device which has characteristics similar to those of
a tunnel diode. However, the typical bias voltage required by a lambda
diode is not so inconveniently small as that needed for a tunnel diode.
A lambda diode is simply two complementary FET’s connected as
shown in Fig. 19-20(a). ( Complementary transistors are two transistors which
have similar parameters but are of different types. For bipolar transistors one
would be a pnp type and the other an npn. For FET’s one is an n-channel
device and the other is a /^-channel FET.)
<
> Anode
u
IP" "
> Cathode
<
(a) Two FETs connected as a lambda diode
(b) Forward characteristics
Figure 19-20. Circuit and characteristics of a lambda diode.
432
Note in Fig. 19-20(a) that the gate of each FET is connected to the 433
source terminal of the other transistor. Note also that the two drain termi- Glossary of
nals are connected together, and that the source of the n-channel device is lmP Terms
the anode of the lambda diode while the source of the /^-channel FET is its
cathode. Figure 19-20(c) shows typical characteristics for the lambda diode.
To understand the device characteristics, consider the situation when a
small voltage (say, 0.5 V) is applied, positive to the anode, negative to the
cathode. The gate of (), is —0.5 V with respect to its source. This is not a
large enough gate-channel reverse bias to turn the device off. Similarly, the
gate of Q 2 > the />-channel FET, is 0.5 V positive with respect to £> 2 ’s source.
Again, this is a reverse bias at the gate-channel junction, but not large
enough to bias the FET off. Under these conditions both transistors are
conducting. Consequently, when the lambda diode forward-bias voltage is
increased from zero through 0.5 V, the current flowing increases in propor-
tion to the applied voltage.
As the forward-bias voltage of the lambda diode is increased, the
reverse bias at the gate-channel junction of each FET also increases.
Eventually, the reverse-bias voltage becomes large enough to begin to turn
each device off (depletion region penetration; see Section 12-2). The point at
which the reverse-bias voltage becomes effective is the point on the char-
acteristic at which the current is a peak. As the lambda diode forward
voltage is increased beyond this point, the FET channels are narrowed and
the current falls steadily to a very low (drain-source leakage) level. With
both FET’s biased off, further increases in (forward) voltage have no effect.
At some high voltage level device breakdown would occur, of course.
When a reverse-bias voltage is applied to the lambda diode, the gate of
the n-channel, FET is always positive with respect to its channel, and the
/^-channel FET always has its gate biased negative with respect to the
channel. Consequently, neither FET can become biased off with this voltage
polarity. The reverse characteristic is, therefore, that of a resistance equal to
the sum of FET channel resistances.
Like the tunnel diode, the negative resistance of the lambda diode
allows it to be used as a parallel or series amplifier and in oscillator and
switching circuits. The voltage required to bias the lambda diode into its
negative resistance region is typically 2 to 3 V, compared to about 200 mV
for the tunnel diode. This makes the lambda diode easier to use in a
laboratory situation.
Piezoelectric crystal. Crystal which generates a voltage when pressed, and Glossary of
distorts when a voltage is applied to its surface. Important
Rochelle salt, tourmaline, quartz. Natural materials which have piezoe-
lectric properties.
Optical axis (Z axis). Axis of quartz crystal at which no piezoelectric effect
is exhibited.
Electrical axis ( X axis). Crystal axis at which a voltage appears when
mechanical stress is applied at the mechanical axis.
434
Miscellaneous
Devices
Mechanical axis ( Y axis). Crystal axis at which a mechanical stress causes
a voltage to be generated at the electrical axis.
A”-cut. Crystal section cut with its flat sides perpendicular to the electrical
axis.
F-cut. Crystal cut with its flat sides perpendicular to the mechanical axis.
GT- cut. Flat rectangular section cut from crystal at a particular angle to
the various axes to give zero temperature coefficient.
Ring-shaped cut. Crystal cut in ring shape, and at a particular angle to
the various axes to give zero temperature coefficient.
Series resonance frequency. Frequency at which crystal series capacitive
reactance and inductive reactance are equal. Frequency at which
crystal impedance is a minimum.
Parallel resonance frequency. Frequency at which the capacitance of the
crystal electrodes resonates with reactance of the crystal circuit.
Frequency at which crystal impedance is a maximum.
Q factor. Ratio of reactance to resistance for a resonant circuit.
Overtone operation. Operation of crystal to control a circuit which is
resonating at a frequency which is a multiple of the crystal frequency.
Crystal oven. Insulated crystal enclosure in which the temperature is
thermostatically controlled in order to stabilize the crystal frequency.
Synthetic piezoelectric device. Ceramic device which exhibits piezo-
electric characteristics.
WC diode. Variable- voltage capacitance diode. Diode in which junction
capacitance is controlled by reverse-bias voltage.
Varicap, varactor, epicap. Other names for a WC diode.
Capacitance timing ratio. Ratio of WC diode capacitance at a small
reverse voltage to that at a large reverse voltage.
Doping profile. Graph showing doping density at a /w-junction.
Abrupt junction. /^-Junction at which uniform doping density changes
abruptly from p - type to n-type.
Hyperabrupt junction. /w-Junction at which doping density increases near
the junction, and changes abruptly from p - type to n-type.
Thermistor. Device which exhibits a large resistance change with tempera-
ture change.
Lambda diode. Two field effect transistors connected to simulate the
performance of a tunnel diode.
Review
Questions
19-1. Sketch a flat plan diagram to show the arrangement of atoms within
a piezoelectric crystal. Identify the electrical axis and the mechanical
axis, and show how a mechanical stress can cause voltage generation,
and how an applied potential can produce crystal distortion.
19-2. (a) Sketch the approximate shape of a natural crystal, and identify
each axis by name and symbol, (b) Draw sketches to illustrate A'-cut,
K-cut, GT-cut, and ring-shaped crystal cut. Briefly explain.
19-3. (a) Sketch the equivalent circuit of a piezoelectric crystal and explain
the origin of each component, (b) Draw a sketch of a typical
impedance- frequency graph for a piezoelectric crystal. Identify and
explain each of the two resonance frequencies.
19-4. (a) Explain the Q factor and compare the Q, factor of a crystal to that
of an ordinary electrical resonant circuit, (b) Describe how greatest
possible crystal frequency stability is achieved, (c) Define overtone
operation of a crystal.
19-5. Sketch two crystal-controlled oscillator circuits, one using a crystal in
parallel resonance, and the other using a series resonant crystal.
Explain the operation of each circuit. Also state two important
considerations for using crystals.
19-6. Discuss the manufacture and applications of synthetic piezoelectric
devices.
19-7. (a) Using illustrations, explain the operation of a WC diode.
(b) Sketch the equivalent circuit for a WC diode. Explain the origin
of each component and show how the circuit may be simplified.
19-8. (a) Explain the difference between abrupt and hyperabrupt junction
WC diodes. Draw sketches to illustrate the differences, (b) Sketch
typical capacitance-voltage characteristics for abrupt junction and
hyperabrupt junction devices, (c) Sketch a circuit to show an applica-
tion of a WC diode.
19-9. (a) Describe the performance of a thermistor and explain its con-
struction. (b) Sketch typical resistance-temperature and voltage-cur-
rent characteristics for a thermistor. Briefly explain.
19-10. Sketch circuit diagrams to show applications of thermistors to (a)
compensation of a relay circuit, (b) liquid level detection, (c) temper-
ature measurement. Briefly explain the operation of each circuit.
Draw a diagram to show how a NTC thermistor might be used to
compensate for Vre variations (due to temperature change) in an
emitter current biased transistor circuit.
19-11. Sketch a diagram to show the construction of a lambda diode. Also
sketch typical forward characteristics for the device. Explain the
operation of the device and the shape of the characteristics. What
would the reverse characteristics of this device look like? Briefly
explain.
19-1. A crystal with a resistance of 7 k£2 has a specified maximum drive
power of 2 mW. Determine the pcak-to-peak ac voltage that may be
developed across the crystal.
435
Problems
Problems
436
Miscellaneous
Devices
19-2. Examine each of the oscillator circuits in Figs. 10-1 through 10-6.
Describe how piezoelectric crystals might be employed in every
circuit to stabilize the output frequency. Also estimate the crystal
power dissipation in each case.
19-3. Calculate the capacitance tuning ratio (TR) at 2 V and 8 V for the
abrupt junction and hyperabrupt junction devices with the character-
istics in Fig. 19-13.
19-4. The frequency-controlled circuit in Fig. 19-14 has V cc = 20 V, L = 80
jiH, /?j =3.3 left, R 2 = 20 kft, and Z>j is an abrupt junction device with
the characteristics in Fig. 19-13. Determine the maximum and
minimum resonance frequencies for the circuit.
19-5. The circuit shown in Fig. 19- 19(a) uses a 1.5 V battery and a 1 mA
meter. The thermistor used has the resistance-temperature character-
istics in Fig. 19-16. Calculate the value of the variable resistance if
the meter is to read full scale when the tempeature is 80 °C. Assuming
that the variable resistance remains unaltered, calculate the meter
readings for temperatures of 50°, 20°, and — 10°C.
19-6. A relay coil has a resistance of 3.3 kft at — 15°C and 5 kft at 80°C.
The relay is energized by a current of 0.5 mA from a 10 V supply in
series with a resistance R v A thermistor is to be connected in series
with the relay and /?, to provide temperature compensation:
(a) Sketch the circuit and calculate the required value of /? x at — 15°
and at 80°C.
(b) If the thermistor is included and has the characteristic shown in
Fig. 19-16, calculate the new values for R i at — 15° and 80°C.
(c) With the thermistor shunted by a 4.1 kft resistance, again
calculate the required values of R x at — 15° and 80°C.
Electron Tubes
Electrons can be made to travel through a metallic crystal. ITiey can
also be made to travel through a vacuum. In the vacuum diode , two electrodes
are contained in a glass envelope from which the air has been evacuated.
One of the electrodes, termed the cathode , is heated electrically, so that it
emits electrons. The other electrode, known as the plate or anode , is main-
tained at a positive potential with respect to the cathode. Since electrons arc
negatively charged they are attracted toward the plate, so that a current
flows (in the conventional direction) from the positive plate to the negative
cathode. If the plate potential is reduced to zero or reversed, the current is
cut off. Additional electrodes introduced between the plate and cathcxlc
afford control over the plate current and create a wide range of multiclcc-
trodc tubes.
CHAPTER
20
20-1
Introduction
437
20-2
The
Vacuum
Diode
20 - 2.1
Construction
Vacuum diodes are usually constructed with the plate in the form of a
cylinder and with the cathode at the center of the plate (Fig. 20-1). The
cathode may be a simple filament of tungsten or tkoriatcd tungsten. Alterna-
tively, it may be a nickel tube coated with barium oxide or strontium oxide , and
heated by an insulated filament. The greatest emission efficiencies are availa-
ble with oxide-coated cathodes, but filament cathodes are toughest.
In low power tubes the plate is usually nickel or iron. For high-power
tubes, tantalum , molybdenum , or graphite may be used, because they do not
deteriorate as rapidly as iron or nickel at high temperatures. For high-volt-
age tubes, the plate voltage limit is determined by the insulation resistance
between electrodes, rather than by the tube dissipation. For this reason, the
plate terminal is frequently at the opposite end of the tube from the other
terminals.
20 - 2.2 Typical vacuum diode characteristics are shown plotted in Fig. 20-2.
Diode When the plate voltage {Ef) is zero, very few of the electrons emitted from the
Characteristics cathode are attracted to the plate. Hence the plate current {If) is near zero.
When E p is increased positively from zero, the plate attracts electrons from
the cathode. Initially only a small quantity of the electrons flows from
cathode to plate. As the plate voltage increases, more and more electrons
flow to it until there is almost a linear increase of plate current with increase
Nickel tube
with oxide-coated
surface
Heating filament
(c) Oxide-coated cathode
Figure 20-1. Vacuum diode construction and circuit symbol.
438
flow to it until there is almost a linear increase of plate current with increase
in plate voltage. With a continued increase in plate voltage, the plate
current eventually reaches a saturation level. At this point all available
electrons from the cathode are being drawn to the plate. Further increase in
E p produces only a slight increase in I p . If the cathode temperature is
increased, more electrons are emitted and I p is raised to a new saturation
level, (T 2 in Fig. 20-2).
There are two major regions of the diode characteristics, the space-
charge limited region , and the temperature- limited region. The diode is operating in
its space-charge limited region when more electrons are being produced at
the cathode than are being drawn to the plate. In this condition the plate
current is dependent on the plate-to-cathode voltage. In the temperature-
limited region, the plate potential is so great that all the electrons produced
at the cathode are being drawn to the plate.
In the space-charge limited region, there is always a cloud of emitted
electrons around the cathode (because more electrons are emitted than are
drawn to the anode). Positive ions , which are formed by electron collision with
gas molecules, are accelerated toward the cathode, but enter the electron
cloud and become neutralized by recombining with electrons. When operat-
ing in the temperature-limited region, there is no protective cloud of
electrons around the cathode, so positive ions can strike the cathode and
seriously damage the oxide coating. For this reason, electron tubes are
normally operated in the space-charge limited region.
439
The Vacuum
Diode
Space charge Temperature
Plate voltage
Figure 20-2. Vacuum diode characteristics
20-2.3
Vacuum
Diode
Applications
Example 20-1
Like the semiconductor diode, the vacuum diode is a one-way device.
Therefore, its applications are essentially the same as the semiconductor
diode applications described in Chapter 3. The vacuum diode has the
disadvantage that its operating plate-to-cathode voltage is typically 5 to
30 V (or greater). The semiconductor diode, by contrast, has an approxi-
mately 1 V drop across it when operating. Also, the vacuum diode requires
an additional supply for the cathode heater. When the added disadvantage
of the vacuum diode’s greater physical size is considered, it is seen that there
is no vacuum diode function that cannot be more conveniently performed by
a semiconductor diode.
A vacuum diode with the characteristic shown in Fig. 20-3 is con-
nected in series with a supply of 100 V and a load resistance of 4 kfl. Draw
the dc load line for the circuit and determine the value of plate current and
plate voltage.
mA
Figure 20-3. Vacuum diode characteristics and dc load line.
solution
The circuit is as shown in Fig. 20-4. From the circuit,
E=E p + I p R L
When /, = 0, E = E p +0.
E p = 100 V
440
Figure 20-4. Vacuum diode with series load.
Plot point A on the characteristic at I p — 0, E p = 1 00 V.
When £, = 0, E=0+I p R t .
100
4kft
= 25 mA
Plot point B at E p = 0, I p = 25 mA.
Draw the dc load line between points A and B.
From the intersection of the load line and the characteristic at point Q,, read
/,= 17 mA and £, = 32 V.
Consider the effect of placing a wire grid in the electron tube between
the cathode and the plate. When the grid is biased to a large negative
voltage with respect to the cathode, all electrons are repelled by it so that no
electrons are permitted to pass from the cathode to the plate. When the grid
is made only slightly negative with respect to the cathode, many electrons
are able to pass through the grid wires to the plate. Thus, by varying the
grid potential the plate current is increased, decreased, or switched off
completely.
If the grid is made positive with respect to the cathode, electrons are
attracted to it, and a grid current will flow. Since this is a condition to be
avoided, the grid is always maintained at a negative voltage with respect to
the cathode. With the addition of the grid the tube becomes a vacuum inode.
The construction and the schematic symbol employed for a vacuum
triode are illustrated in Fig. 20-5. The cathode and plate are normally of the
same type of construction as for a diode tube. The grid is usually a nickel
wire, spiral wound around two support posts. In some modern miniature
441
The Vacuum
Triode
20-3
The Vacuum
Triode
20 - 3.1
Grid Effect
20 - 3.2
Construction
442
Electron
Tubes
Gas envelope
Plate
Grid
Cathode
Plate
(b) Circuit symbol
Figure 20-5. Triode construction and circuit symbol.
tubes, the grid is a self-supporting wire mesh. The connections for grid,
plate, cathode, and cathode heaters are usually brought out at the base of
the tube.
20-4
Triode
Characteristics
20 - 4.1
Plate
Characteristics
When the grid of a triode is maintained at the same potential as the
cathode, the triode plate characteristics are similar to those of a diode. Thus,
in Fig. 20-6 the triode I p / E p characteristic for is g = 0 is exactly as would be
expected from a diode tube operating in the space-charge limited region. If
E p is increased further, the temperature-limited region will eventually be
reached.
When the grid is made 1 V negative with respect to the cathode
(E g = — 1 V), then the I p / E p characteristic is significantly altered from that
for £^=0. This is because the grid at— 1 V constitutes a large negative
barrier for electrons to cross before they can pass from cathode to plate.
Therefore, the plate current does not commence when E p is around zero
volts; instead, E p has to be made substantially greater than zero before any
plate current will flow. Also, at each subsequent level of E p , the plate current
is less than when E g = 0. The effect is that of the E g = 0 characteristic being
moved to the right. This is illustrated by the E ' — — 1 V characteristic in Fig.
20 - 6 .
When the negative bias on the grid is greater than 1 V, the plate
characteristic is moved even farther to the right. Thus, using various values
of grid voltage, a family of l p / E p characteristics can be obtained as shown in
the figure. If the grid is made positive with respect to the cathode, the
Figure 20-6. Typical plate characteristics for a vacuum triode.
characteristics are as shown by the broken lines in Fig. 20-6. In this case,
electrons are being collected by the positive grid, and grid current is flowing.
This is a condition normally avoided.
We have already seen that the plate current can be controlled by
variation of the grid voltage. If the plate voltage is held constant and the
plate current values are recorded for each setting of grid voltage, the
transconductance characteristic or transfer characteristic is obtained (Fig. 20-7).
Referring to Fig. 20-7, it is seen that, for £^,= 100 V and E g = 0 V,
L — 28 mA. If E ' is held constant at 100 V and E ' is altered to — 1 V, L will
P P e P
be reduced because the negative grid will retard the flow of electrons from
cathode to plate. A further alteration of E g to more negative levels (with E p
maintained at 100 V) will further decrease l p . Using a new constant value of
E p , new levels of l p are obtained for each — E g setting. Thus, using different
E p voltages a family of transconductancc characteristics can be plotted.
These characteristics are obtained by keeping I p at a fixed level, and
plotting grid voltage (£^) versus plate voltage ( E p ) (Fig. 20-8).
From any one set of characteristics the other two may be derived.
Consider the plate characteristics shown on Fig. 20-6. If a horizontal line is
drawn at 7^ = 10 mA, then at the intersection of the line and each E p f l p
443
Triode
Characteristics
20-4.2
Trans-
con ductance
Characteristics
20-4.3
Constant
Current
Characteristics
20-4.4
Relationships
Between
Characteristics
444
Electron
Tubes
30
mA
V -3
-2
- 1
0
Figure 20-7. Typical transconductance characteristics for a vacuum triode.
graph the corresponding values of E g and E p can be read. Hence, the grid
voltage values can be plotted against the plate voltage values to obtain the
constant current characteristic for l p = 1 0 mA.
Similarly, if a vertical line is drawn representing a constant value of
plate voltage, then the corresponding values of E g and I p can be read where
the line cuts each graph (see Fig. 20-6). From these readings the transcon-
ductance characteristics can be plotted for the plate voltage selected. By a
similar method, either of the other two sets of characteristics may be used to
produce all three sets of characteristics.
0
50
100
150 V
Figure 20-8. Typical constant current characteristics for vacuum triode.
From the plate characteristics shown in Fig. 20-6 derive Example 20-2
(a) The transconductance characteristic for E p = 75 V.
(b) The constant current characteristic for I p = 10 mA.
solution (a)
Draw a vertical line at E p = lb V on the plate characteristics (Fig. 20-6).
Where the line cuts each characteristic, read the corresponding plate current
and grid voltage values:
‘p
20 mA
10mA
2 mA
E !
0 V
-1 V
-2 V
Plot the above values at points 1, 2, and 3 on Fig. 20-7. Join the points
together to draw the transconductance characteristic for E p = 75 V.
solution (b)
Draw a horizontal line at I p — 10 mA on the plate characteristics (Fig. 20-6).
Where the line cuts each characteristic, read the corresponding plate voltage
and grid voltage values:
E S
0 V
-IV
-2 V
-3 V
E P
45 V
75 V
105 V
132 V
Plot the above values at points 1, 2, 3, and 4 on Fig. 20-8. Join the
points together to draw the constant current characteristic for l p = 10 mA.
20-5
Triode
Parameters
Consider the plate characteristics shown in Fig. 20-9(a). The reciprocal
of the slope of the E g = 0 characteristic at E p = 75 V is
(a resistance) = r p
From the characteristic
30 V
10 mA
3kft
( 20 - 1 )
The plate resistance is the resistance offered by the vacuum tube to plate
voltage variations when the grid voltage is held constant. Thus, if E g is held
20-5.1
Plate
Resistance
( r p>
445
446
Electron
Tubes
(a) Plate characteristics
£> — -
Figure 20-9. Derivation of parameters from triode characteristics.
constant at 0 V and E p is varied by 30 V, I p would be altered by
A£ J& /r J& = 30V/3 kO =10 mA. Typical values of r p range from 250 Q, to 70
k £1
20 - 5.2
Transcon-
ductance (g m )
From the characteristic, £ m =(10X 10~ 3 )/1 =0.01 S, or£ m = 10 mA/V.
The transconductance (g m ) is a measure of the grid voltage control over
plate current when the plate voltage is held constant. For the g m value
From the transconductance characteristics on Fig. 20-9(b) the slope of
the 2?^ = 1 00 V characteristic at E g = 1 V is
A/
— — = (a conductance) = g m
A h 0
( 20 - 2 )
calculated above, each 1 V variation in E g will cause I p to be altered by 447
10 mA. Typical values of g m range from 1 to 10 mA/V. ^olthod”
Electron emission from the cathode of a vacuum tube decreases as the Circuit
tube approaches the end of its useful life. This causes a decrease in the value
of g m for the tube. Thus g m is useful as an indication of how good a vacuum
tube is (i.e., it is a figure of merit).
From the constant current characteristics of Fig. 20-9(c), the slope of
the l p = 20 mA characteristic at E g = — 1 V is
^ i
= (a ratio) = p.
(20-3)
20-5.3
Amplification
Factor ( /i)
From the characteristic
The amplification factor ( \l) is a measure of the relative effectiveness of
plate voltage and grid voltage as controllers of the plate current. From the
characteristics it is seen that a variation in E g of 1 V will change I p by
10 mA when E p remains constant. To achieve the same variation in I p with
E g held constant requires E p to be changed by 30 V. Thus, E g is p times as
effective as E p in controlling l p {\i = 30 in this case). Typical values of /i
range from 2.5 to 100.
The following formula manipulation shows the relationship between [i ,
g m y and r p . The expression for ft is multiplied by Al p /AI py which is the same
as multiplying by 1.
A E f A E ( A/, A/, A E,
JL
Sm
where g m is in A / V y not mA/V
20-5.4
Relationship
Between
Parameters
20-6
Common
Cathode
Circuit
The three major circuit configurations that may be used with electron
tubes are common cathode , common plate , and common gnd. The common cathode
circuit is shown schematically in Fig. 20-10.
20 - 6.1
Circuit
Configuration
448
Electron
Tubes
It can be seen from the circuit that the grid of the triode is biased
negatively with respect to the cathode. The resistance R g is referred to as the
grid leak , and its function is to connect the bias voltage to the grid so that
input signals are not short circuited by E g . Since no grid current flows, the
signal “sees” an input resistance equal to R g . R g is typically 1 Mft, and if it is
made too large electrons may accumulate on the grid and alter the bias
voltage. Therefore, another function of R g is to “leak” electrons off the grid.
The input signal is applied via Cj to the grid, and the output voltage is
developed across the load R L . The plate current flows through the load
resistor R L , so that
E p ~ Epp
20 - 6.2
DC Load
Line
Using the above equation, the dc load line may be drawn on the plate
characteristics. Take R L = 10 kS2 and £^, = 200 V. When I p = 0,
£ =£ -0 = 200 V
p PP
I p — 0 and E p = 200 V are plotted to obtain one point on the dc load
line, point A on Fig. 20-11. When £^, = 0,
E p 200 V
R l ~ 10 kS2
= 20 mA
£^ = 0 and I p — 20 mA are plotted to obtain point B on the characteristics.
The dc load line is drawn by joining these two points together as shown.
This is the load line for R L = 10 kS2 and £^, = 200 V. If either R L or Epp is
altered, a new load line must be drawn.
Figure 20-11. DC load line for triode amplifier.
Let the circuit be biased to point Q, on the dc load line. At point (),
E g — — 2 V, l p cz. 9.5 mA, and E p = 105. If E g is now altered to zero volts, I p
becomes 13.5 mA and E p becomes 65 V. Therefore, a change of +2 V at the
grid has produced a 4-4 mA change in I p and a —40 V change in
/^.Similarly, when E g is changed from —2 to — 4V, I p changes from 9.5 to
5.5 mA and E p changes from 105 to 145 V. Thus, a —2 V change in E g
produces a —4 mA change in I p and a +40 V change in E p . Therefore, a
signal of ± 2 V produces an output voltage of ± 40 V, so that a voltage gain
in this case equal to 20 is obtained. Also, I p increases when E g is increased
(positively) and decreases when E g is decreased. So I p changes in phase with
the grid signal voltage. E p , on the other hand, decreases when E g is increased
(positively), and increases when E g decreases. Therefore, the output voltage
of the common cathode amplifier is antiphase to the input voltage.
The grid voltage variations discussed above could be produced by an
ac signal coupled via capacitor C, in Fig. 20-10. From the point of view of
the ac performance of the circuit, the actual dc bias and supply voltages can
be regarded as short circuits. Redrawing the circuit to include the signal
voltage e s , and with E g and shorted out, gives the ac equivalent circuit
shown in Fig. 20- 12(a). From the ac equivalent circuit it is seen that the
input signal e t is applied between the grid and cathode terminals of the tube.
449
AC Analysis
of Common
Cathode
Circuit
20 - 6.3
Amplification
20-7
AC Analysis
of Common
Cathode
Circuit
450
Electron
Tubes
(a) dc voltages become ac short circuits
(b) Vacuum tube becomes voltage generator of
voltage - pe s and internal resistance r p
Figure 20-12. Developing ac equivalent circuit for common cathode amplifier.
Also, the output voltage V 0 is derived across the plate and cathode terminals.
The cathode terminal is common to both input and output, hence the circuit
name common cathode.
In the ac equivalent circuit the vacuum tube may be replaced by a
voltage source of — \u s volts. The ac internal resistance of the vacuum triode
is the plate resistance r p . Therefore, the voltage source representing the tube
must have an internal resistance of r p . The complete ac equivalent circuit is
now the voltage equivalent circuit shown in Fig. 20- 12(b).
From the voltage equivalent circuit it is seen that — fie s is potentially
divided across r p and R L to produce the output voltage V 0 . Therefore,
K =-/«,x
«L
r p + R L
The voltage gain
A F °
" <•, r p + R L
(20-5)
Using typical values of p = 30, r^ = 5 kS2, and R L = 10 k ft,
451
AC Analysis
of Common
Cathode
Circuit
“Looking in” to the equivalent circuits from the output terminals, it is seen
that the output impedance of a common cathode amplifier is r p in parallel
with R l . Also, so long as the grid is biased negatively with respect to the
cathode, no grid current flows, and the circuit has a high input resistance
equal to R g .
The common cathode circuit can now be defined as having a high
input resistance, an output resistance of R L in parallel with r py substantial
voltage gain, and its output voltage antiphase to the input signal. Like its
transistor equivalent (the common emitter circuit), the common cathode
configuration is the most frequently used of all vacuum-tube circuits.
A vacuum triode used in a common cathode amplifier circuit has the Example 20-3
plate characteristics shown in Fig. 20-13. If the load resistance is 7 kfi, the
supply voltage is 175 V, and the grid bias is —2 V, determine I p and E p .
Calculate the input impedance, output impedance, and voltage gain of the
amplifier.
( 20 - 6 )
and
(20-7)
solution
when I p — 0, E PP = E p + 0.
£,-175 V
Plot point A on the characteristic at l p — 0, £^,= 175 V.
When E p — 0, E PP = Q+ I p R L .
Plot point B at l p — 25 mA, E p — 0 V.
452
Electron
Tubes
mA
Figure 20-13. Plate characteristics, load line, and parameters for Example 20-3.
Draw the dc load line from point A to B. Where the load line intersects
the E g — — 2 V characteristic, read
7 p = 10 mA and 2^= 105 V
input impedance
From Eq.(20-7),
Z t ■= R g = 1 typically
output impedance
From Eq. (20-6),
Z=r p \\R L
and
45
50 V
10 mA
(from the characteristics) = 5 kfi
Output impedance = R L || r p
7 kflX5 k!2
7k£2+5kfl
= 2.9 kfl
|
voltage gam
From Eq. (20-5),
V*L
r f> +
453
Common
Plate
Circuit
From Eq. (20-3),
A£.
At the bias point, an increase in E p of 50 V produces a change in l p of
10 mA when E g remains at —2 V. At the bias point, a decrease of 2 V in E g
produces a change of 10 mA in I p if E p remains at 105 V. Thus,
50 V
= 25
The voltage gain is
25X7 kfi
" 5kft+7kft
= 14.6
In this circuit (shown in Fig. 20-14) the load resistance R L is connected
in series with the cathode of the tube. The grid bias voltage E B is now
positive, but the grid-to-cathode voltage E g is not equal to the grid bias
voltage. Because of the voltage drop across R L ,
or ^g~ ^b~ {ip x Rl)
EB = E g + (I p X ^l)
20-8
Common
Plate
Circuit
Figure 20-14. Common plate amplifier or cathode follower.
454
Electron
Tubes
If R l = 10 kft, £^> = 200 V, and the tube has the characteristics shown
in Fig. 20-11, a dc load line can be drawn exactly as for the common
cathode circuit. From point Q on the load line,
E g = — 2 V and I p = 9.5 mA
£ fi =-2V + (9.5 mAX 10 kfl)
= +93 V
To achieve the bias conditions at point Q, the grid bias voltge must be
+ 93 V. This is a major change from the negative grid bias voltages required
with common cathode circuits. Note that the grid is still negative with
respect to the cathode.
Now consider the signal required to produce a ± 40 V output. A + 40
V change across the 10 kfi load resistance requires a +4 mA change in I p .
l p becomes (9.5 mA + 4 mA)= 13.5 mA, and to achieve this E g becomes
0 V (Fig. 20-11).
Now, I p XR L = 13.5 mAX 10 kft=135 V, and (bias voltage) + (signal
voltage) = E b + E sy where (E B + E s ) = E g + (I p X R L ). Since E B = + 93 V, the
signal voltage is E s = 135 — 93 V = 42 V. Therefore, an output change of + 40
V requires a signal input of + 42 V. Similarly, it can be shown that an input
of — 42 V will produce an output of — 40 V. Thus, the common plate circuit
has a voltage gain approximately equal to one, and the output is in phase
with the signal input. It can also be shown that this circuit has a high input
resistance and a very low output resistance. Like the transistor common
collector circuit, the common plate circuit (or cathode follower ) is normally
used as a buffer amplifier ; i.e., it is connected between a low impedance load
and a high impedance signal source.
20-9
Common
Grid
Circuit
This is the vacuum-tube equivalent of the transistor common base
circuit (Fig. 20-15). Since the input signal is applied to the cathode, the
input voltage must supply the plate current changes, and so the circuit has a
low input resistance. However, the signal is developed directly across grid
and cathode, so a voltage gain is achieved. Like its transistor equivalent, the
only major application of the common grid circuit is as a high-frequency
amplifier. The application of the signal to the cathode means that the grid
can be grounded to avoid feedback via the plate-to-grid capacitance.
20-10
Triode
Biasing
Methods
There are several methods of obtaining the required negative grid bias
voltage for a vacuum-tube circuit. Figure 20-10 shows that if a suitable
negative supply voltage is available the cathode may be grounded and the
grid connected via R g to — E b . By far the most convenient and most
frequently employed biasing method is the cathode bias technique illustrated
on Fig. 20-16. The negative grid voltage is provided by the voltage drop
I p XR k . Since the grounded end of R k is negative with respect to the cathode,
i
455
Triode
Biasing
Methods
r
Figure 20-15. Common grid amplifier.
the grid (which is grounded via R g ) is also negative w'ith respect to the
cathode. To obtain maximum ac gain, R k is bypassed by large capacitor C„
so that R k is short circuited to alternating current.
With the inclusion of the cathode resistance R k in the circuit, the total
dc load in series with the vacuum tube becomes (R L + R k ). The dc load line
must be drawn for (R L + R k ). If R k has a bypass capacitor, the ac load is R L .
The bias point on the dc load line can be determined by drawing a bias line.
A common cathode amplifier has /? L =9.7 k£2, 7?* = 270 £2, and E PP — Example 20-4
200 V. The triode employed has the plate characteristics shown in Fig.
20-1 1, and R k is ac bypassed by a large capacitor. Draw the dc load line and
Figure 20-16. Cathode bias or self-bias
456
Electron
Tubes
Figure 20-17. Determining £ point for self-biased circuit.
determine the values of E gi I p , and E p . Also draw the ac load line for the
circuit.
solution
Total dc load resistance = R L + R k = 9.7 k£2 + 270 £2« 10 k£2
The dc load line is drawn exactly as explained in Section 20-6. The
grid-to-cathode bias voltage must now be determined by plotting a bias line,
as shown in Fig. 20-17. With self-bias,
E=LX R,
g P *
When E g = -4 V, I p = 4 V/270 £2=14.8 mA.
Plot point 1 on the characteristics at E g = — 4 V, I p — 14.8 mA (Fig. 20-17).
When E g = — 3 V, I p = = 11.1 mA (point 2)
When E g — — 2 V , I p = = 7.4 mA (point 3)
When E g = - 1 V, I p = = 3.7 mA (point 4)
Now draw the bias line for R k = 270 £2 through points 1, 2, 3, and 4.
mA
30-
457
The
Tetrode
Tube
E P *~
Figure 20-18. AC load line for self-biased circuit.
The bias line intersects the dc load line at point Q,, giving E g ztz — 2A
V, /^«8.8 mA, and £^, = 112 V. Note that E p is the tube plate- to- cathode
voltage . The voltage from ground to plate is ( E p + I p R k ). Since R k is bypassed
to alternating current, the ac load = R L = 9.7 kft.
One point on the ac load line is point Q. When an ac signal causes l p
to change by A I p , E p will change by - A I p X R L .
Let A I p = 10 mA.
E p = — 10 mA X 9.7 k £2= -97 V
On Fig. 20-18, plot point C on the characteristic by measuring A I p =
10 mA and A E p = —97 V from the Q point.
Draw the ac load line through points C and Q. It is seen that, because
the value of ac load is close to the dc load value, the ac and dc load lines are
not very different from each other. This is not the case where (ac /?,)<&:( dc
20-11
The
Tetrode
Tube
Interelectrodc capacitance in a vacuum triode limits the high- 20-11.1
frequency performance of the device. The grid-to-cathodc capacitance (C^) Theory of
appears in parallel with the tube input and is referred to as the input Operation
458
Electron
Tubes
20 - 11.2
Characteristics
of the
Tetrode
capacitance. The plate- to-cathode capacitance (C pk ) is termed the output capaci-
tance. Since the grid-to-plate capacitance ( C provides a leakage path from
plate to grid, it is called the leakage capacitance. is the most important of
the three interelectrode capacitances because it permits signals from the
plate to be fed back to the grid at high frequencies. This can result in loss of
gain or in unwanted oscillations. To eliminate the high-frequency feedback,
the tetrode tube was developed.
In the tetrode an additional grid, the screen grid , is inserted between the
control grid and the plate. The construction is similar to that of the triode
illustrated in Fig. 20-5(a), with the screen grid as another fine wire spiral in
the space between plate and control grid.
When a tetrode is connected in a circuit the screen grid is grounded to
alternating current, so that signals fed back from the plate are channeled to
ground instead of reaching the control grid. The screen grid must also be
maintained at a high positive (dc) potential with respect to the cathode;
otherwise, it would repel the electrons from the cathode. A large capacitor
must be connected from screen grid to ground to provide an ac path to
ground. The tetrode circuit symbol and the biasing arrangement for the
screen grid are shown in Fig. 20-19.
Since the screen grid is held at a fixed high positive potential, it
behaves as another plate and collects a portion of the total electron flow
from the cathode. The plate collects the remaining portion of the cathode
current. The cathode current remains constant, being determined by E B and
R k . Therefore, I k = I p + l sg (see Fig. 20-19).
Consider the plate characteristic for E g = 0 and the screen grid char-
acteristic in Fig. 20-20. When the plate voltage is zero, no plate current
Figure 20-19. Tetrode biasing arrangement.
£> -
Figure 20-20. Typical tetrode plate characteristics and screen grid characteristic.
459
The
Tetrode
Tube
flows. Therefore,
7^ — 0 and I k — 0 + I sg
At this time all the cathode current flows via the screen grid. As E p is
increased from zero, I p increases and consequently I sg decreases. At points B
and B\ I p t&35 mA and I sg t & 50 mA. The cathode current is then / a sk 85 mA.
When the plate voltage exceeds that at point B y electrons accelerated
through the screen grid to the plate strike the plate with sufficient force to
cause secondary emission. Since the screen grid is more positive than the plate,
the secondary electrons are attracted from the plate to the screen grid. This
constitutes a decrease in I p and an increase in I sg , giving parts B to C and
parts B' to C' of the characteristics.
As the plate continues to be made more positive, the secondary
electrons begin to be attracted back to the plate. I tg now decreases and I p
increases again with E p increase, giving parts C to D and parts C' to 7)' of
the characteristic. Beyond points D and D\ E p is greater than E tg \ therefore,
the plate is collecting most of the electrons flowing from the cathode.
The kink in the tetrode characteristics is a distinct disadvantage,
because only the linear portion (beyond point D) of the characteristics is
usable. Several methods have been devised to eliminate the kink. One
approach resulted in the beam tetrode , which has the circuit symbol and
typical characteristics shown in Fig. 20-21. In the beam tetrode, the elec-
trons flowing to the plate arc concentrated in dense channels by the negative
potential on beam-forming plates located between the screen grid and the
plate. The result is that secondary emitted electrons are swept back to the
plate by the dense channel of electrons flowing toward the plate, and thus
the kink is largely eliminated from the characteristic.
0
'X
2X
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ft*
Plate
(a) Pentode circuit
symbol
-Ep~
(bi Pentode characteristics
Figure 20-22. Pentode circuit symbol and characteristics.
-
r r.
•X 'Wtr*
r*****’'*'
T
.re*- _
ductance ( g m ) of a pentode remains similar to that of a triode, because the
control grid in each case is located close to the cathode. From Fig. 20-22,
225 V
cr * 1
3 mA
= 75 kl>
rss***
Typically, r fi is around 1.5 MG. Values of 3000 to 10,000 are typical for
fi, while g m remains on the order of 1 to 10 mA/V, as in a triode.
ties*'
^ •
*■«**
The negative bias for the control erid of a pentode may be obtained by
any of the methods employed for a triode. The positive bias for the screen
?rid is usually provided by the potential divider technique shown in Fig.
20-23. A large capacitor (C 3 ) must be included to give the potential divider
a low- output impedance. The suppressor grid is usually connected directly to
either the cathode or ground.
20-1:
Pentc
Bias i
20-13
The
Variable-Mu
or Remote
Cutoff
Pentode
The transconductance characteristics for a sharp cutoff (i.e., normal)
pentode and for a remote cutoff pentode are shown in Fig. 20-24. For the sharp
cutoff pentode the characteristics are almost completely linear. Also, the
plate current is cut off (i.e., goes to zero) at small values of E g [—11 and
— 15 V in Fig. 20-24(a)]. For the remote cutoff tube the transconductance
characteristics are quite curved, and E g must go to a large negative level to
achieve I p cutoff.
In a normal pentode, the control grid wires are evenly spaced along
the length of the cathode, as they are in a triode (Fig. 20-5). Consequently,
electrons emitted from all parts of the cathode are equally affected by the
grid potential. In a remote cutoff pentode, the grid wires are either unevenly
spaced, or the cathode ends are allowed to project beyond the ends of the
grid. With this arrangement, electrons emitted from those cathode areas
which are relatively far from grid wires are less affected by the grid
potential. To repel electrons emitted from these (farther away) areas, the
grid must be made much more negative than it would otherwise need to be.
The result is a nonlinear transconductance characteristic and a cutoff grid
voltage which might be as large as — 60 V.
Consider Fig. 20-24(a) and (b) once again. The transconductance (g m )
is hI p /hE g , i.e., the slope of the characteristic. For the sharp cutoff device g m
remains substantially constant, but for the remote cutoff tube g m decreases
with increasing values of — E g , Since the tube amplificadon factor ( /i)
equals g m r p , the variation in g m produces a variation in p. Therefore, a
variable-mu pentode circuit has a gain which varies according to the grid bias.
This allows specialized applications such as automatic gain control.
Figure 20-23. Pentode amplifier circuit showing biasing technique for each electrode.
462
mA
Figure 20-24. Transconductance characteristics for sharp cutoff and remote cutoff
pentodes.
463
The
Cathode- Ray
Tube
20-14
The
Cathode-Ray
Tube
The basic construction and biasing of a cathode-ray tube are shown in 20-14.1
Fig. 20-25. The system of electrodes is contained in an evacuated glass tube General
with a viewing screen at one end. A beam of electrons is generated by the
cathode and directed to the screen, causing the phosphor coating on the
screen to glow where the electrons strike. The electron beam is deflected
vertically and horizontally by externally applied voltages.
20-14.2
Triode
Section
The triode section of the tube consists of a cathode, a grid, and an
anode, which are all substantially different in construction from the usual
electrodes in a triode vacuum tube. The grid, which is a nickel cup with a
hole in it (see Fig. 20-25), almost completely encloses the cathode. The
cathode, also made of nickel, is cylinder shaped with a flat, oxide-coated,
electron-emitting surface directed toward the hole in the grid. Cathode
heating is provided by an inside filament. The cathode is typically held at
approximately —2 kV, and the grid potential is adjustable from approxi-
mately — 2000 to —2050 V. The grid potential controls the electron flow
from the cathode, and thus controls the number of electrons directed to the
screen. A large number of electrons striking one point will cause the screen
to glow brightly; a small number will produce a dim glow. Therefore, the
grid potential control is a brightness control.
The first anode {A x ) is cylinder shaped, open at one end, and closed at
the other end with a hole at the center of the closed end. Since A x is
grounded and the cathode is at a high negative potential, A x is highly
positive with respect to the cathode. Electrons are accelerated from the
cathode through the holes in the grid and anode to the focusing section of
the tube.
20-14.3 The focusing electrodes A x , A 2 , and A 3 are sometimes referred to as an
The electron lens. Their function is to focus the electrons to a fine point at the
^5* Stern screen of the tube. A x provides the accelerating field to draw the electrons
464
Figure 20-25. Basic construction and biasing of cathode-ray tube.
from the cathode, and the hole in A x limits the initial cross section of the
electron beam. A 3 and /l, are held at ground potential while the A 2 potential
is adjustable around — 2 kV. The result of the potential difference between
anodes is that equipotential lines are set up as shown in Fig. 20-26. These are
lines along which the potential is constant. Line 1, for example, might have
a potential of — 700 V along its entire length, while the potential of line 2
might be —500 V over its whole length. The electrons enter A x as a
divergent beam. On crossing the equipotential lines, however, the electrons
experience a force which changes their direction of travel toward right
angles with respect to the equipotential lines. The shape of the lines within
A x produces a convergent force on the divergent beam, and those within A 3
produce a divergent force on the beam. The convergent and divergent forces
can be altered by adjusting the potential on A 2 . This adjusts the point at
which the beam is focused. A 2 is sometimes referred to as the focus ring.
The negative potential on A 2 tends to slow down the electrons, but
they are accelerated again by A 3 , so that the beam speed leaving A 3 is the
same as when entering A x . The electrons are traveling at a constant velocity
as they pass between the deflecting plates.
Consider the electrostatic deflection illustration in Fig. 20-27. When
the potential on each plate is zero, the electrons passing between the plates
do not experience any deflecting force. When the upper plate potential is
+ E/2 volts and the lower potential is —E/2, the potential difference
between the plates is E volts. The (negatively charged) electrons are
attracted toward the positive plate and repelled from the negative plate. The
electrons are actually accelerated in the direction of the positive plate.
However, since they also have a horizontal velocity, the electrons normally
never strike a deflecting plate. Instead, the beam is deflected and the
electrons strike the screen at a new' position.
465
The
Cathode- Ray
Tube
20-14.4
Beam
Deflection
Figure 20-26. Electrostatic focusing.
466
Electron
Tubes
20 - 14.5
The
Screen
Figure 20-27. Electrostatic deflection.
The beam could be deflected by grounding one plate and applying a
positive or negative potential to the other plate. In this case, the potential at
the center of the space between the plates would be greater or less than zero
volts. This would cause horizontal acceleration or deceleration of the elec-
trons, thus altering the beam speed. Equal positive and negative deflecting
voltages would then not produce equal deflections. With + E/2 volts on one
plate and —E/2 on the other plate, the center potential in the space
between plates is zero volts, and the beam speed is unaffected. The tube
sensitivity to deflecting voltages can be expressed in two ways. The voltage
required to produce one division of deflection at the screen (V/cm) is
referred to the deflection factor of the tube. The deflection produced by one V
(cm/V) is termed the deflection sensitivity .
The isolation shield shown in Fig. 20-25 is designed to keep the deflect-
ing plates isolated from each other’s electric fields.
The screen of a cathode-ray tube is formed by placing a coating of
phosphor materials on the inside of the tube face. When the electron beam
strikes the screen, electrons within the screen material are raised to a higher
energy level and emit light as they return to their normal levels. The glow
may persist for a few milliseconds, for several seconds, or even longer.
Depending upon the materials employed, the color of the glow produced at
the screen may be blue, red, green, or white.
The phosphors used on the screen are insulators, and, but for sec-
ondary emission, the screen would develop a negative potential as the
primary electrons accumulate. The negative potential would eventually
become so great that it would repel the electron beam. The secondary
electrons are collected by a graphite coating termed aquadag , around the
neck of the tube (see Fig. 20-25), so that the negative potential does not
accumulate on the screen. In another type of tube, the screen has a fine film
of aluminum deposited on the surface at which the electrons strike. This
permits the electron beam to pass through, but collects the secondary
electrons and conducts them to ground. The aluminum film also improves
the brightness of the glow by reflecting the emitted light toward the glass. A
further advantage of the film is that it acts as a heat sink, conducting away
heat that might otherwise damage the screen.
20 - 14.6
Brightness
of Display
20 - 14.7
Waveform
Display
As has already been explained, the brightness of the glow produced at
the screen is dependent upon the number of electrons making up the beam.
Since the grid controls the electron emission from the cathode, the grid
voltage control is a brightness control. Brightness also depends upon beam
speed; so for maximum brightness the electrons should be accelerated to the
greatest possible velocity. However, if the electron velocity is very high when
passing through the deflection plates, the deflecting voltages will have a
reduced influence, and the deflection sensitivity will be poor. It is for this
reason that postdeflection acceleration is provided; i.e., the electrons are accel-
erated again after they pass between the deflecting plates. A helix of resistive
material is deposited on the inside of the tube from the deflecting plates to
the screen (Fig. 20-25). The potential at the screen end of the helix might be
typically + 12 kV and at the other end 0 kV. Thus, the electrons leaving the
deflecting plates experience a continuous accelerating force all the way to
the screen, where they strike with high energy.
When an alternating voltage is applied to the vertical deflecting plates
and no input is applied to the horizontal plates, the spot on the tube face
will move up and down continuously. If a constandy increasing voltage is
also applied to the horizontal deflecting plates, then, as well as moving
vertically, the spot on the tube face will move horizontally. Consider Fig.
20-28, in which a sine wave is applied to a vertical deflecting plate and a
sawtooth is applied to the horizontal plates. If the waveforms are perfectly
synchronized, then at time t = 0 the vertical deflecting voltage is zero and the
horizontal deflecdng voltage is —2 V. Therefore, assuming a deflection
sensitivity of 2 cm/V, the vertical deflection is zero and the horizontal
deflection is 4 cm left from the center of the screen [point 1 on Fig. 20- 28(c)].
When / = 0.5 ms, the horizontal deflecting voltage has become —1.5 V;
therefore, the horizontal deflection is 3 cm left from the screen center. The
vertical deflecdng voltage has now become +1.4 V, and causes a vertical
deflection of + 2.8 cm above the center of the screen. The spot is now 2.8 cm
up and 3 cm left from the screen center (point 2). The following is a table of
data for other dmes.
At t
Horizontal
Vertical
Point
1 ms
-1 V
+ 2 V
3
1.5 ms
-0.5 V
+ 1.4 V
Point 4
2 ms
0 V
0 V
Center of screen.
2.5 ms
+ 0.5 V
-1.4 V
Point 6
3 ms
+ 1 V
-2 V
Point 7
3.5 ms
+ 1.5 V
-1.4 V
Point 8
4 ms
+ 2 V
-0 V
Point 9
At point 9 the horizontal deflecting voltage rapidly goes to — 2 V
again, so the beam returns to the left side of the screen. From here it is ready
468
Electron
Tubes
0 1 2 3 4 ms
7
(c) Display
Figure 20-28. Waveform display on cathode-ray tube.
to repeat the waveform trace over again. It is seen that, with a sawtooth
applied to the horizontal deflecting plates, any waveform applied to the
vertical plates will be displayed on the screen of the cathode-ray tube.
Example 20-5 A 500-Hz triangular wave with a peak amplitude of ± 40 V is applied
to the vertical deflecting plates of a CRT. A 250 Hz sawtooth wave with a
peak amplitude of ± 50 V is applied to the horizontal deflecting plates. The
CRT has a vertical deflection sensitivity of 0.1 cm/V and a horizontal
deflection sensitivity of 0.08 cm/V. Assuming that the two inputs are
synchronized, determine the waveform displayed on the screen.
solution
For a triangular wave,
T=
f
1
500 Hz
= 2 ms
469
The
Cathode-Ray
Tube
For a sawtooth wave,
1
250 Hz
= 4 ms
The two waveforms are shown in Fig. 20- 29(a) and (b).
at t = 0
Vertical voltage = 0
Horizontal voltage = — 50 V
Horizontal deflection = (voltage) X (deflection sensitivity)
= — 50 X 0.08 cm
= — 4 cm (i.e., 4 cm left from center)
Point 1 on the CRT screen [Fig. 20-29(c)] is at
Vertical deflection = 0
Horizontal deflection = 4 cm left of center
at t = 0J) ms
Vertical voltage = + 40 V
Horizontal voltage = — 37.5 V
Therefore, at point 2 on the CRT screen,
Vertical deflection = +40x0.1 cm = + 4 cm
Horizontal deflection = - 37.5 X0.08 cm — — 3 cm
at t = 1 ms (point 3)
Vertical deflection = 0
Horizontal deflection = — 25 X 0.08 cm =** — 2 cm
at /= 15 ms (point 4)
Vertical deflection = — 40 X 0. 1 cm = — 4 cm
Horizontal deflection — — 12.5X0.08 cm — — 1 cm
470
Electron
Tubes
4 8
(c) Display at CRT screen
Figure 20-29. Waveforms and display for Example 20-5.
at t = 2 ms (point 5)
Vertical deflection = 0
Horizontal deflection = 0
f(ms) 2.5 3 3.5 4
Vertical voltage + 40 V 0 — 40V 0
Vertical deflection +40 cm 0 —4 cm 0
Horizontal voltage
Horizontal deflection
Point
+ 12.4 V +25 V +37.5 V +50 V
+ 1 cm + 2 cm + 3 cm + 4 cm
6 7 8 9
The triode section and focusing section of the tube are together
referred to as an electron gun. A double-beam tube normally has two electron
guns used to generate two separate beams. Two separate sets of vertical and
horizontal deflecting plates are included. Both beams are made to sweep
across the screen together so that the time and phase relationships of
separate waveforms can be compared.
Vacuum diode. Two-electrode vacuum tube, contains plate and cathode.
Cathode. Negative terminal of vacuum tube — emits electrons when
heated.
Plate. Positive terminal of vacuum tube — collects electrons from cathode.
Anode. Same as plate.
Filament. Cathode, or heater for indirectly heated cathode.
Tungsten. Element used in filaments.
Thoriated tungsten. Alloy of tungsten and thorium, used for filament-type
cathodes.
Barium oxide. Electron-emitting oxide used on the surface of indirectly
heated cathodes.
Plate voltage, E p . Voltage at plate, or voltage measured from cathode to
plate.
Plate current, I p . Electrons flowing from cathode to plate — conventional
direction current from plate to cathode.
Plate characteristics. Graph of l p values plotted against corresponding
values of E p , for various constant values of grid voltage.
Space-charge limited region. Region of diode plate characteristics during
which space charge exists-region in which device is operated.
Temperature-limited region. Region of diode plate characteristics in
which all electrons emitted from the cathode are drawn to plate.
Vacuum triode. Three-electrode tube; contains plate, cathode, and grid.
Grid. Wire spiral surrounding the cathode, used to control the plate
current.
Transconductance, g m . Ratio of change in plate current to grid voltage
change.
Transconductance characteristic. Graph of l p values plotted against corre-
sponding grid voltage E g values, with E p constant.
Constant current characteristics. Graph of E p values plotted against corre-
sponding E g values, with I p constant.
20 - 14.8
Double-Beam
Cathode-Ray
Tubes
Glossary of
Important
Terms
471
472
Electron
Tubes
Plate resistance, r p . Reciprocal of the slope of plate characteristics —
{kEp/M p ) ohms.
Amplification factor, p. Ratio of plate voltage change for a given value of
Alp to grid voltage change for same A I p .
Common cathode circuit. Vacuum triode circuit in which input signal is
applied between grid and cathode, and output is taken between plate
and cathode.
Common plate circuit. Vacuum triode circuit in which input signal is
applied between grid and plate, and output is taken between cathode
and plate.
Cathode follower. Same as common plate circuit .
Common grid circuit. Vacuum triode circuit in which input signal is
applied between cathode and grid, and output is taken between plate
and grid.
Grid leak. Resistance used to connect grid to bias voltage and to “leak”
electrons off the grid.
Cathode bias. Biasing technique using a resistance in series with the
cathode.
Self-bias. Same as cathode bias.
Leakage capacitance. Plate-to-grid capacitance.
Input capacitance. Grid-to-cathode capacitance.
Output capacitance. Plate-to-cathode capacitance.
Tetrode. Four-electrode tube containing plate, screen grid, control grid,
and cathode.
Screen grid. Grid employed to screen the control grid from the effects of
plate voltage changes.
Beam tetrode. Tetrode with beam-forming plates to eliminate secondary
emission.
Pentode. Five-electrode tube containing plate, suppressor grid, screen grid,
control grid, and cathode.
Suppressor grid. Grid employed to suppress secondary emission.
Variable-mu pentode. Pentode in which the transconductance g m varies
according to grid bias voltage. Also requires large negative grid voltage
to cut off plate current.
Remote cutoff pentode. Same as variable-mu pentode.
Sharp cutoff pentode. Ordinary pentode (i.e., not variable-mu) — requires
relatively small negative grid voltage to cut off plate current.
Cathode-ray tube (CRT). Electron tube in which electrons are con-
centrated into a beam (or ray) which is directed to a display screen.
Electron gun. Cathode, grid, accelerating, and focusing electrodes in
cathode-ray tube.
Electron beam. Stream or ray of electrons in a cathode-ray tube.
Brightness control. Voltage control on the grid of a cathode-ray tube.
Focusing system. CRT electrodes which focus the electron beam to a point
at the screen of a cathode-ray tube.
Electron lens. Same as focusing system.
Equipotential lines. Lines in space between electrodes having a constant
potential along their length.
Focus ring. Cylindrical electrode on which the potential is varied to obtain
focus of electron beam in CRT.
Vertical deflecting plates. CRT electrodes which deflect the electron beam
vertically when a deflecting voltage is applied.
Horizontal deflecting plates. CRT electrodes which deflect the electron
beam horizontally when a deflecting voltage is applied.
Isolation shield. Metal plate inserted between CRT horizontal and vertical
deflecting plates to isolate their electric fields.
Deflection factor. Voltage required to produce one division of deflection at
screen of CRT (V/ cm).
Deflection sensitivity. Divisions of deflection at screen of CRT produced
by 1 V at deflecting plates (cm/V).
Screen. Flat portion of CRT glass envelope, has inside coating of phosphor
materials which glow when struck by electrons.
Aquadag. Graphite coating inside the neck of CRT, collects secondary
emitted electrons.
Postdeflection acceleration (PDA). Arrangement to accelerate CRT elec-
tron beam after it has been deflected.
Resistive helix. Film of resistive material deposited as helix around the
neck of a CRT to facilitate postdeflection acceleration.
Double-beam CRT. CRT with two electrode systems generating separate
electron beams.
20-1. Draw sketches to show the circuit symbol and mechanical construc-
tion of a vacuum diode. Name each part of the device and briefly
explain how it operates.
20-2. (a) Describe the construction of two types of thermionic cathode.
State the advantages and disadvantages of each, (b) List the materi-
als used for plates in low-power and high-power vacuum tubes.
20-3. Sketch typical (plate voltage)/(plate current) characteristics for a
vacuum diode. Label each region of the characteristics, explain their
shape, and show the effects of temperature increase.
20-4. Draw sketches to show the symbol and mechanical construction of a
triode vacuum tube. Name each electrode and state its function.
20-5. Sketch typical plate characteristics for a vacuum triode for several
473
Review
Questions
Review
Questions
474
Electron
Tubes
values of negative grid voltage. Also show the effect of positive grid
voltage.
20-6. Sketch a practical circuit diagram for
(a) A vacuum triode common cathode amplifier.
(b) A vacuum triode common plate amplifier.
(c) A vacuum triode common grid amplifier.
Indicate supply voltage polarities, current directions, input, and
output terminals.
20-7. Draw an ac equivalent circuit for a common cathode amplifier. Draw
the voltage equivalent circuit (from the ac equivalent circuit) and
derive expressions for voltage gain and output resistance. Also state
the input resistance.
20-8. State typical applications for common cathode, common plate, and
common grid amplifiers. Explain each application in terms of voltage
gain, input and output resistance, etc.
20-9. State the function of, and typical maximum value for, a grid leak
resistor. Briefly explain the possible effects of making the grid leak
resistor too large.
20-10. Draw sketches to show how the grid of a vacuum triode may be
biased to a desired voltage by cathode bias (or self-bias).
20-11. Draw a sketch to show the various capacitances that exist within a
triode vacuum tube. Name each of these capacitances, state which is
most important, and explain why.
20-12. Explain how the tetrode vacuum tube combats the effects of inter-
electrode capacitance. Sketch the circuit symbol for a tetrode and
name each electrode and state its function.
20-13. Sketch one plate characteristic and one screen grid characteristic for
a tetrode vacuum tube. Carefully explain the shape of the character-
istics.
20-14. Explain the origin and operation of a beam tetrode. Sketch the
circuit symbol and a typical family of plate characteristics for this
device.
20-15. Explain the origin of the pentode vacuum tube. Sketch a typical
family of plate characteristics and the circuit symbol for the device.
20-16. State typical values for /t, g m , and r p for a pentode. Briefly explain.
20-17. Draw a circuit diagram of a pentode common cathode amplifier with
self-bias. Explain the bias arrangements for each electrode.
20-18. Sketch typical transconductance characteristics for (a) a sharp cutoff
pentode, (b) a variable-mu pentode. Explain the characteristics, and
discuss the mechanical differences between the tubes. State a typical
application for a variable-mu tube.
20-19. Sketch the electron-gun section of a cathode-ray tube. Identify each
electrode and its function; also indicate typical voltages.
20-20. Draw a sketch to show how an electron lens functions. Briefly
explain.
20-21. Sketch the deflection system of a cathode- ray tube and explain how it
operates.
20-22. Describe the screen of a cathode-ray tube. Explain the function of the
aquadag, and describe another method of performing the function.
20-23. Define postdeflection acceleration. Explain why PDA is required and how
it is achieved.
20-1. A vacuum diode with plate characteristics as shown in Fig. 20-3 is
connected in series with a load resistance of 3.3 kfi and a supply of 90
V. Draw the dc load line and determine the values of /. and £..
p P
20-2. A vacuum diode with a series load of 2 kfi has an I p of 18 mA. If the
plate characteristic for the diode is as shown in Fig. 20-3, draw the dc
load line and determine the supply voltage.
20-3. From the triode plate characteristics in Fig. 20-30 derive (a) the
transconductance characteristic for £,= 80 V; (b) the constant cur-
rent characteristic for I p — 4 mA.
20-4. From the plate characteristics in Fig. 20-30 derive r p , g mt and p at
£, = 60 V, £,= — 1 V.
20-5. A triode used in a common cathode amplifier has the plate character-
istics of Fig. 20-30. Supply voltage is 120 V, load resistance is 12 kfi,
and grid bias is —2 V. Draw the dc load line and determine plate
current and voltage. Also calculate the output impedance and voltage
gain of the amplifier.
475
Problems
Problems
Figure 20-30. Triode plate characteristics for Problems 20-3 through 20-6.
476
Electron
Tubes
20-6. A common cathode amplifier has R L = 1 3 kfl, R k = 2 kft, and E PP —
100 V. The triode employed has the plate characteristics of Fig.
20-30, and R k is ac bypassed by a large capacitor. Draw the dc load
line and determine the values of E g , I p , and E p . Also draw the ac load
line for the circuit.
20-7. A common cathode amplifier uses a triode with the characteristics
shown in Fig. 20-11. The supply voltage is £^, = 150 V, and the plate
voltage is to be E p = 100 V when E g = — 2 V. Draw the dc load line;
determine the value of R L and calculate A v .
20-8. The circuit in Problem 20-7 is to use the cathode bias technique.
Determine a suitable value for R k . Assuming R k is bypassed by a large
capacitor, draw the ac load line for the circuit. Taking 7^ = 100 kft,
calculate the input and output impedance of the circuit.
20-9. A common plate circuit with R L = 9 kft has a vacuum triode with the
characteristics shown in Fig. 20-17. The supply voltage is E^ = 180 V,
and the cathode voltage is to be E k = 80 V. Draw the dc load line for
the circuit and determine the level of I p . Also calculate the required
grid bias voltage level.
20-10. A pentode tube in a common cathode amplifier has the characteris-
tics shown in Fig. 20-22. The supply voltage is £ ' <pp = 300 V, and E p is
to be 150 V when /, = 50 mA. Draw the dc load line and determine
the required value of E g .
20-11. For the circuit in Problem 20-10 determine a suitable value of
cathode resistor R k to give the required grid bias voltage. Assuming R k
is bypassed by a large capacitor, calculate the circuit voltage gain
and output impedance.
20-12. A pentode common plate circuit with £ L = 4 kfi and £^, = 300 V uses
a tube with the characteristics in Fig. 20-22. The cathode voltage is to
be approximately 160 V. Draw the dc load line, determine the level
of I p> and calculate the required grid bias voltage.
20-13. A CRT has a deflection of 5 cm when 75 V is applied to the
deflecting plates. Calculate its deflection factor and deflection sensi-
tivity.
20-14. A 1 kHz square wave with a peak amplitude of ±25 V is applied to
the vertical deflecting plates of a CRT. A 500 Hz sawtooth with a
peak amplitude of ±40 V is applied to the horizontal deflecting
plates. The CRT has a vertical deflection sensitivity of 0.1 cm/V and
a horizontal deflecting sensitivity of 0.075 cm/V. Assuming that the
two inputs are synchronized, determine the waveform displayed on
the screen.
20-15. Repeat Problem 20-14 with the following changes:
(a) The sawtooth waveform is 1 kHz.
(b) A triangular wave is substituted in place of the square wave.
(c) The square wave is replaced by a pulse waveform with a pulse
width of 250 /as and a frequency of 1 kHz.
Appendixes
Appendix 1
Typical Standard Resistor Values
n
Q
til
til
til
MS 2
MS 2
10
100
1
10
100
1
10
—
12
120
1.2
12
120
1.2
—
—
15
150
1.5
15
150
1.5
15
—
18
180
1.8
18
180
1.8
—
—
22
220
2.2
22
220
2.2
22
2.7
27
270
2.7
27
270
2.7
—
3.3
33
330
3.3
33
330
3.3
—
3.9
39
390
3.9
39
390
3.9
—
4.7
47
470
4.7
47
470
4.7
—
5.6
56
560
5.6
56
560
5.6
—
6.8
68
680
6.8
68
680
6.8
—
—
82
820
8.2
82
820
—
—
477
478
Appendix 2
Appendix 2
Typical Standard Capacitor Values
pF
pF
pF
PF
pF
pF
pF
HF
»F
pF
hF
5
50
500
5000
0.05
0.5
5
50
500
5000
—
51
510
5100
—
—
—
—
—
—
—
56
560
5600
0.056
0.56
5.6
56
—
5600
—
—
—
6000
0.06
—
6
—
—
6000
—
62
620
6200
—
—
—
—
—
—
—
68
680
6800
0.068
0.68
6.8
—
—
—
—
75
750
7500
—
—
—
75
—
—
—
—
—
8000
—
—
8
80
—
—
—
82
820
8200
0.082
0.82
8.2
82
—
—
—
91
910
9100
—
—
—
—
—
—
10
100
1000
0.01
0.1
1
10
100
1000
10,000
—
110
1100
—
—
—
—
—
—
12
120
1200
0.012
0.12
1.2
—
—
—
—
130
1300
—
—
—
—
—
—
15
150
1500
0.015
0.15
1.5
15
150
1500
—
160
1600
—
—
—
—
—
—
18
180
1800
0.018
0.18
1.8
18
180
—
20
200
2000
0.02
0.2
2
20
200
2000
22
220
2200
—
0.22
2.2
22
—
—
24
240
2400
—
—
—
—
240
—
—
250
2500
—
0.25
—
25
250
2500
27
270
2700
0.027
0.27
2.7
27
270
—
30
300
3000
0.03
0.3
3
30
300
3000
33
330
3300
0.033
0.33
3.3
33
330
3300
36
360
3600
—
—
—
—
—
—
39
390
3900
0.039
0.39
3.9
39
—
—
—
—
4000
0.04
—
4
—
400
—
43
430
4300
—
—
—
—
—
—
47
470
4700
0.047
0.47
4.7
47
—
—
Answers to Problems
3-1 50 fi, 46 mA Chapter 3
3-2 16 mA, 38 mA
3-3 12 /xA, 24 pA
3-6 14.3 fi, 12 mA
3-7 37 mA, 1 pA
3-8 49 V, 10 mV, 49 mA, 49 mW
3-9 750 pF
3-10 1.237 A, 120 mA, 27.8 V, IN4001, 0.46 «
3-11 335 pF
3-12 61 1 mA, 60 mA, 14.6 V, IN4001, 0.44 fl
3-13 780 pF
3-14 25 MHz, 33.3 MHz
3-15 200 fl, 15 V, 71.5 mA
3-16 433 fi, 7 V, 14.5 mA
479
Chapter 4
Chapter 5
Chapter 6
Chapter 8
4-1 2.0 mA
4-2 0.98, 49, 5.355 mA, 0.301 mA
4-3 2.08 mA, 2.1mA
4-4 12.627 mA, 61.5, 0.984, 9.66 mA
4-5 40 p A, 2.3 mA
4-7 3 mA, 2.9 mA
4-8 50
4-9 0.06 X 10~ 3 , 53.3
4-10 2.7 k!2
5-1 (0.97 mA 7.7 V), (0.75 mA 6 V)
5-2 4.5 k!2
5-3 (2.325 mA 5.35 V), (1.86 mA 6.28 V), (2.79 mA 4.42 V)
5-4 ±2.3 V
5-5 283.2 k!2, 10 V, 0.134 V
5-6 251.7 k!2, 14.91 V, 10.08 V
5-7 9.58 V, 12.5 V, 7.13 V
5-8 248 k!2, 4.94 k!2, 1 1.67 V, 8.77 V
5-9 6.06 V, 6.02 V, 6.008 V
5-10 10 k!2, 9.84 k 12, 19 k!2, 10.7 k!2, 9.92 V, 10.2 V
5-11 5.93 k!2, 13.1 k!2, 6.7 k 12, 8.04 V, 7.97 V
5-12 61,59.3,1.83
5-13 1mA, 8 V
6-1 992 12, 3.289 k!2, - 132, 39.7, 5240
6-2 12.96 k!2, 3.289 k!2, -9.08, 35.68, 324
6-3 18.93 k!2, 39.47 12, 1, 0.945, 0.945
6-4 48.89 12, 3.88 k!2, 77.22, 0.968, 74.75
6-5 147.4 12, 24.44, 22.57
6-6 1.49 k!2, 8.2 k!2, 29387, 5343, 1.59 X 10 8
6-7 4029,1211
6-8 7.74, 5
8-1 64.1 °C, 155.4 mW
8-2 8.1 k!2
8-3 — 1.25 dB
8-4 1.262 V
8-5 160 kHz, 125.7 kHz
8-6 141 pF
8-7 2.79 pF
8-8 938 pF, 1038 pF, 31938 pF, 938 pF
8-9 19.13 pV
8-10 2.4 dB
8-11 25 V, 0.65 V to 0.85 V
8-12 90.4, no
480
9-1
/?, = /? 5 = 100 k!2, R 2 = R b = 33 k!2, /? 3 = /? 7 =10 k!2, R 4
= R q = 3.3 k!2, C 2 =C 4 = 330 /xF, C, = C 2 = 22 /xF
Chapter 9
9-2
/?, = /? 5 = 39 k!2, R 2 — R b = 22 k!2, /? 3 = /? 7 = 3.3 k!2 /? 4 =
R & = 2.2 k!2, C 2 =C 4 = 180 /xF, C, = C 3 = 15 /xF
9-3
^1 = ^2 = 560 &l\ = ^42 = 5.6 k!2, C, = C 2 = 15 /xF
9-4
/?, = 10 k!2, /? 2 = 390 k!2, /? 3 = 6.8 k!2, 7? 4 = 5.6 k!2, C, =
5.6/xF, C 2 = 47 fxF
9-5
/?, = 12 k!2, /? 2 = 120 k!2, /? 3 = 12 k!2, /? 4 = 4.7 k!2, C, = 15
jxF,C 2 = 47 jxF
9-6
12.2 V
9-7
117.5, 3 k!2, 4.7 k!2
9-8
5.25 V
9-9
7.9998 V
9-10
/?, = 1.5 k!2, R 2 — 1 00 k!2, 7? 3 = 1.5 k!2
9-11
/?, = 1 k!2, /? 2 = 1 20 k!2, R 3 =l k!2
9-12
/?, = 820 12, /? 2 = 1 80 k!2, /? 3 = 180 k!2
9-13
/?, = 1 k 12, 7?2 = 33 k 12, /? 3 = 1 k!2
9-14
Point A: (20 V, 0 mA), Point Q: (15 V, 49.7 mA), Point
B: (A V= 20 V, A/ c = 49.7 mA)
9-15
Point Q: (40 V, 0 mA), Point B: (0 V, 66.8 mA)
9-16
Transformer: 8 W, R L = 12 12, /?/ = 155 12 , Transistor:
50 V, 644 mA, 4 W
9-17
18 V, 20 W, Transistors: 90 V, 900 mA, 10 W
9-18
37.6 fiA, 7.4 V, 0.95 W, 35 mW
10-1
/?,= 6.8 k!2, R 2 = 220 k!2, /? 3 = 6.8 k!2, 7? = 680 12, C =
0.033 jxF
Chapter 10
10-2
/?,= 4.7 k!2, 7? 2 =150 k!2, 7? 3 = 4.7 k!2, /? = 180 12
10-3
/?, = 5.6 k!2, R 2 = 3.3 k!2, R 3 = 1 .5 k!2, /? 4 = 1 .5 k!2, C, *
5.6 fxF
10-4
C, = C 2 = 0.1 /xF, L = 56 mil, 7?,=47 k!2, /? 2 = 180 k!2
10-5
C, = C 2 = 0.82 /xF, /?, = 33 k!2, /? 2 = 150 k!2
10-6
C, = C 2 = 1300 pF, /?, = /? 2 = /? 4 = 8.2 k!2, /? 3 = 18 k!2
10-7
/?, = /? 2 = 7? 4 = 3.3 k!2, /? 3 = 6.8 k!2
11-1
8.8 V, 8.9425 V, 0.002%/ °C
Chapter 11
11-2
IN751, /? 5 = 116 12, R l — 103 12, S t , = 0.128, Z 0 = 14.83 12
11-3
3%, 14.7%
11-4
IN757, R s = 470 12, 0.115 V
11-5
10.91 mA, 679 12
11-6
IN755, R e = 3.3 k!2, 7?,=680 12, 2.06 mA
12-3
2 mA/V, 0.35 mA/V
Chapter 12
12-5
259 mA/V
481
Chapter 13
Chapter 14
Chapter 15
Chapter 16
13-1 -1.5 V
13-2 7.8 mA, 2.9 mA, 23.62 V, 12.84 V, 12.7 mA, 7.5 mA,
13.5 V, 2.06 V
13-4 1.9 mA, 1.3 mA, 13.89 V, 11.07 V, 8.82 V, 3.66 V
13-5 6.5 kfi,/?,=3i? 2
13-6 7.75 V, 4.6 V
13-7 1.7 mA, 1.3 mA, 4.34 V, 0.72 V
13-8 2.5 k ft
13-10 25.6 V, 15.7 V
13-11 17.2 V, 15 V
13-12 16.64 V, 12.72 V
13-13 21.37 V, 14.06 V
13-14 12.95 V, 9.19 V, 9.08 V, 3.2 V
13-15 1.1 Mft, 100 kft, 3.5 k ft
13-16 RJR 2 = 15
13-17 1.3 M ft, 200 kft, 2.5 k ft
14-1 25.5, 6.37 kft, 2.2 Mft
14-2 42.7 pF, 6.29 kft
14-3 20 kft, 90, 120
14-4 117 pF, 154.4 pF
14-5 687.5 kft, 194 ft, 0.97
14-6 2N5459, 181.8 ft, 333.3 ft, 142.8 ft, 0.82
14-7 25.47, 241 ft, 6.37 kft
14-8 13.6 kft, 59.9, 11.98
14-9 ^ = 9.8 V, V s = (-6.7 V, -4.2 V)
14-10 2.2
15-1 -63.6 ft
15-2 -146 ft
15-3 3.8, 1,3.8
15-4 120 ft, 12 ft, 225 mV, ± 140 mV
15-5 7
16-1 50.5 ft, 0.5 V, 247 pA, 1.05 V
16-2 C6A, 0.58 V, 0.63 mA, 1.033 V
16-3 652 kft, 3.2 Mft, C6B
16-4 8.46 kft, 82.2 kft
16-5 1.02 V
16-6 39 kft, 53 kft
16-7 1 V, 15 V, <0.83 mA, <2 mA
482
16-8
16-9
16-10
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
19-1
19-3
19-4
19-5
19-6
20-1
20-2
20-4
20-5
20-6
20-7
C6B, = (1.4 M12 to 8.5 M12)
/?! = (129 k!2 to 1.55 M12), (V R for Z), & D 2 )>311 V
1.5°
120 mW, 21.9 V
11.7 V, 17.1 V
50.8 Hz
11.3 k 12, 3.4 M 12
33 k!2, 12 k!2, 18.95 V, 1.5 V, 45 k!2
270 12, 0.34, 1 V
15.6 Hz, 12.4 Hz, 21.2 V
1.8 k!2, 820 12, I G < 1 mA, ^*<2.5 V
6.8 k!2, 3.9 k!2, 14.6 V, 0.9 V, 10.7 k!2
368 W, 3 mW
1.18 kW
6.5 k!2 between base and + 5 V
50 /xA, 22 pA
162 0.25 V, 0.9 mA
43 12, 116 12, 326 12
0.04 V
70 cells, 5 parallel groups of 14 in series
1,792 parallel groups of 279 in series, 116kVVh
2.5 k!2
1.4 mA
flj = 27 k!2, R 2 = 680 12 with V= V cc
1.2 k!2
10.58 V
1.5, 12
1.7 MHz, 2.5 MHz
200 12, 3.75 mA, 2.1 mA, 0.65 mA
(a) 15 k!2, (b) 13.7 k!2, 14.96 k!2, (c) 15 k!2, 14.96 k!2
17 mA, 34 V
70 V
5 k!2, 4 mA/V, 20
3.5 mA, 78 V, 3.53 k!2, 14.1
-2.6 V, 1.3 mA, 80 V
6.8 k!2, 17.3
483
Answers to
Problems
Chapter 17
Chapter 18
Chapter 19
Chapter 20
484
20-8
270 fi, 100 kfl, 2.1 k ft
Answers to
20-9
8.9 mA, 78 V
Problems
20-10
-6 V
20-11
120 fi, 18.75, 3 k£2
20-12
3.75 mA, -8 V
20-13
15 V/cm, 0.067 cm/V
index
Abrupt junction, 423
ac bypassing, 110
ac degeneration, 1 10
ac equivalent circuit ( See under device
name )
ac load line, 110, 214, 257
ac resistance, 23
Acceptor doping, 10
Active region, 76
Alloy transistor, 146
Alpha, 70
Ampere, 6
Amplification factor, 447, 461
Amplifier:
bandwidth, 167; buffer, 130, 204,
313, 454; capacitor coupled, 183;
class A, 211; class AB, 219; class B,
216; cascaded CE, 139; common base
(CB), 131; common cathode, 447;
Amplifier ( Qmtd .)
common collector (CC), 125; com-
mon drain, 255; common emitter
(CE), 116; common gate, 318; com-
mon grid, 454; common plate, 453;
common source, 308; differential,
192; direct coupled, 188; FET, 308,
313, 318; frequency response, 167;
half power points, 167; high input
impedance, 208; IC, 201; inverting,
209; multistage, 101; non-inverting,
206; operational, 201; parallel, 335;
transformer coupled, 211, 216; tran-
sistor, 125, 131, 139; tunnel diode,
335; vacuum triode, 447
And gate, 55
Annular transistor, 149
Anode, 29, 437
Aquadag, 465
485
486
Index
Atom, 1
Atomic bonding, 7
Atomic number, 3
Atomic weight, 3
Avalanche breakdown, 247
Bandwidth, 167
Barium oxide, 438
Barium titanate, 421
Barkhausen criteria, 230
Barrier potential:
at pn -junction, 18; at transistor
junctions, 65
Base (of transistor), 65
Base current, 70
Base-emitter voltage, 68
Beam tetrode, 459
Beta, 72
Bias circuits:
FET, 289; MOSFET, 300, transistor
(bipolar), 93; vacuum tube, 454
Bias line:
FET, 292, 295, 296; MOSFET, 301,
303; vacuum tube, 455
Bi-FET circuits, 322
Bi-MOS circuits, 322
Bilateral four layer diode, 359
Bipolar transistor, 69
Boltzsman’s constant, 171
Bonding:
covalent, 7, ionic, 7; metallic, 7
Breakdown diode, 245
Bridge rectifier, 50
Buffer amplifier, 130, 204, 313, 454
Bypass capacitor, 110, 185, 295, 455
Cadmium selenide, 385
Cadmium sulfide, 385
Capacitance:
depletion layer, 25; diffusion, 25; in-
terelectrode, 457; storage, 25; stray,
167
Capacitive tuning ratio, 423
Capacitor:
by-pass, 110, 185, 295, 455; coupling,
185; reservoir, 51; smoothing, 51
Cascaded CE circuit, 139
Cathode, 29, 438
Cathode bias, 454
Cathode follower, 454
Cathode ray tube, 463
aquadag, 465, beam deflection, 465;
brightness, 467; brightness control,
464; deflection factor, 466; deflection
sensitivity, 466; double beam CRT,
471; electrode system, 464; electron
gun, 471; electron lens, 464; equi-
potential lines, 465; focus ring, 465;
focusing, 464; isolation shield,
465; post deflection acceleration,
467; screen, 466; triode section, 464;
waveform display, 467
Ceramic transducer, 422
Channel (FET), 262
Characteristics ( See Diode, Transistor,
etc.)
Charge carriers, 6
majority, 11, 68; minority, 11, 68;
mobility, 6; n-type, 10; p- type, 10
Coherent light, 407
Circuit noise, 171
Class A driver, 219
Class A amplifier, 21 1
Class AB amplifier, 219
Class B amplifier, 216
Collector, 67
Collector-base junction, 66
Collector-base leakage current, 70
Collector current, 70
Collector-to-base bias, 100
Colpitts oscillator, 234
Common base characteristics:
current gain, 77; forward transfer, 77;
input, 75; output, 75
Common base circuit, 131
current gain, 136; current gain factor,
71; cut-off frequency, 169; A -parame-
ter analysis, 132; input impedance,
133; output impedance, 134; power
gain, 136; voltage gain, 135
Common cathode circuit, 447
ac analysis, 449; ac equivalent cir-
cuit, 450; ac load line, 457; dc load
line, 448; input impedance, 451; out-
put impedance, 451; voltage gain,
450
Common collector characteristics:
current gain, 81; input, 82; output,
81
Common collector circuit, 125
current gain, 1 29; A-parameter analy-
sis, 126; input impedance, 127; out-
put impedance, 127; power gain, 129;
voltage gain, 128
Common drain circuit, 313
ac analysis, 315; equivalent circuit,
315; input impedance, 317; output
impedance, 316; voltage gain, 315
Common emitter characteristics, 78
current gain, 80; cut-off region, 179;
input, 78; output, 79; saturation re-
gion, 176
Common emitter circuit, 1 1 6
current gain, 117, 122; current gain
factor, 72; cut-off frequency, 169; A-
parameter analysis, 118; input im-
pedance, 120; output impedance,
120; power gain, 122; voltage gain,
121
Common gate circuit, 318
ac analysis, 319; equivalent circuit,
319; input impedance, 321; output
impedance, 320; voltage gain, 319
Common grid circuit, 454
Common mode gain, 196
Common plate circuit, 453
Common source circuit, 308
ac analysis, 310; equivalent circuit,
310; input impedance, 312; output
impedance, 311; voltage gain, 310
Compensated reference diode, 251
Complementary emitter follower, 225
Composite characteristics, 217
Conduction band, 4
Conduction in solids, 5, 6, 12
Conductor resistivity, 8, 9
Constant current characteristics, 444
Constant current circuit, 198, 254
Constant current tail, 198
Conventional current, 6
Covalent bonding, 7
Cross-over distortion, 218
Crystal lattice, 7
Crystal oscillator, 420
Crystal, piezoelectric, 414
Cut-off frequencies, 167
Dark current, 383
Dark resistance, 12, 384
Darlington pair, 222
Data sheet:
diode, 40; FET, 270, 284, IC, 201,
202; SCR, 349, 350; transistor (bi-
polar), 158; UJT, 368; Zener diode,
249
dB, 165
dc bias point:
diode, 35; FET, 291; transistor (bi-
polar), 94; tunnel diode, 335; vacuum
triode, 454
dc feedback pair, 189, 323
dc load line:
diode, 33, 35; FET, 289; photodiode,
390; phototransistor, 396; transistor
(bipolar), 94; transformer coupled
circuit, 214; tunnel diode, 340;
vacuum triode, 448
Decibels, 165
Deflection sensitivity, 466
Delay time, 178
Depletion layer capacitance, 25, 26
Depletion mode MOSFET, 281
Depletion region, 18, 19, 67
Derating of transistors, 163
D1AC, 354
Differential amplifier, 192
common mode gain, 196; constant
current tail, 198; IC differential
amplifier, 200; input impedance, 196;
inverting input, 196; noninverting in-
put, 196; output impedance, 196;
voltage gain, 193
Diffused transistor, 147
Diffusion capacitance, 25
Diffusion current, 12
Diffusion process, 145
Diode:
ac resistance, 23; alloy, 31; AND
gate, 55; avalanche, 245; bias point,
35; capacitance, 25; characteristics,
31; clipper, 56; currents, 40; data
sheet, 40; dc bias point, 35; dc load
line, 33; diffused, 31; double based,
364; dynamic resistance, 23; equiv-
alent circuit, 39; Esaki diode, 327;
fabrication, 31; forward resistance,
23; forward volt drop, 32; frequency
response, 53; graphical analysis, 33;
IC diode, 152; light-emitting diode,
487
Index
488
Index
Diode ( Contd .)
398; logic circuits, 55; OR gate, 56;
parameters, 31; peak repetitive cur-
rent, 48; peak reverse voltage, 40, 49;
photo diode, 388; piecewise linear
characteristics, 38, 333; power dis-
sipation, 43; rectifier, 43, 49; reverse
breakdown, 33, 40; reverse current,
20, 32; reverse resistance, 20; reverse
saturation current, 33; Shockley di-
ode, 355; static forward volts drop,
43; static reverse current, 43; steady
state forward current, 40; surge cur-
rent, 40; switching time, 53; symbol,
30; temperature, 23; tunnel diode,
327; vacuum diode, 438; varactor di-
ode, 422; voltage multiplier, 58;
WC diode, 422; Zener diode, 245
Donor doping, 9
Double-base diode, 364
Drain (of FET), 262
Drain characteristics, 265
Drift current, 12
Driver stage, 219
Dynamic resistance, 23, 33
Dynamic scattering, 401
Dynode, 382
Electron, 1
deflection, 465; emission, 438; gas
bonding, 7; gun, 471; lens, 464; mo-
tion, 5; shell, 3; tubes, 437; valence, 3
Electron-volt, 4
Electron charge, 1
Electronic mass, 2
Electrostatic deflection, 466
Emitter, 66
Emitter-base junction, 65
Emitter current bias, 102
Emitter follower, 1 26, 1 22, 1 25
Energy bands, 4, 9
Energy gap, 4
Energy levels, 4
Enhancement MOSFET, 279
Epicap, 422
Epitaxial growth, 145
Epitaxial mesa, 148
Equipotential lines, 465
Equivalent circuit, ( See under device
name)
Esaki diode, 327
Extrinsic semiconductor, 9
Fall time, 178
FET (field effect transistor), 262
bias circuit, 292; bias line, 292, 295,
301; bias point, 291; breakdown volt-
age, 275; capacitances, 276; channel
ohmic region, 266; common drain
{See Common drain circuit); common
gate {See Common gate circuit); com-
mon source {See Common source
circuit); construction, 276; dc load
line, 289; depletion enhancement
MOSFET, 281; depletion regions,
262; differential stage, 323; drain,
262; drain characteristics, 265; drain
current, 262; drain resistance, 274;
drain-source ON resistance, 274;
drain-source ON voltage, 274; drain-
source saturation current, 266, 271;
enhancement MOSFET, 279; equiv-
alent circuit, 277; fixed voltage bias
circuit, 292; forward transfer admit-
tance, 273; gate, 262; gate reverse
current, 274; gate-source cut-off cur-
rent, 274; gate cut-off voltage, 271;
graphical analysis, 290, 299; Ipss,
266, 271; input resistance, 274; in-
sulated gate FET (IGFET), 278;
junction FET (JFET), 262;
MOSFET, 278; ^-channel FET, 262;
noise figure, 271; output admittance,
274; /^-channel FET, 268; parame-
ters, 269; pinch-off current, 271;
pinch-off region, 266; pinch-off volt-
age, 266, 271; power dissipation, 275;
saturation current, 266, 27 1 ; self bias,
293, 296, 301; source, 262; spread of
characteristics, 271; symbol, 264, 279,
280, 282, 264, 269; tetrode connected,
264; transadmittance, 273; transcon-
ductance, 272; transfer characteris-
tics, 267; V-MOSFET, 282
Filament, 438
Fixed current bias, 98
Focusing ring, 465
Foot candle, 381
Forbidden gap, 4
Forward transfer admittance, 273
Forward transfer ratio, 86
Four-layer device, 344
Four-layer diode, 355
Frequency response:
diode, 53; transistor, 144, 167
Free electrons, 5
Full-wave rectification, 49
Gallium arsenide, 398
Gallium arsenide phosphide, 398
Gas discharge display, 404
Gate (of FET), 262
Gate (of SCR), 344
Germanium, 3
Germanium atom, 3
Graphical analysis (See under device name )
Grid, 441
Grid leak, 448
Grounded base ( See common base)
Grounded collector (See common collec-
tor)
Grounded emitter (See common emitter)
h FE , h /t> 72, 86
h f£ tolerance, 93
A-parameters, 84, 86
A-parameter circuit analysis:
common base, 132; common collec-
tor, 126; common emitter, 118; com-
mon emitter cascade, 139
A-parameter equivalent circuit, 85, 89
Half power points, 167
Half-wave rectification, 43
Hartley oscillator, 237
High input impedance, 208
Holding current, 348
Hole, 3
Hole-electron-pair, 1 1
Hole storage, 25
Hole transfer, 5
Hybrid 1C, 151
Hybrid parameters, 84
Hyperabrupt junction, 423
W 266, 271
Incremental resistance, 23, 33
Input characteristics (See common base,
common collector, or common
emitter)
Input resistance, 86
Insulated gate FET, 278
Insulator, 8, 9
Integrated circuits (IC), 150, 182
amplifiers, 201; capacitors, 153;
cathode sputtering, 150; components,
152; data sheet, 201, 202; differential
amplifier, 191; diodes, 152; dual-in-
line, 155; fabrication, 150; flat pack,
155; hybrid, 151; monolithic, 150;
multichip, 151; operational amplifier,
201; packaging, 154; parasitic com-
ponents, 152; printed thin film, 150;
resistors, 153; thick film, 150; thin
film, 150; TO can, 155; transistor,
152; vacuum evaporation, 150
Intrinsic semiconductor, 9
Intrinsic stand-off ratio, 370
Inverting amplifier, 209
Inverting input, 196
Ion, 2
Ionic bonding, 7
Ionization:
by collision, 247; by electric field, 246
Junction field effect transistor (JFET),
262
Junction transistor (bipolar), 65
Lambda diode, 432
Latching, 346
Lazer diode, 407
Light-emitting diode (LED), 398
Light units, 381
Line regulation, 255
Liquid-crystal display, 401
dynamic scattering, 401 ; field effect,
402; reflective type, 401; transmittive
type, 401
Load regulation, 255
Logic gates, 56
Lumen, 381
Luminous flux, 381
Majority charge carriers, 1 1, 68
Metal oxide semiconductor FET
(MOSFET), 278
Metallic bonding, 7
Microalloy transistor, 147
Miller effect, 169, 312
Milliwatts per sq cm, 381
489
Index
490
Index
Minority charge carriers, 1 1 , 68
Mobility (of charge carriers), 6
Monolithic IC, 150
MOSFET, 278
Mu (/i), 447
Multichip IC, 151
Multimorph, 422
Multistage amplifiers, 182
n-channel FET, 262
n-type semiconductor, 10
Negative ion, 2
Negative resistance:
tunnel diode, 333; unijunction tran-
sistor, 366
Negative temperature coefficient, 11,
427
Neutrons, 2
Noise, 171
calculations, 172; factor, 173; figure,
173; spot noise figure, 173; thermal,
171
Non-inverting amplifier, 206
Non-inverting input, 196
npn transistor, 65
Nucleus, 1
Offset current, 203
Offset voltage, 203
Open loop gain, 202
Operating point ( See dc bias point)
Operational amplifier, 201
common mode rejection ratio, 202;
differential voltage gain, 202; input
bias current, 203; input offset current,
203; input offset voltage, 203; input
resistance, 203; input unbalance cur-
rent, 203; open loop gain, 202
Optoelectronic coupler, 405
Optoelectronic devitfcs, 380
OR gate, 56
Oscillator:
crystal, 420; colpitts, 234; hartley,
237; phase shift, 230; Wein bridge,
240
Oscilloscope, 463
Output conductance, 86
Oxide coated cathode, 438
/> -channel FET, 268
p-type semiconductor, 10
Parallel amplifier, 335
Parasitic junctions, 153
Peak repetitive current, 48
Pentode vacuum tube, 460
amplification factor, 461; biasing,
461; plate characteristics, 461; plate
resistance, 461; remote cut-off, 462;
sharp cut-off, 462; suppressor grid,
460; symbol, 461; transconductance,
460; variable mu pentode, 462
Phase control of SCR, 352, 354
Phase shift oscillator, 230
Photocathode, 382
Photoconductive cell, 384
applications, 388; cadmium selenide,
385; cadmium sulfide, 385; character-
istics, 385; dark resistance, 384; re-
sponse time, 385; spectral response,
386; symbol, 385
Photodarlington, 394
Photodetector, 394
Photodiode, 388
characteristics, 389; dc load line, 390;
photoconductive operation, 389; pho-
tovoltaic operation, 390; symbol, 390
Photoemissive device; 380, 382
Photofet, 397
Photomultiplier tube, 382
Phototransistor, 394
Photovoltaic device, 380, 390, 392
Piecewise linear characteristics, 38, 333
Piezoelectric crystal, 414
atomic structure, 415; crystal cuts,
417; drive power, 421; electrical axis,
416; equivalent circuit, 418;
mechanical axis, 416; optical axis,
416; oscillators, 420; oven, 420; over-
tone operation, 419; parallel reso-
nance, 419; Q, fac 1011 * 419; quartz,
416; rochelle salts, 416; series reso-
nance, 419; synthetic piezoelectric
devices, 421; tourmaline, 416; trans-
ducer, 422
Planar transistor, 149
Plate, 438
Plate characteristics:
vacuum diode, 439; pentode, 416;
tetrode, 459; triode, 442, 443; in-
junction, 16; barrier potential, 18;
capacitances, 25; depletion region,
Plate characteristics ( Contd. )
18, 19; equivalent circuit, 25; forward
characteristics, 22; forward resistance,
23; reverse breakdown, 21; reverse
characteristics, 21; reverse resistance,
20; reverse saturation current, 20;
temperature effects, 24
fmp transistor, 65
fmpn devices, 344
Polycrystalline material, 144
Positive ion, 2
Power dissipation in transistors, 163
Programmable UJT (PUT), 375
Proton, 2
Punch-through, 76, 144
Push-pull, 218
PUT, 375
d factor, 419, 423
Q, point (See dc bias point)
Quiescent point ( See dc bias point)
r-parameters, 83
Reach-through, 76, 144
Recombination, 11, 68
Rectifier:
bridge, 50; full wave, 49; half wave,
43; smoothing circuit, 46, 51
Reference diode, 245
Reflected load, 213
Regulator (voltage), 252, 256
emitter follower, 257; line regulation,
255; load regulation, 255; output im-
pedance, 253; series, 257; stabiliza-
tion ratio, 253
Relaxation oscillator, 358, 371
Reservoir capacitor, 46, 51
Resistivity of semiconductor, 9
Resonance frequency, 231, 419
Reverse breakdown, 33, 40, 245
Reverse recovery time, 25, 54
Reverse saturation current, 20, 30
Reverse transfer ratio, 86
Ripple waveform, 45
Rise time, 178
Saturation region, 76, 176
Saturation voltage, 144, 148, 176
SCR, 344
Screen grid, 458
Secondary emission, 382, 459
Self bias, 102, 293, 296
Semiconductor, 8, 9
Semiconductor diode (See Diode)
Series amplifier, 341
Series clipper, 56
Series regulator, 257
Seven segment display, 399
Shell, 3
Shockley diode, 355
Shunt clipper, 56
Silicon, 3
Silicon atom, 3
Silicon bilateral switch (SBS), 359
Silicon controlled rectifier (SCR), 344
average forward current, 348; char-
acteristics, 347; control circuits, 349,
374; data sheets, 349, 350; equivalent
circuit, 345; forward blocking region,
348; forward blocking voltage, 348;
forward breakover voltage, 347; for-
ward conduction voltage, 347; for-
ward leakage current, 345; gate
current, 346; holding current, 348;
latching, 346; parameters, 346; peak
surge current, 348; phase control,
352, 354; pulse control, 349; reverse
blocking current, 346; reverse block-
ing region, 346; reverse blocking volt-
age, 346; reverse breakdown voltage,
346; reverse leakage current, 346;
RMS forward current, 348; symbol,
345; two transistor equivalent circuit,
345; UJT control, 374
Silicon controlled switch (SGS), 360
Silicon unilateral switch (SUS), 359
Single crystal material, 145
Smoothing circuit, 46, 51
Solar cell, 392
Solar energy converter, 392
Source follower, 313
Spectral response, 380
Stability factor, 107
Stabilization ratio, 253
Storage time, 178
Stray capacitance, 167
Superbeta circuit, 223
Suppressor grid, 460
Surge current (of diode), 48
Surge limiting resistor, 48
Synthetic piezoelectric devices, 421
491
Index
492
Index
T-equivalent circuit, 83
Temperature coefficient, 23, 427
Tetrode vacuum tube, 457
characteristics, 458; screen grid, 458
Thermal noise, 171
Thermal runaway, 107
Thermal stability, 107
Thermistor, 427
applications, 430, 431; characteristics,
429; construction, 427; resistance,
428; temperature coefficient, 427
Thick film IC, 150
Thin film IG, 150
Thoriated tungsten, 438
Threshold frequency, 382
Threshold wavelength, 382
Thyristor, 344
Transadmittance, 273
T ransconductance :
FET, 272; pentode, 460; triode, 446
Transfer characteristics:
FET, 267; triode, 444
Transformer coupled amplifier, 211, 216
Transistor (bipolar):
alloy, 146; alpha, 70; amplifier, 116,
125, 131; annular, 149; beta, 72;
base, 65; biasing, 93; breakdown, 76,
144; capacitances, 83, 162, 170; char-
acteristics ( See Common base, Com-
mon collector, Common emitter);
collector-to-base bias, 100; construc-
tion, 143; current gain, 71, 86, 143;
cut-off, 176; cut-off frequency, 167;
data sheets, 158; dc load line, 94;
emitter current bias, 102; equivalent
circuits, 83; fabrication, 143; fixed
current bias, 98; forward current
transfer ratio, 71, 72; frequency re-
sponse, 144, 176; graphical analysis,
94, 111; h/?£-, 72, 86; high power, 143;
A-parameters, 84; hybrid equivalent
circuit, 85; junction dissipation, 147;
noise, 171; npn, 65; packages, 155;
pnp, 65; planar, 147; power dissipa-
tion, 163; power dissipation curve,
164; r-parameters, 83; saturation
voltage, 176; self bias, 102; stability
factor, 107; switching, 144, 175; sym-
bols, 73; thermal runaway, 107; ther-
mal stability, 107; voltages, 73
Transistor types:
alloy, 146; annular, 149; diffused
planar, 147; epitaxial mesa, 148;
mesa, 148; microalloy, 147
Transit time, 168
TRIAC, 354
Triode (See Vacuum triode)
TO can, 154
Tungsten, 438
Tunnel diode, 327
biasing, 335; characteristics, 332; dc
load line, 340; energy band diagrams,
328, 330, 331; equivalent circuit, 334;
forward biased, 329; forward volt
drop, 332; negative resistance, 333;
parallel amplifier, 335; parameters,
332; peak current, 332; peak voltage,
332; piecewise linear characteristics,
333; resistive cut-off frequency, 355;
reverse biased, 329; self resonant
frequency, 335; symbols, 332; valley
current, 332; valley voltage, 332
Tunneling, 328
Turn-off time, 178
Turn-on time, 178
Unijunction transistor (UJT), 364
characteristics, 366; control of SCR,
374; cut-off region, 366; data sheet,
368; double base diode, 364; emitter
reverse current, 365; emitter satura-
tion voltage, 370; equivalent circuit,
365; interbase resistance, 367; intrin-
sic stand-off ratio, 370; modulated
interbase current, 37 1 ; negative resis-
tance region, 366; programmable
UJT (PUT), 375; relaxation oscilla-
tor, 371; saturation region, 367;
saturation resistance, 366; specifica-
tion, 367; symbol, 366; temperature
coefficient, 367; valley current, 366,
371; valley voltage, 366
Unilateral four-layer diode, 359
Vacuum diode, 438
anode, 438; applications, 440;
barium oxide, 438; cathode, 438;
characteristics, 439; construction,
438; filament, 438; plate, 438; plate
current, 438; plate voltage, 438;
Vacuum diode ( Contd . )
space charge limited region, 439;
strontium oxide, 438; temperature
limited region, 439; thoriated tungs-
ten, 438; tungsten, 438
Vacuum triode, 441
amplification factor ( p), 447 ; biasing,
454; characteristics, 442, 443; con-
struction, 442; grid, 441; interelec-
trode capacitance, 457; parameters,
445; plate resistance, 445; transcon-
ductance, 446
Valence band, 4
Valence shell, 3
Varactor diode, 422
Variable voltage capacitor diode, 422;
abrupt junction, 423; capacitive
tuning ratio, 423; characteristics, 425;
doping profile, 424; hyperabrupt
junction, 423; factor, 423
Varicap, 422
V-FET, 282
Virtual earth, 209
Virtual ground, 209
Voltage follower, 204
Voltage multiplier, 58
Voltage reference diode, 245
Voltage regulator {See Regulators)
WC diode, 422
Wein bridge oscillator, 240
Y„, 273
Y„, 274
Zener breakdown, 245
Zener diode, 245
breakdown voltage, 246; characteris-
tics, 248; compensated diode, 251;
constant current circuit, 257; data
sheet; 249; dynamic impedance, 249;
equivalent circuit, 249; overvoltage
protection, 259; parameters, 247;
symbol, 248; temperature coefficient,
251; voltage regulator, 252, 256, 257
493
Index
0 - 8359 - 1634-0
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